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Edt Inetrview Q&a

EDT INTERVIEW Q&A

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440 views3 pages

Edt Inetrview Q&a

EDT INTERVIEW Q&A

Uploaded by

ctulasi1411
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Enhanced Deterministic Test (EDT) is a sophisticated technique used in DFT to improve test

coverage and efficiency. Here are some common interview questions and answers related to
EDT:

1. What is Enhanced Deterministic Test (EDT)?

Answer: Enhanced Deterministic Test (EDT) is a technique used in DFT to enhance the
efficiency of deterministic testing by compressing test data. It aims to reduce the volume of test
data while maintaining or improving fault coverage. EDT uses on-chip hardware to decompress
the compressed test vectors during testing.

2. How does EDT differ from traditional scan-based testing?

Answer: Traditional scan-based testing uses full scan vectors that require significant storage and
application time. EDT, on the other hand, uses compressed test data and decompresses it on-chip,
reducing the amount of test data storage and speeding up the test process. This leads to lower test
costs and faster testing.

3. What are the key components of an EDT architecture?

Answer: The key components of an EDT architecture include:

 Compressor: Compresses the test vectors to reduce the volume of test data.
 Decompressor: Decompresses the compressed test data on-chip during testing.
 Scan Chains: Standard scan chains used to shift test data in and out.
 Control Logic: Manages the operation of the compressor and decompressor.

4. What are the benefits of using EDT in testing?

Answer: Benefits of using EDT include:

 Reduced test data volume and storage requirements.


 Faster test application time due to compressed data.
 Lower test costs due to reduced test time and data handling.
 Improved fault coverage and diagnostic capabilities.

5. How does EDT achieve data compression?

Answer: EDT achieves data compression by using techniques such as:

 Linear Feedback Shift Registers (LFSRs): To generate pseudorandom test patterns.


 Built-In Compression Logic: To compress deterministic test patterns.
 X-Filling: To fill don’t-care bits (X’s) in the test patterns to further optimize
compression.
6. What is X-Filling and how is it used in EDT?

Answer: X-Filling is a technique used in test pattern generation where don’t-care bits (X’s) in
the test patterns are filled with specific values to achieve certain objectives, such as reducing
power consumption or improving test data compression. In EDT, X-Filling helps optimize the
compressed test vectors to maximize the efficiency of the decompression process.

7. What challenges are associated with implementing EDT?

Answer: Challenges associated with implementing EDT include:

 Design Overhead: Adding compression and decompression hardware increases the


design complexity and area overhead.
 Compatibility: Ensuring compatibility with existing test methodologies and tools.
 Debugging: Debugging compressed test patterns can be more complex than traditional
test patterns.
 Power Management: Managing power consumption during the decompression process
to avoid excessive power spikes.

8. Explain the role of Linear Feedback Shift Registers (LFSRs) in EDT.

Answer: In EDT, LFSRs are used to generate pseudorandom test patterns that serve as the basis
for compressed test data. LFSRs can produce a large number of patterns with minimal hardware,
making them efficient for generating the seeds required for decompression. The patterns
generated by LFSRs can be combined with deterministic patterns to enhance fault coverage.

9. What is the difference between internal and external compression in EDT?

Answer:

 Internal Compression: Refers to the compression logic that is built into the chip itself,
allowing for on-chip decompression during testing. This reduces the amount of test data
that needs to be transferred to and from the tester.
 External Compression: Involves compressing test data externally before loading it onto
the chip. The chip then uses internal decompression logic to apply the test patterns.
External compression primarily reduces data transfer time and storage requirements.

10. How does EDT improve test coverage?

Answer: EDT improves test coverage by enabling the use of more complex and varied test
patterns, including both pseudorandom and deterministic patterns. The decompression process
can generate a larger number of effective test vectors from a smaller set of compressed data,
increasing the likelihood of detecting faults.

11. What is the role of Built-In Self-Test (BIST) in conjunction with EDT?
Answer: BIST is a technique that allows a circuit to test itself using built-in hardware. When
used in conjunction with EDT, BIST can generate and apply compressed test patterns internally,
further reducing the need for external test data and enabling efficient at-speed testing. BIST and
EDT together can enhance overall test coverage and reduce test time.

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