Unit -1 IC Technologies, MOS & Bi CMOS Circuits

UNIT-I

IC Technologies
 Introduction Basic Electrical Properties of
MOS and BiCMOS Circuits
 MOS  IDS - VDS relationships

 PMOS  MOS transistor Threshold

Voltage - VT figure of
 NMOS merit-ω0
 Transconductance-gm, gds;
 CMOS
 Pass transistor
&
 NMOS Inverter, Various
 BiCMOS pull ups, CMOS Inverter

Technologies analysis and design

 Bi-CMOS Inverters
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

INTRODUCTION TO IC TECHNOLOGY
The development of electronics endless with invention of vaccum tubes and associated
electronic circuits. This activity termed as vaccum tube electronics, afterward the evolution of solid
state devices and consequent development of integrated circuits are responsible for the present status
of communication, computing and instrumentation.
• The first vaccum tube diode was invented by john ambrase Fleming in 1904.
• The vaccum triode was invented by lee de forest in 1906.
Early developments of the Integrated Circuit (IC) go back to 1949. German engineer
Werner Jacobi filed a patent for an IC like semiconductor amplifying device showing five
transistors on a common substrate in a 2-stage amplifier arrangement. Jacobi disclosed small
cheap of hearing aids.
Integrated circuits were made possible by experimental discoveries which showed that
semiconductor devices could perform the functions of vacuum tubes and by mid-20th-century
technology advancements in semiconductor device fabrication.
The integration of large numbers of tiny transistors into a small chip was an enormous
improvement over the manual assembly of circuits using electronic components.
The integrated circuits mass production capability, reliability, and building-block approach to
circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete
transistors.

An integrated circuit (IC) is a small semiconductor-based electronic device consisting of

fabricated transistors, resistors and capacitors. Integrated circuits are the building blocks of
most electronic devices and equipment. An integrated circuit is also known as a chip or
microchip.
There are two main advantages of ICs over discrete circuits: cost and performance. Cost is
low because the chips, with all their components, are printed as a unit by photolithography rather
than being constructed one transistor at a time. Furthermore, much less material is used to construct a
packaged IC die than a discrete circuit. Performance is high since the components switch quickly and
consume little power (compared to their discrete counterparts) because the components are small and
positioned close together. As of 2006, chip areas range from a few square millimeters to around 350
mm2, with up to 1 million transistors per mm
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

IC Invention:

Inventor Year Circuit Remark

Fleming 1904 Vacuum tube diode large expensive, power-

hungry, unreliable
1906 Vacuum triode
William Shockley 1945 Semiconductor replacing --
(Bell labs) vacuum tube

Bardeen and 1947 Point Contact transfer Driving factor of growth of

Brattain and the VLSI technology
Shockley (Bell labs) resistance device “BJT”

Werner Jacobi 1949 1st IC containing amplifying No commercial use reported

(Siemens AG) Device 2stage amplifier

Shockley 1951 Junction Transistor “Practical form of

transistor”
Jack Kilby July 1958 Integrated Circuits F/F Father of IC design
With 2-T Germanium slice
(Texas and gold wires
Instruments)
Noyce Fairchild Dec. 1958 Integrated Circuits Silicon “The Mayor of Silicon
Semiconductor Valley”

Kahng Bell Lab 1960 First MOSFET Start of new era for
semiconductor industry

Fairchild 1061 First Commercial

Semiconductor
And Texas IC
Frank Wanlass 1963 CMOS

(Fairchild
Semiconductor)
Federico Faggin 1968 Silicon gate IC technology Later Joined Intel to lead
first CPU Intel 4004 in 1970
2
(Fairchild 2300 T on 9mm
Semiconductor)
Zarlink Recently M2A capsule for take photographs of
Semiconductors endoscopy digestive tract 2/sec.
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Moore’s Law:

 Gordon E. Moore - Chairman Emeritus of Intel Corporation

 1965 - observed trends in industry - of transistors on ICs vs release dates
 Noticed number of transistors doubling with release of each new IC generation
 Release dates (separate generations) were all 18-24 months apart

“The number of transistors on an integrated circuit will double every 18 months”

The level of integration of silicon technology as measured in terms of number of devices per IC
Semiconductor industry has followed this prediction with surprising accuracy.
IC Technology:

• Speed / Power performance of available technologies

• The microelectronics evolution

• SIA Roadmap

• Semiconductor Manufacturers 2001 Ranking

Circuit Technology

IC Technology

Bipolar CMOS BiCMOS SOI SiGe GaAs

Category BJT CMOS

Lower
Power Moderate less Power
Dissipation
Dissipation to High
Speed Faster Fast Appr. High
Equal rise packing
Gm 4ms 0.4ms and fall Why density
time CMOS
Switch poor Good
implementation ?
Technology slower Faster Fully
restored
Scale down
improvement more easily
logic levels
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Scale of Integration:
 Small scale integration(SSI) --1960

The technology was developed by integrating the number of transistors of 1-100

on a single chip. Ex: Gates, flip-flops, op-amps.

 Medium scale integration(MSI) --1967

The technology was developed by integrating the number of transistors of 100-

1000 on a single chip. Ex: Counters, MUX, adders, 4-bit microprocessors.

 Large scale integration(LSI) --1972

The technology was developed by integrating the number of transistors of 1000-

10000 on a single chip. Ex:8-bit microprocessors,ROM,RAM.

 Very large scale integration(VLSI) -1978

The technology was developed by integrating the number of transistors of 10000-

1Million on a single chip. Ex:16-32 bit microprocessors, peripherals,

complimentary high MOS.

 Ultra large scale integration(ULSI)

The technology was developed by integrating the number of transistors of 1Million-

10 Millions on a single chip. Ex: special purpose processors.

 Giant scale integration(GSI)

The technology was developed by integrating the number of transistors of above 10

Millions on a single chip. Ex: Embedded system, system on chip.

 Fabrication technology has advanced to the point that we can put a complete system on a
single chip.
 Single chip computer can include a CPU, bus, I/O devices and memory.
 This reduces the manufacturing cost than the equivalent board level system with higher
performance and lower power.
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

MOS TECHNOLOGY:

MOS technology is considered as one of the very important and promising technologies in
the VLSI design process. The circuit designs are realized based on pMOS, nMOS, CMOS and
BiCMOS devices.
The pMOS devices are based on the p-channel MOS transistors. Specifically, the pMOS
channel is part of a n-type substrate lying between two heavily doped p+ wells beneath the
source and drain electrodes. Generally speaking, a pMOS transistor is only constructed in
consort with an NMOS transistor.
The nMOS technology and design processes provide an excellent background for other
technologies. In particular, some familiarity with nMOS allows a relatively easy transition to
CMOS technology and design.
The techniques employed in nMOS technology for logic design are similar to GaAs technology..
Therefore, understanding the basics of nMOS design will help in the layout of GaAs circuits
In addition to VLSI technology, the VLSI design processes also provides a new degree of
freedom for designers which helps for the significant developments. With the rapid advances in
technology the the size of the ICs is shrinking and the integration density is increasing.
The minimum line width of commercial products over the years is shown in the graph below.

The graph shows a significant decrease in the size of the chip in recent years which implicitly
indicates the advancements in the VLSI technology.
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

MOS Transistor Symbol:

ENHANCEMENT AND DEPLETION MODE MOS TRANSISTORS

MOS Transistors are built on a silicon substrate. Silicon which is a group IV material is the
eighth most common element in the universe by mass, but very rarely occurs as the pure free element
in nature. It is most widely distributed in dusts, sands, planetoids, and planets as various forms of
silicon dioxide (silica) or silicates. It forms crystal lattice with bonds to four neighbours. Silicon is a
semiconductor. Pure silicon has no free carriers and conducts poorly. But adding dopants to silicon
increases its conductivity. If a group V material i.e. an extra electron is added, it forms an n-type
semiconductor. If a group III material i.e. missing electron pattern is formed (hole), the resulting
semiconductor is called a p-type semiconductor.
A junction between p-type and n-type semiconductor forms a conduction path. Source and
Drain of the Metal Oxide Semiconductor (MOS) Transistor is formed by the “doped” regions on the
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

surface of chip. Oxide layer is formed by means of deposition of the silicon dioxide (SiO2) layer
which forms as an insulator and is a very thin pattern. Gate of the MOS transistor is the thin layer of
“polysilicon (poly)”; used to apply electric field to the surface of silicon between Drain and Source,
to form a “channel” of electrons or holes. Control by the Gate voltage is achieved by modulating the
conductivity of the semiconductor region just below the gate. This region is known as the channel.
The Metal–Oxide–Semiconductor Field Effect Transistor (MOSFET) is a transistor which is a
voltage-controlled current device, in which current at two electrodes, drain and source is controlled
by the action of an electric field at another electrode gate having in-between semiconductor and a
very thin metal oxide layer. It is used for amplifying or switching electronic signals.
The Enhancement and Depletion mode MOS transistors are further classified as N-type named
NMOS (or N-channel MOS) and P-type named PMOS (or P-channel MOS) devices. Figure 1.5
shows the MOSFETs along with their enhancement and depletion modes.

Figure 1.5: (a) Enhancement N-type MOSFET (b) Depletion N-type MOSFET

Figure 1.5: (c) Enhancement P-type MOSFET (d) Depletion P-type MOSFET

The depletion mode devices are doped so that a channel exists even with zero voltage from gate to
source during manufacturing of the device. Hence the channel always appears in the device. To
control the channel, a negative voltage is applied to the gate (for an N-channel device), depleting the
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

channel, which reduces the current flow through the device. In essence, the depletion-mode device is
equivalent to a closed (ON) switch, while the enhancement-mode device does not have the built in
channel and is equivalent to an open (OFF) switch. Due to the difficulty of turning off the depletion
mode devices, they are rarely used
Working of Enhancement Mode Transistor
The enhancement mode devices do not have the in-built channel. By applying the required potentials,
the channel can be formed. Also for the MOS devices, there is a threshold voltage (Vt), below which
not enough charges will be attracted for the channel to be formed. This threshold voltage for a MOS
transistor is a function of doping levels and thickness of the oxide layer.
Case 1: Vgs = 0V and Vgs < Vt
The device is non-conducting, when no gate voltage is applied (Vgs = 0V) or (Vgs < Vt) and also drain
to source potential Vds = 0. With an insufficient voltage on the gate to establish the channel region as
N-type, there will be no conduction between the source and drain. Since there is no conducting
channel, there is no current drawn, i.e. Ids = 0, and the device is said to be in the cut-off region. This
is shown in the Figure 1.7 (a).

Figure 1.7: (a) Cut-off Region

Case 2: Vgs > Vt
When a minixmum voltage greater than the threshold voltage Vt (i.e. Vgs > Vt) is applied, a high
concentration of negative charge carriers forms an inversion layer located by a thin layer next to the
interface between the semiconductor and the oxide insulator. This forms a channel between the
source and drain of the transistor. This is shown in the Figure 1.7 (b).

Figure 1.7: (b) Formation of a Channel

 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

A positive Vds reverse biases the drain substrate junction, hence the depletion region around the
drain widens, and since the drain is adjacent to the gate edge, the depletion region widens in the
channel. This is shown in Figure 1.7 (c). This results in flow of electron from source to drain
resulting in current Ids.. The device is said to operate in linear region during this phase. Further
increase in Vds, increases the reverse bias on the drain substrate junction in contact with the inversion
layer which causes inversion layer density to decrease. This is shown in Figure 1.7 (d). The point at
which the inversion layer density becomes very small (nearly zero) at the drain end is termed pinch-
off. The value of Vds at pinch-off is denoted as Vds,sat. This is termed as saturation region for the
MOS device. Diffusion current completes the path from source to drain in this case, causing the
channel to exhibit a high resistance and behaves as a constant current source.

Vgs > Vt Vgs > Vt

VSB = 0 VDS > 0 VSB = 0 VDS > 0

ID > 0 ID > 0
n+ n+ n+ n+

P Substrate P Substrate

Body Body
Figure 1.7: (c) Linear Region. (d) Saturation Region

The MOSFET ID versus VDS characteristics (V-I Characteristics) is shown in the Figure 1.8. For VGS
< Vt, ID = 0 and device is in cut-off region. As VDS increases at a fixed VGS, ID increases in the linear
region due to the increased lateral field, but at a decreasing rate since the inversion layer density is
decreasing. Once pinch-off is reached, further increase in VDS results in increase in ID; due to the
formation of the high field region which is very small. The device starts in linear region, and moves
into saturation region at higher VDS.
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

NMOS FABRICATION

The following description explains the basic steps used in the process of fabrication.
(a) The fabrication process starts with the oxidation of the silicon substrate.
It is shown in the Figure 1.9 (a).
(b) A relatively thick silicon dioxide layer, also called field oxide, is created on the surface of the
substrate. This is shown in the Figure 1.9 (b).
(c) Then, the field oxide is selectively etched to expose the silicon surface on which the MOS
transistor will be created. This is indicated in the Figure 1.9 (c).
(d) This is followed by covering the surface of substrate with a thin, high-quality oxide layer, which
will eventually form the gate oxide of the
MOS transistor as illustrated in Figure 1.9 (d).
(e) On top of the thin oxide, a layer of polysilicon (polycrystalline silicon) is deposited as is shown in
the Figure 1.9 (e). Polysilicon is used both as gate electrode material for MOS transistors and also as
an interconnect medium in silicon integrated circuits. Undoped polysilicon has relatively high
resistivity. The resistivity of polysilicon can be reduced, however, by doping it with impurity atoms.
(f) After deposition, the polysilicon layer is patterned and etched to form the interconnects and the
MOS transistor gates. This is shown in Figure 1.9 (f).
(g) The thin gate oxide not covered by polysilicon is also etched along, which exposes the bare
silicon surface on which the source and drain junctions are to be formed (Figure 1.9 (g)).
(h) The entire silicon surface is then doped with high concentration of impurities, either through
diffusion or ion implantation (in this case with donor atoms to produce n-type doping). Diffusion is
achieved by heating the wafer to a high temperature and passing the gas containing desired impurities
over the surface. Figure 1.9 (h) shows that the doping penetrates the exposed areas on the silicon
surface, ultimately creating two n-type regions (source and drain junctions) in the p-type substrate.
The impurity doping also penetrates the polysilicon on the surface, reducing its resistivity.
(i) Once the source and drain regions are completed, the entire surface is again covered with an
insulating layer of silicon dioxide, as shown in
Figure 1.9 (i).(j) The insulating oxide layer is then patterned in order to provide contact windows for
the drain and source junctions, as illustrated in Figure 1.9 (j).
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

CMOS FABRICATION:

CMOS fabrication can be accomplished using either of the three technologies:

• N-well technologies/P-well technologies

• Twin well technology
• Silicon On Insulator (SOI)

The fabrication of CMOS can be done by following the below shown twenty steps, by which CMOS
can be obtained by integrating both the NMOS and PMOS transistors on the same chip substrate. For
integrating these NMOS and PMOS devices on the same chip, special regions called as wells or tubs
are required in which semiconductor type and substrate type are opposite to each other.
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

A P-well has to be created on a N-substrate or N-well has to be created on a P-substrate. In this

article, the fabrication of CMOS is described using the P-substrate, in which the NMOS transistor is
fabricated on a P-type substrate and the PMOS transistor is fabricated in N-well.

The fabrication process involves twenty steps, which are as follows:

N-Well Process
Step1: Substrate

Primarily, start the process with a P-substrate.

Step2: Oxidation

The oxidation process is done by using high-purity oxygen and hydrogen, which are exposed in an
oxidation furnace approximately at 1000 degree centigrade.

Step3: Photoresist

A light-sensitive polymer that softens whenever exposed to light is called as Photoresist layer.
It is formed.

Step4: Masking

The photoresist is exposed to UV rays through the N-well mask

Step5: Photoresist removal

 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

A part of the photoresist layer is removed by treating the wafer with the basic or acidic solutio n.

Step6: Removal of SiO2 using acid etching

The SiO2 oxidation layer is removed through the open area made by the removal of photoresist using
hydrofluoric acid.

Step7: Removal of photoresist

The entire photoresist layer is stripped off, as shown in the below figure.

Step8: Formation of the N-well

By using ion implantation or diffusion process N-well is formed.

Step9: Removal of SiO2

Using the hydrofluoric acid, the remaining SiO2 is removed.

Step10: Deposition of polysilicon

 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Chemical Vapor Deposition (CVD) process is used to deposit a very thin layer of gate oxide.

Step11: Removing the layer barring a small area for the Gates

Except the two small regions required for forming the Gates of NMOS and PMOS, the remaining
layer is stripped off.

Step12: Oxidation process

Next, an oxidation layer is formed on this layer with two small regions for the formation of the gate
terminals of NMOS and PMOS.

Step13: Masking and N-diffusion

By using the masking process small gaps are made for the purpose of N -diffusion.

The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for the formation
of the terminals of NMOS.

Step14: Oxide stripping

 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

The remaining oxidation layer is stripped off.

Step15: P-diffusion

Similar to the above N-diffusion process, the P-diffusion regions are diffused to form the terminals of
the PMOS.

Step16: Thick field oxide

A thick-field oxide is formed in all regions except the terminals of the PMOS and NMOS.

Step17: Metallization

Aluminum is sputtered on the whole wafer.

Step18: Removal of excess metal

The excess metal is removed from the wafer layer.

Step19: Terminals

The terminals of the PMOS and NMOS are made from respective gaps.

Step20: Assigning the names of the terminals of the NMOS and PMOS
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Fabrication of CMOS using P-well process

Among all the fabrication processes of the CMOS, N-well process is mostly used for the fabrication
of the CMOS. P-well process is almost similar to the N-well. But the only difference in p-well
process is that it consists of a main N-substrate and, thus, P-wells itself acts as substrate for the N-
devices.

Twin tub-CMOS Fabrication Process

In this process, separate optimization of the n-type and p-type transistors will be provided. The
independent optimization of Vt, body effect and gain of the P-devices, N-devices can be made
possible with this process.
Different steps of the fabrication of the CMOS using the twintub process are as follows:
 Lightly doped n+ or p+ substrate is taken and, to protect the latch up, epitaxial layer is used.
 The high-purity controlled thickness of the layers of silicon are grown with exact dopant
concentrations.
 The dopant and its concentration in Silicon are used to determine electrical properties.
 Formation of the tub
 Thin oxide construction
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

 Implantation of the source and drain

 Cuts for making contacts
 Metallization
By using the above steps we can fabricate CMOS using twin tub process method.
Silicon-on-Insulator (SOI) CMOS Process
Rather than using silicon as the substrate material, technologists have sought to use an insulating
substrate to improve process characteristics such as speed and latch-up susceptibility. The SOI
CMOS technology allows the creation of independent, completely isolated nMOS and pMOS
transistors virtually side-by-side on an insulating substrate. The main advantages of this technology
are the higher integration density (because of the absence of well regions), complete avoidance of the
latch-up problem, and lower parasitic capacitances compared to the conventional p & n-well or twin-
tub CMOS processes. A cross-section of nMOS and pMOS devicesusing SOI processis
shown below.

The SOI CMOS process is considerably more costly than the standard p & n-well CMOS process.
Yet the improvements of device performance and the absence of latch-up problems can justify its
use, especially for deep-sub-micron devices.
 Basic VLSI Design )

2.1 DRAIN-TO-SOURCE CURRENT Ids versus VOLTAGE Yds

RELATIONSHIPS

The whole concept of the MOS transistor evolves from the use of a voltage on the gate to
induce a charge in the channel between source and drain, which may then be caused to move
from source to drain under the influence of an electric field created by voltage Vds applied
between drain and source. Since the charge induced is dependent on the gate to source
voltage Vgs• then Ids is dependent on both Vgs and Vds· Consider a structure, as in Figure 2.1,
in which" electrons will flow source to drain:

I = _I = Charge induced in channel (QJ

ds sd Electron transit. hme
. ('t ) (2.1)

First, transit time:

Length of channel (L)
'tsd = --=---------'-~
Velocity (v)

Gate

FIGURE 2.1 nMOS transistor structure.

but velocity

where
fl = electron or hole mobility (surface)
Eds = electric field (drain to source)
Now

- vd.s
Eds - -
L
( Basic Electrical Properties of MOS and BiCMOS Circuits
••
so that

v = JlVds
L
Thus

(2 .2)

Typical values of Jl at room temperature are:

lln * 650 cm N 2
sec (surface)
Jlp * 240 cm N 2
sec (surface)

2.1.1 The Non-saturated Region

Charge induced in channel due to gate voltage is due to the voltage difference between the
gate and the channel, Vgs (assuming substrate connected to source). Now note that the voltage
along the channel varies linearly with distance X from the source due to the IR drop in the
channel (see Figure 1.5) and assuming that the device is not saturated then the average value
is VtJ/2. Furthermore, the effective gate voltage Vg = Vgs - V1 where V, is the threshold
voltage needed to invert the charge under the gate and establish the channel.
Note that the charge/unit area = EgE-;nsf.o. Thus induced charge
Qc = EgE-;nsf.oWL
where
Eg = average electric field gate to channel
E;ns = relative permittivity of insulation between gate and channel
Eo = permittivity of free space
(Note: Eo = 8.85 x 10- 14 F cm- 1; E;ns * 4.0 for silico~~ioxide)
Now

Eg-
.- ({V~ - V,) - v;) .
D
where D = oxide thickness.
Thus

Qc = WLE;nsEo
D
((V _ V.) _
gs t
Vds)
(2 .3)
2

Now, combining equations (2.2) and (2.3) in equation (2.1), we have

I
ds
=EinsEoJ..LW
D L
((V - V.)-
gs t
Vds)v
2 ds
*.1:1 Basic VLSI Design )

or

(2.4)

in the non-saturated or resistive region where Vds < V1s - V, and

K = E;ns£oJ.t
D
The factor W/L is, of course, contributed by the geometry and it is common practice to
write

~=K­
w
L
so that

1.. =~(w .. - V.> v., - v!) (2.4a)

which is an alternative form of equation (2:4).

Noting that gate/channel capacitance

£1 ,:_W£
C = "'..., (parallel plate)
' D
we also have

K=-
c,J.l
WL
so that

(2.4b)

which is a further alternative form of equation (2.4).

Sometimes it is convenient to use gate capacitance per unit area C0 (which is often
denoted C0 _t) rather than C1 in this and other expressions. Noting that
C1 = C0 WL
we may also write

(2.4c)
(

2.1.2
Basic Electrical Properties of MOS and BiCMOS Circuits

The Saturated Region

.,.
Saturation begins when Vds = Vgs - V, since at this point the IR drop in the channel equals
the effective gate to channel voltage at the drain and we may assume that the current remains
fairly constant as Vds increases further. Thus

(2.5)

or, we may write

(2.5a)
or
Cgll
-
I tb- --2 (vgs - ~) 2 (2.5b)
2L
We may also write

(2.5c)

The expressions derived for Ids hold for both enhancement and depletion mode devices, but
it should be noted that the threshold voltage for the nMOS depletion mode device (denoted
as v,d) is negative.
Typical characteristics for nMOS transistors are given in Figure 2.2. pMOS transistor
characteristics are similar, with suitable reversal of polarity.

2.2 ASPECTS OF MOS TKArfSISTOR THRESHOLD VOLTAGE Yt

The gate structure of aMOS transistor consists, electrically, of charges stored in the dielectric
layers and in the surface to surface interfaces as well as in the substrate itself.
Switching an enhancement mode MOS transistor from the off to the on state consists
in applying sufficicmt gate voltage to neutralize these charges and enable the underlying
silicon to undergo an inversion due to the electric field from the gate.
Switching a depletion mode nMOS transistor from the on to the off state consists in
applying enough voltage to the gate to add to the stored charge and invert the 'n' implant
region to 'p' .
The threshold voltage V, may be expressed as: .

(2.6)

where
Q11 = the charge per unit area in the depletion layer beneath the oxide
Qss = charge density at Si:Si02 interface
·1·1 . Basic VLS/ Design )

'•
~6 •0.3V00

'•
~ Saturation ( v,. > Vg. - V, )
V66 •0
~
~.=-0.1

v66 = -0.31'oo
voo
r Vg.
..............
t Vp

0.5V00 ·v,.
0
I
(a) Depletion mode device

'•
~.=o,av00

'd•
. Saturation ( V.- > V66 - V1 )
Vg. z: 0.5 voo
~
~-l t
vP

Vg.=0.4V00
vP
~
~=0.2V00

0 ~
o.svoo voo
(b) Enhancement mode device

FIGURE 2.2 MOS transistor characteristics .

...
 Basic Electrical Properties of MOS and BiCMOS Circuits
•••
C0 = capacitance per unit gate area
<l>ms = work function difference between gate and Si
<I>JN = Fermi level potential between inverted surface and bulk Si.
Now, for polysilicon gate and silicon substrate, the value of <l>ms is negative but negligible,
and the magnitude and sign of V1 are thus determined by the balance between the remaining

negative term -Qss and the other two terms, both of which are positive. To evaluate V1, each
Co
term is determined as follows:

Qss = (1.5 to 8) X 10-S cou)omb/m2

depending on crystal orientation, and where

Vs8 = substrate bias voltage (negative w.r.t. source for nMOS, positive for pMOS)
q = 1.6 X 10- 19 coulomb
N = impurity concentration in the substrate (NA or ND as appropriate)
£.5 ; = relative permittivity of silicon =;: 11.7
n; = intrinsic electron concentration (1.6 x 10 10/cm 3 at 300°K)
k = Boltzmann's constant = 1.4 x 10- 23 joule/°K
The body effects may also be taken into account since the substrate may be biased with
respect to the source, as shown in Figure 2.3 .

Source Gate Drain

Vss

FIGURE 2.3 Body effect (nMOS device shown).

Increasing Vs8 causes the channel to be depleted of charge carriers and thus the threshold
voltage is raised.
Change in V1 is given by ,~.V1 =;: '((Vs8 ) 112 where '( is a constant which depends on
substrate doping so that the more lightly doped the substrate, the smaller will be the body
effect.
4t4 Basic VLSI Design )

Alternatively, we may write

where V,(O) is the threshold voltage for Vs8 = 0.

To establish the ,magnitude of such effects, typical figures for V1 are as foUows:
For nMOS enhancement mode transistors:

VsB = 0 V; V, = 0.2VDD (= +1 V for VDD = +5 V) } S~ but

negative values
Vs8 = 5 V; V, = 0.3VDD (= +1.5 V for VDD = +5 V) for pMOS
For nMOS depletion mode transistors:
Vsa = 0 V; vtd = -0.7VDD (= -3.5 v for VDD = +5 V)
Vsa = 5 V; Vtd = -0.6VDD (= -3 .0 V for VDD = +5 V)

2.3 MOS TRArtSISTOR TRArtSCOrtDUCTAriCE g, AriD ODTPUI'

COrtDUCTAriCE g,.

Transconductance expresses the relationship between output current Ids and the input voltage
V11 and is defined as

To fmd an expression for g,. in terms of circuit and transistor parameters, consider that
the charge in channel Qc is such that

where 't is transit time. Thus change in current

Now

(from 2.2)

Thus
( Basic Electrical Properties of MOS and BiCMOS Circuits
•••
but change in charge

so that ·

Now

In saturation
vd.r = v"'- v,
c6~
--[!
g. (V., - V,) (2.7)

and substituting for C = E;uEoWL

' D

(2.7a)

Alternatively,
g, = ~(V1s- V,)
It is possible to increase the g, of a MOS device by increasing its width. However, this
will also increase the input capacitance and area occupied.
A reduction in the channel length results in an increase in .COo owing to the higher g,.
However, the gain of the MOS device decreases owing to the strong degradation of the
output resistance = llgds·
The output conductance gd.r can be expressed by

gds oi ='A..Ids
= _.1!....
oV.,
(1)
a -
L
2

Here the strong dependence on the channel length is demonstrated as

for the MOS device.

~ ~------~~~~~~~~~~~~~----~----------------------------------------------

.,, Basic VLSI Design )

2.4 MOS TRArfSISTOR FIGURE OF MERIT ro 0

An indication of frequency response may be obtained from the parameter OOo where

ro0 =Cgm =_!::_

L2 (V
g
gs
- V)
I
(= _1 )
tsd
(2 .8)

This shows that switching speed depends on gate voltage above threshold and on carrier
mobility and inversely as the square of channel length. A fast circuit requires that g"' be as
high as possible.
Electron mobility on a (100) oriented n-type inversion layer surface (11n) is larger than
that on a ( 111) oriented surface, and is in fact about three times as large as hole mobility on
a (111) oriented p-type inversion layer. Surface mobility is also dependent on the effective
gate voltage (V85 - V1).
For faster nMOS circuits, then, one would choose a (100) oriented p-type substrate in
which the inversion layer will have a surface carrier mobility l1n :::= 650 cm2N sec at room
temperature.
Compare this with the typical bulk mobilities
l1n = 1250 cm2/V sec
l1p = 480 cm2/V sec

from which it will be seen that l1s :::= 0.5 (where 11s = surface mobility and 11 =bulk mobility).
11

2.5 THE PASS TRANSISTOR

Unlike bipolar transistors, the isolated nature of the gate allows MOS transistors to be used
as switches in series with lines carrying logic levels in a way that is similar to the use of relay
contacts. This application of the MOS device is called the pass transistor and switching logic
arrays can be formed-for example, an And array as in Figure 2.4.

~0---.. ,----X

T A 8
Tc
1!._= A.B.C (Logic 1 = ~0 - V1 )
X=?

Note.: Means must exist so that X assumes ground potential when A + B + C = 0.

FIGURE 2.4 Pass transistor And gate.
 Basic Electrical Properties of MOS and BiCMOS Circuits

2.6 THE nMOS INVERTER

A basic requirement for producing a complete range of logic circuits is the inverter. This is
needed for restoring logic levels, for Nand and Nor gates, and for sequential and memory
circuits of various forms . In the treatment of the inverter used in this section, the authors
wish to acknowledge the influence of material previously published by Mead and Conway.
The basic inverter circuit requires a transistor with source connected to ground and a
load resistor of some sort connected from the drain to the positive supply rail Vvv· The output
is taken from the drain and the input applied between gate and ground.
Resistors are not conveniently produced on the silicon substrate; even modest values
occupy excessively large areas so that some other form of load resistance is required. A
convenient way to solve this problem is to use a depletion mode transistor as the load, as
shown in Figure 2.5.

vout

--------~--- GNO
FIGURE 2.5 nMOS Inverter.

Now:
• With no current drawn from the output, the currents Ids for both transistors must be
equal.
• For the depletion mode transistor, the gate is connected to the source so it is always
on and only the characteristic curve Vgs = 0 is relevant.
• In this configuration the depletion mode device is called the pull-up (p.u.) and the
enhancement mode device the pull-down (p.d.) transistor.
• To obtain the inverter transfer characteristic we superimpose the Vgs = 0 depletion
mode characteristic curve on the family of curves for the enhancement mode device,
noting that maximum voltage across the enhancement mode device corresponds to
minimum voltage across the depletion mode transistor.
• The points of intersection of the curves as in Figure f-6 give points on the transfer
characteristic, which is of the form shown in Figure 2.7.
• Note that as Vin(=Vgs p.d. transistor) exceeds the p.d. threshold voltage current begins
to flow. The output voltage Vout thus decreases and the subsequent increases in Vin
will cause the p.d. transistor to come out of saturation and become resistive. Note
that the p.u. transistor is initially resistive as the p.d. turns on.
 VgJerih) = 0.8 V00
'{1()f('~.

:>10ftlL!.

'{L 1/'
c ~
lt' Vg.(enh) = 0.4 V00

Vg~(enh) = 0.2 V oo
Vu(enh)
0
... v,.(dep)
0.5 V00 Voo
[OV(dep))

Vd1 (enh) • Voo- Vd1 (dep) • V.,.;1

V1 ,(enh) • V;n . .. intersection points give transfer characteristic

FIGURE 2.6 Derivation of nMOS Inverter transfer characteristic.

v_,

, ., , ~~- v.,
, ,,
,
,,

~d lr:'
' , ,
, ,,
~ I_ //
,,
, ' Increasing
,, Zp.,iZp.tt.
,,
0~----------~~----------~~--~ Vm
v.,.,.o.svoo ~

(>'
FIGURE 2. 7 nMOS Inverter transfer characteristic.

• During transition, the slope of the transfer characteristic determines the gain:
(.fl

,,,
• - avOIII
Gam---
5V;,
 ( Basic Electrical Properties of MOS and BiCMOS Circuits
••
• The po~nt at which Vout = V;, is denoted as V;,v and it will be noted that the transfer
characteristics and V;,v can be shifted by variation of the ratio of pull-up to pull-
down resistances (denoted zp.ulZp.d. where Z is determined by the length to width
ratio of the transistor in question).

2. 7 DETERMINATION OF PULL-UP TO PULL-DOWN RATIO (Zp.u}

Zp.d.) FOR AN nMOS INVERTER DRIVEN BY ANOTHER nMOS
INVERTER

Consider the arrangement in Figure 2.8 in which an inverter is driven from the output of
[. another similar inverter. Consider the depletion mode transistor for which Vgs = 0 under all
conditions, and further assume that in order to cascade inverters without degradation of
levels we are aiming to meet the requirement

v~ v.,.,,

FIGURE 2.8 nMOS inverter driven directly by another inverter.

For equal margins around the inverter threshold, we set V;,v = 0.5 VDD· At this point both
transistors are in saturation and

I = KW
(v - v.,)2
___,gs'----
ds L 2
In the depletion mode

and in the enhancement mode

I ds = K Wp.d.
L
U-:,v -2 V, f smce
. Vgs =
V
inv
p.d.
Equating (since currents are the same) we have

w
_1!3:_ (
w
vmv - v. )2 = -.!!:!!:.... (- v.td )2
L 1L
pd p~
41:1 Basic VLSI Design )

where Wp.d.• Lp.d.• Wp.u.• and Lp.u. are the widths and lengths of the pull-down and pull-up
transistors respectively.
Now write
L L
zp.d. = ___!!:!!:_
W '· z p.u. = --..!!:.!!:....
W
p.d. p.u.
we have

whence

(2.9)

Now we can substitute typical values as follows:

VI= 0.2Vvv; vtd = - 0.6Vvv
Vinv = 0.5Vvv (for equal margins)
thus, from equation (2.9)
06
0.5 =0.2 + ·
Jzp.ulZp.d.
whence

and thus
Zp.ul Zp.d. = 4/1

for an inverter directly driven by an inverter.

2.8 PULL-UP TO PULL-DOWN RATIO FOR AN nMOS INVERTER

DRIVEN THROUGH ONE OR MORE PASS TRANSISTORS

Now consider the arrangement of Figure 2.9 in which the input to inverter 2 comes from the
output of inverter 1 but passes through one or more nMOS transistors used as switches in
series (called pass transistors) .
We are concerned that connection of pass transistors in series will degrade the logic
1 level finto inverter 2 so that the output will not be a proper logic 0 level. The critical
condition is when point A is at 0 volts and B is thus at Vvv. but the voltage into inverter 2
at point C is now reduced from VDD by the threshold voltage of the series pass transistor.
With all pass transistor gates connected to Vvv (as shown in Figure 2.8), there is a loss of
 ( Basic Electrical Properties of MOS and BiCMOS Circuits

Inverter 2
•s•
A
Vou/2

FIGURE 2.9 Pull-up to pull-down ratios for inverting logic coupled by pass transistors.

V1P, however many are connected in series, since no static current flows through them and
there can be no voltage drop in the channels. Therefore, the input voltage to inverter 2 is

V;nz = Vvv- Vtp

where
V1p = threshold voltage for a pass transistor.

We must now ensure that for this input voltage we get out the same voltage as would be the
case for inverter 1 driven with input = Vvv·
Consider inverter 1 (Figure 2.1O(a)) with input = Vvv· If the input is at Vvv. then the
( p.d. transistor T2 is conducting but with a low voltage across it; therefore, it is in its resistive
region represented by R 1 in Figure 2.10. Meanwhile, the p.u. transistor T 1 is in saturation and
is represented as a current source.

Voo
VDD

Depletion mode
r,
+,, r, lz

Depletion mode

t
Voutl
Enhancement
mode

GND GND
(a) Inverter 1 with input= V00 (b) Inverter 2 with input= V00 - V,p

FIGURE 2.10 Equivalent circuits of inverters 1 and 2.

For the p.d. transistor

Ids = K ~p.d.I
p .d .l
[(VDD - V,) Vdsl - v; 1
) (from 2.4)
litI Basic VLSI Design )

·Therefore

. ':,..
Note that Vdrt is small and Vdstl2 may be ignored.
Thus

.
Rt * K1 z p.d.t
Now, for depletion mode p.u. in saturation with V,. = 0

I =Itb =K Wp.i..t ( - V~r~)2

I L p .ll.l 2 (fivm 2.5)

The product

Thus
2
u -I R _ z,.d.t ( 1 -) (V~r~)
,.outl- I I - - - - --
zp.ll.l VDD -:- V, · 2

Consider inverter 2 (Figure 2.10(b)) when input = VDD- Ytp. As for inverter 1

R ... 1 z 1
2 .... K p.d.2 ((VDD - Vtp) - v,

whence

If inv¢er 2 is to have the same output voltage under these conditions then V0111 1 = V0111 2.
That is

Therefore

z,..,.2 = z,...t _....;.(_,VD=D'------'V,-'-)-

zp.d.2 zp.d.t (Voo - V,, - V,)
 ( Basic Electrical Properties of MOS and BiCMOS Circuits
•••
Taking typical values
V, = 0.2Vvv
Vrp = 0.3Vvv*

Therefore

Summarizing for an nMOS inverter:

• An inverter driven directly from the output of another should have a Zp.ulZp.fl. ratio
of~ 4/1.
• An inverter driven through one or more pass transistors should have a Zp.u./Zp.d. ratio
of~ 8/1.
'
't Note: It is the driven, not the driver, whose ratio is affected.

2.9 ALTERMTIVE FORMS OF f'IJLL-UP

Up to now we have assumed that the inverter circuit has a depletion mode pull-up transistor
as its load. There are, however; at least four possible arrangements:
1. Load resistance RL (Figure 2.11 ). This arrangement is not often used because of the
large space requirements of resistors produced in a silicon substrate.

------4---- Voo

FIGUIIIE 2.11 RHistor pull-up.

•tl Basic VLSI Design )

2. nMOS depletion mode transistor pull-up (Figure i .12).

(a) Dissipation is high ,since rail to rail current flows when V;n = logical 1.
(b) Switchlng of output from 1 to 0 begins when V;n exceeds V, of p.d. device.
(c) When switching the output from 1 to 0, the p.u. device is non-saturated initially
and this presents lower resistance through which to charge capacitive loads .

..'
~:
.No curr nt
....
Current
flows
Non-zero output

GNO

FIGURE 2.12 nMOS depletion mode transistor pull-up and transfer characteristic.

3. nMOS enhancement mode pull-up · (Figure 2.13).

(a) Dissipation is high since current flows when V;n =logical 1 (VaG is returned to V00) .
(b) Vout can never reach VDD (logical I) if VGG = V00 as is normally the case.

-.. -- ..... -:-...............+--............ -..... -. -.. -.................. .. -

-------~ ........... .

GNO ...
0
V;n

FIGURE 2.13
v,2

nMOS enhancement mode pull-up and transfer characteristic. ·

--
t
 (

(c)
Basic Electrical Properties of MOS and BiCMOS Circuits

VGG may be derived from a switching source, for example, one phase of a clock,
.,.
so that dissipation can be greatly reduced.
(d) If VGG is higher than VDD then an extra supply rail is required.
4. Complementary transistor pull-up (CMOS) (Figure 2.14).
(a) No current flow either for logical 0 or for logical 1 inputs.
(b) Full logical 1 and 0 levels are presented at the output.
(c) For devices of similar dimensions the p-channel is slower than the n-channel device.

v,n
•
~
'P
' I
-· -----·--------------------------~--------·- ·

,. pon
p
n off

Vout
' non

p off
n

Vss
(a) Circuit (b) Transfer characteristic

Regions
Current
(between 2 3 4 5
rails)

(c) CMOS inverter current versus "'n

.\,.
FIGURE 2.14 Complementary transistor pull-up (CMOS).
lEI Basic VLSI Design )

2.10 THE CMOS INVERTER

The general arrangement and characteristics are illustrated in Figure 2.14. We have seen
(equations 2.4 and 2.5) that the current/voltage relationships for the MOS transistor may be
written

in the resistive region, or

in saturation. In both cases the factor K is a technology-dependent parameter such that

The factor WIL is, of course, contributed by the geometry and it is common practice to
write

so that, for example

I ds = ~2 (Vgs - V.)
I
2

in saturation, and where 1t may be applied to both nMOS and pMOS transistors as follows:

where Wn and Lm WP and LP are the n- and p-transistor dimensions respectively. With regard
to Figures 2.14(b) and 2.14(c), it may be seen that the CMOS inverter has five distinct
regions of operation.
Considering the static conditions first, it may be Seen that in region 1 for which Vi,. =
logic 0, we have the p-lransistor fully turned on while the n-transistor is fully turned off.
Thus no current flows through the _inverter and the output is directly connected to VDD
through the p-transistor. A good logic 1 output voltage is thus present at the output.
In rey:ion 5 V;,. = logic 1, the n-transistor is fully on while the p-transistor is fully off.
Again, no current flows and a good logic 0 appears at the output.
( Basic Electrical Properties of MOS and BiCMOS Circuits
.
.,.,
In region 2 the input voltage has increased to a level which just exceeds the threshold
voltage of the n-transistor. The n-transistor conducts and has a large voltage between source
and drain; so it is in saturation. The p-transistor is also conducting but with only a small
voltage across it, it operates in the unsaturated resistive region. A small current now flows
through the inverter from V00 to V55 . If we wish to analyze the behavior in this region, we
equate the p-device resistive region current with the n-device saturation current and thus
obtain the voltage and current relationships.
Region 4 is similar to region 2 but with the roles of the p- and n-transistors reversed.
However, the current magnitudes in regions 2 and 4 are small and most of the energy
consumed in switching from one state to the other is due to the larger current which flows
in region 3.
Region 3 is the region in which the inverter exhibits gain and in which both transistors
are in saturation.
The currents (with regard to Figure 2.14(c)) in each device must be the samt: smce the
transistors are in series, so we may write

where

and

from whence we can express V;n in terms of the ~ ratio and the other circuit voltages and
currents

(2.10)

Since both transistors are in saturation, they act as current sources so that the equivalent
circuit in this region is two current sources in series between V00 and Vss with the output
voltage coming from their common point. The region is inherently unstable in consequence
and the changeover from one logic level to the other is rapid.
If ~n = ~P and if Vm = -V,P, then from equation (2.10) .
V;n = 0.5 Voo
This implies that the changeover between logic levels is symmetrically disposed about
the point at which
.,. Basic VL$1 Design

since only at this point will the two ~ factors be equal. But for ~n =
)

~P the device geometries j

must be such that
J.l.pWJLP = J.l.nWn/Ln
Now the mobilities are inherently unequal and thus it is necessary for the width to length
ratio of the p-device to be two to three times that of the n:.device, namely 'I.

WJLP * 2.5 WJLn

However, it must be recognized that mobility Jl is affected by the transverse electric field in
the ·channel and is thus depeqdent on Vgs (and thus on V;n in this in case). It has been shown
empirically that the actual mobility is
ll = llz (I - «<> (Vgs - V,)t 1
cj>is a constant approximately equal to 0.05, V1 includes any body effect, and llz is the
mobility with zero transverse field. Thus a ~ ratio of 1 will only hold good around the point
of symmetry when Vout = V;n = 0.5Vvv·
The ~ ratio is often unimportant in many configurations and in most cases minimum
size transistor geometries are used for both n- and p-devices. Figure 2.15 indicates the trends
in the transfer characteristic as the ratio is varied. The changes indicated in the figure would
be for quite large variations in ~ ratio (e.g. up to 10: 1) and the ratio is thus not too critical
in this respect.

V,p
I
,..................~~.......~-------------!-------- Voo
I
I
I
I

Bn :
......~-+- ->1
Bp

Voo/2

V00 12

FIGURE 2.15 Trends In transfer characteristic with p ratio.

2.11 MOS TRANSISTOR CIRCUIT MODEL

The MOS transistor can be modeled with varying degrees of complexity. However, a
consideration of the actual physical construction of the device (as in Figure 2.16) leads to
some understanding of the various components of the model.
 Basic Electrical Properties of MOS and BiCMOS Circuits ,,.
s G D

FIGURE 2.16 nMOS transistor model.

Notes : CQc = gate to channel capacitance

Ccs = gate to source capacitance
} Small for self-aligning nMOS process
CcD = gate to drain capacitance
Remaining capacitances are associated with the depletion layer and are voltage dependent.
Note that Css indicates source-to-substrate, CDs drain-to-substrate, and Cs channel-to-substrate
capacitances.

2.12 SOME CHARACTERISTICS OF npn BIPOLAR TRANSISTORS

The key properties of MOS transistors and MOS inverters having been covered, it is now
desirable to extend our thoughts into some properties of bipolar transistors and into BiCMOS
inverters.
In dealing with bipolar transistor characteristics, it will be assumed tha_t the reader is
familiar with the basic operation and the fundamental aspects of bipolar transistors .

2.12.1 Transconductance Om-Bipolar

The transconductance of a bipolar transistor is commonly presented as

where
Ic = collt:ctor current
q = electron charge
k = Boltzmann's constant
T = temperature °K
11:1 Basic VLSI Design )

The expression can be rewritten in the form

gm a. AeeYbe(qlkD

where
Vbe is the base to emitter voltage
and
AE is the emitter area.
Note that the following factors may be deduced
• gm a eYbe, that is, exponentially dependent on input voltage Vbe
• gm a. lc
• gm is independent of process
• g,;, is a weak function of transistor size.
Remembering that, for MOS transistors

g = Jl£;n.sEo W (V - V.t)
m D L gs

where
D = oxide thickness (often denoted tox)
Comparisons can be made between MOS and bipolar transistor gm as follows:
1. For Ic =Ids the difference between the thermal voltage (kT!q) and the effective gate
voltage ( V15 - V1) introduces a large difference in transconductance.
2. If inputs are controlled by equal amounts of charge
that is
Cg(MOS) = Chase (bipolar)
then
gm(bipolar) >> gm (MOS)
noting that
Chase = tFlc(q/k1)
C1 = CoA
where C0 (often denoted as Cox) is the gate to channel capacitance per unit area and A= W.L.
tF is the forward transit time.

2.12.2 Comparative Aspects of Key Parameters of CMOS and

Bipolar Transistors
In order to put matters in perspective, a comparison of key parameters follows in Table 2.1.
 . I

( Basic Electrical Properties of MOS and BiCMOS Circuits IQI

TABLE 2.1 A comparison of some parameters

CMOS Bipolar

1. Ids = (JlCo) W (V - V,) 2 lc = Is exp(q Vbefk1)

2 L gs

= J! (Vgs - Vi [In saturation]

2
kT
gm = IJ-
.. q .
[expressions given can be put in this form]
3. ldJA = (J.LCof2L 2 )(Vgs- V,) 2 IJA = li(R 8 Jl'ts)

where Id/A and IJA are current/area and R8 is base resistance and 'ts is the base transit time
(usually in the order of 10-30 ps).
Evaluating, we may see that 1/A for bipolar is five times better than that for CMOS. A
discussion of the current drive aspects of BiCMOS circuits will be found in Chapter 4
(section 4.8 .3).

2.12.3 BICI'IOS Inverters

As in nMOS and CMOS logic circuitry, the basic logic element is the .inverter circuit.
When designing .with BiCMOS in mind, the logical approach is to use MOS switches
to perform the logic function and bipolar transistors to drive the output loads. The simplest
logic function is that of inversion, and a simple BiCMOS inverter circuit is readily set out
as shown in Figt,~re 2.17.
It consists of two bipolar transistors T1 and T2 with one nMOS transistor T3, and one
pMOS transistor T4 , both being enhancement mode devices. The actiori of the circuit is
straightforward and may be described as follows:
• With V;n ·= 0 volts (GND) T3 is off so that T1 will be non-conducting. But T4 is on
and supplies current to the base of T2 which will conduct and act as a current source
to char_ge the load Cr toward +5 volts(Vnn). The output of the inverter will rise to
+5 volts less the ·base to emitter voltage V8 E of T2 .
• With V;n = +5 volts· CVnn) T4 is off so that T2 will be non-conducting. But T3 will
now be on and will supply current to the base of T1 which will conduct and act as
a current sink to the' load Cr discharging it toward 0 volts (GND). The output of the
inverter will fall to 0 volts plus the saturation voltage VCEsar from the collector to the
emitter of T1•
• T1 and T2 will present low impedances when turned on into saturation and the load
Cr will be charged or discharged rapidly.
~
~-4-•JI~------------------------~B~a~s'~·c_V~L~S~I~D~e~s~ig~n~--------------------------~)

----------------~~----~---GND
vss
FIGURE 2.17 A simple BiCMOS inverter.

• The output logic levels will be good and will be close to the rail voltages since VCEsar
is quite small and V8 E is approximately + 0.7 volts.
• The inverter has a high input impedance.
• The inverter has a low output impedance.
• The inverter has a high current drive capability but occupies a relatively small area.
• The inverter has high noise margins.
However, owing to the presence of a DC path from Vnn to GND through T3 and T~o this
is not a good arrangement to implement since there will be a significant static current flow
whenever V;n = logic I. There is also a problem in that there is no discharge path for current
from the base of either bipolar transistor when it is being turned off. This will slow down
the action of this circuit.
An improved version of this circuit is given in Figure 2.18, in which the DC path
through T3 and T1 is eliminated, but the output voltage swing is now reduced, since the
output cannot fall below the base to emitter voltage V8 E of T1.
An improved inverter arrangement, using resistors, is shown in Figure 2.19. In this
circuit resistors provide the improved swing of output voltage when each bipolar transistor
is off, and also provide discharge paths for base current during turn-off.
The provision of on chip resistors of suitable value is not always convenient and may
be space-consuming, so that other arrangements-such as in Figure 2.20-are used. In this
circuit, the transistors T5 and T6 are arranged to turn on when T2 and T 1 resi?ectively are being
turned off.
In general, BiCMOS inverters offer many advantages where high load current sinking
and sourcing is required. The atran_gements lead on to the BiCMOS gate circuits which will
be dealt with in Chapter 5.
•
( Basic Electrical Properties of MOS and BiCMOS Circuits
•1•

v,,

c,

-----------------.~----~--GND
FIGURE 2.18 An alternative BICMOS Inverter with no static current flow.

--~--------------~---------voo

--~--------------~----._-- GNV
FIGURE 2.19 ~,An improved BICMOS inverter with better output logic levels.

2.13 LATCH-UP IN CMOS CIRCUITS

A problem which is inherent in the p-well and n-well processes is due to the relatively large
number of junctions which are formed in these structures and, as mentioned earlier, the
consequent pre·sence of parasitic transistors and diodes. Latch-up is a condition in which .the
parasitic components give rise to the establishment of low-resistance conducting paths between