Hi3518E V20X/Hi3516C V200 Hardware Design

User Guide

Issue 01

Date 2016-10-28
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 Hi3518E V20X/Hi3516C V200 Hardware Design
User Guide About This Document

About This Document

Purpose
This document describes the design recommendations for the schematic diagrams, printed
circuit board (PCB), and board heat dissipation of Hi3518E V20X. It also provides the
hardware design methods of Hi3518E V20X.

Related Versions
The following table lists the product versions related to this document.

Product Name Version

Hi3518E V200
Hi3518E V201
Hi3516C V200

Intended Audience
This document is intended for:
 Technical support engineers
 Board hardware development engineers

Change History
Changes between document issues are cumulative. Therefore, the latest document issue
contains all changes made in previous issues.

Issue 01 (2016-10-28)
This issue is the first official release, which incorporates the following changes:
Chapter 1 Design Recommendations on Schematic Diagrams
Section 1.2.6 is added.

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Section 1.3.7.2 is modified.

Chapter 2 PCB Design Recommendations
Section 2.1.3 is modified.

Issue 00B03 (2016-05-16)

This issue is the third draft release, which incorporates the following changes:
Chapter 1 Design Recommendations on Schematic Diagrams
Section 1.2.5 and section 1.3.7.1 are modified.

Issue 00B02 (2015-12-10)

This issue is the second draft release, which incorporates the following changes:
Chapter 1 Design Recommendations on Schematic Diagrams
In section 1.1.3.4, figure 1-5 is modified.
In section 1.2.1, figure 1-7 is modified.
Section 1.3.5 and section 2.2.1 are modified.

Issue 00B01 (2015-09-14)

This issue is the first draft release.

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 Hi3518E V20X/Hi3516C V200 Hardware Design
User Guide Contents

Contents

About This Document ......................................................................................................................i

1 Design Recommendations on Schematic Diagrams .............................................................. 1
1.1 Design Recommendations on the Small System .............................................................................................. 1
1.1.1 Clocking Circuit ...................................................................................................................................... 1
1.1.2 DDR Circuit ............................................................................................................................................ 2
1.1.3 Flash and eMMC..................................................................................................................................... 3
1.1.4 System Configuration Circuit for Hardware Initialization ...................................................................... 7
1.1.5 POR and Watchdog ................................................................................................................................. 8
1.1.6 JTAG Debug Interface ............................................................................................................................ 8
1.2 Power Design Recommendations ..................................................................................................................... 9
1.2.1 Core Power.............................................................................................................................................. 9
1.2.2 DDR Power ........................................................................................................................................... 11
1.2.3 I/O Power .............................................................................................................................................. 12
1.2.4 PLL Power ............................................................................................................................................ 13
1.2.5 Power-on and Power-off Sequences...................................................................................................... 14
1.2.6 SVB Dynamic Voltage Scaling ............................................................................................................. 15
1.2.7 Precautions ............................................................................................................................................ 17
1.3 Peripheral Interfaces ....................................................................................................................................... 17
1.3.1 UART Interface ..................................................................................................................................... 17
1.3.2 USB 2.0 Port ......................................................................................................................................... 18
1.3.3 MAC Interface ...................................................................................................................................... 18
1.3.4 Audio Interfaces .................................................................................................................................... 19
1.3.5 VI Interface ........................................................................................................................................... 23
1.3.6 VO Interface.......................................................................................................................................... 27
1.3.7 SDIO Interface ...................................................................................................................................... 27
1.3.8 SPI and I2C Interface............................................................................................................................. 28
1.3.9 RTC ....................................................................................................................................................... 28
1.3.10 PWM Interface .................................................................................................................................... 28
1.3.11 Processing of Unused Pins .................................................................................................................. 28
1.3.12 Sensor Board Design ........................................................................................................................... 29

2 PCB Design Recommendations................................................................................................ 31

2.1 Small System .................................................................................................................................................. 31

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2.1.1 Power Supplies for the Small System ................................................................................................... 31

2.1.2 Clock Circuit ......................................................................................................................................... 34
2.1.3 ETH Signals .......................................................................................................................................... 36
2.2 Typical Peripheral Interfaces .......................................................................................................................... 36
2.2.1 USB Port ............................................................................................................................................... 36
2.2.2 Audio Circuit Design ............................................................................................................................ 37
2.2.3 VI Interface ........................................................................................................................................... 40

3 Design Recommendations on ESD and Heat Dissipation .................................................. 42

3.1 Background .................................................................................................................................................... 42
3.2 ESD Design Recommendations ..................................................................................................................... 42
3.3 Recommendations on Heat Dissipation Design ............................................................................................. 43
3.3.1 Operating Conditions ............................................................................................................................ 43
3.3.2 Reference Design for Circuit Heat Dissipation ..................................................................................... 43

4 Differences Between Hi3518E V20X and Hi3516C V200 and Design Recommendations
for Hi3516C V200 ............................................................................................................................ 45
4.1 Differences Between Hi3518E V20X and Hi3516C V200 ............................................................................ 45
4.2 Design Recommendations for Hi3516C V200 ............................................................................................... 45
4.2.1 DDR3/DDR3L Interface ....................................................................................................................... 45
4.2.2 Schematic Diagram of the DDR Power ................................................................................................ 46
4.2.3 PCB Design Recommendations ............................................................................................................ 47

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Figures

Figure 1-1 24 MHz crystal oscillator circuit ......................................................................................................... 2

Figure 1-2 RTC crystal oscillator circuit ............................................................................................................... 2

Figure 1-3 Recommended pull-up/-down design for the SFC interface ................................................................ 3

Figure 1-4 Typology when two external SPI flash memories are connected ......................................................... 4

Figure 1-5 Connection between the eMMC and Hi3518E V20X .......................................................................... 6

Figure 1-6 JTAG connection mode and standard connector pins .......................................................................... 9
Figure 1-7 Schematic diagram of the core power ................................................................................................ 10

Figure 1-8 Type of filter capacitors for the Hi3518E V20X core power ............................................................. 10

Figure 1-9 Type of filter capacitors for the Hi3516C V200 core power .............................................................. 10
Figure 1-10 Reference design of the power voltage division network ................................................................ 11

Figure 1-11 Schematic diagram of AVDD_DDRPLL ......................................................................................... 11

Figure 1-12 Schematic diagram of the DDR power ............................................................................................ 12

Figure 1-13 Schematic diagram of the PLL power supply and GND pins .......................................................... 14

Figure 1-14 Power-on sequence .......................................................................................................................... 14

Figure 1-15 Power-off sequence.......................................................................................................................... 15

Figure 1-16 Schematic diagram of dynamic voltage scaling ............................................................................... 16

Figure 1-17 Signal connection in RMII mode (clocks are provided by Hi3518E V20X).................................... 19

Figure 1-18 Schematic diagram of the power design for the audio module ........................................................ 20
Figure 1-19 Schematic diagram of the single-ended MIC input for the audio part ............................................. 20

Figure 1-20 Schematic diagram of the differential MIC input for the audio part ................................................ 21

Figure 1-21 Schematic diagram of the MIC_BIAS and input signal for the audio module ................................ 21

Figure 1-22 Schematic diagram of the audio operational amplifier output ......................................................... 22

Figure 1-23 5-wire connection in I2S master mode ............................................................................................. 22

Figure 1-24 5-wire connection in I2S slave mode................................................................................................ 23

Figure 1-25 VI HS and VS signals ...................................................................................................................... 24

Figure 2-1 Core power pins for Hi3518E V20X .................................................................................................. 32

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Figure 2-2 Core power pins for Hi3516C V200 .................................................................................................. 32

Figure 2-3 PCB design of AVDD_DDRPLL ....................................................................................................... 33

Figure 2-4 PCB design of the AVDD11_PLL power and GND pins ................................................................... 34

Figure 2-5 PCB design of the AVDD33_PLL power and GND pins ................................................................... 35

Figure 2-6 PCB design of the 24 MHz system clock and RTC ........................................................................... 35

Figure 2-7 PCB design of the AC_Vref power .................................................................................................... 37

Figure 2-8 PCB design of AVDD33_AC and AVSS_AC .................................................................................... 38

Figure 2-9 PCB design of MIC_BIAS when dual MIC inputs are used .............................................................. 38

Figure 2-10 Mother board PCB design of the audio input and output signal traces ............................................ 39

Figure 2-11 PCB design for surrounding the audio signal traces with GND traces and isolating them from other
high-speed signal traces (1) .................................................................................................................................. 39
Figure 2-12 PCB design for surrounding the audio signal traces with GND traces and isolating them from other
high-speed signal traces (2) .................................................................................................................................. 40
Figure 2-13 PCB design of the VI interface ........................................................................................................ 41
Figure 4-1 Filter capacitors for the DDR3/3L power (at the Hi3516C V200 end) .............................................. 46

Figure 4-2 Filter capacitors for the DDR3/3L power (at the DDR SDRAM end) ............................................... 46

Figure 4-3 Reference design of the DDR3/3L power voltage division network ................................................. 47
Figure 4-4 Filter capacitor layout for the 1.5 V/1.35 V power ............................................................................ 48

Figure 4-5 Design of the 1.5 V/1.35 V power module and power channels ........................................................ 48

Figure 4-6 Trace routing at the top layer ............................................................................................................. 49

Figure 4-7 Trace routing at the bottom layer ....................................................................................................... 49

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User Guide Tables

Tables

Table 1-1 Recommended design when an external SPI flash memory is connected ............................................. 3
Table 1-2 Recommended design when two external SPI flash memories are connected ...................................... 4

Table 1-3 Recommended eMMC design ............................................................................................................... 5

Table 1-4 Hardware configuration signals ............................................................................................................. 7

Table 1-5 Signals of the JTAG debug interface ..................................................................................................... 8

Table 1-6 Design requirements on the chip I/O power ........................................................................................ 12

Table 1-7 RC parameters for in the SVB voltage scaling circuit ......................................................................... 17

Table 1-8 Design recommendations on the default interconnection mode of the VI interface ............................ 25
Table 1-9 Recommendations on processing unused pins ..................................................................................... 28

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1 Design Recommendations on Schematic

Diagrams

This document uses Hi3518E V20X as an example. Unless otherwise specified, this document applies to
Hi3518E V200, Hi3518E V201, and Hi3516C V200. The differences between Hi3518E V200, Hi3518E
V201, and Hi3516C V200 and design recommendations for Hi3516C V200 are described in chapter 4
"Differences Between Hi3518E V20X and Hi3516C V200 and Design Recommendations for Hi3516C
V200."

1.1 Design Recommendations on the Small System

1.1.1 Clocking Circuit
The system clock circuit can be generated by combining the internal feedback operational
amplifier circuit of Hi3518E V20X with a 24 MHz external crystal oscillator circuit. Figure 1-
1 shows the clock circuit design and component parameters.

The load capacitance of capacitors used in the clock circuit must match that of the crystal, and
the NPO resistors are commended. It is recommended that the 4-pin surface mount device
(SMD) crystal oscillator be selected and its two ground (GND) pins be fully connected to the
board GND to improve the anti-ESD interference capability of the system clock.

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Figure 1-1 24 MHz crystal oscillator circuit

Hi3518E V20

XIN XOUT

1 MΩ

10 Ω

24 MHz

18 pF 18 pF

Hi3518E V20X integrates the real-time clock (RTC) module. The board needs to provide a
clock circuit for this module. Figure 1-2 shows the clock circuit design and component
parameters.

Figure 1-2 RTC crystal oscillator circuit

The inherent load capacitance of the crystal varies according to the brand and model. The load
capacitance of the capacitors in the circuit must match that of the crystal to ensure that the clock
frequency offset falls within the required specifications range.

1.1.2 DDR Circuit

The DDR circuit design described in this section applies only to Hi3518E V200 and Hi3518E V201. The
DDR circuit design for Hi3516C V200 is described in chapter 4 "Differences Between Hi3518E V20X
and Hi3516C V200 and Design Recommendations for Hi3516C V200."

Hi3518E V20X has embedded DDR2 SDRAMs. Therefore, you need only to pay attention to
the DDR power design. For details, see section 1.2 "Power Design Recommendations."

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1.1.3 Flash and eMMC

1.1.3.1 Flash Interface
The SPI flash interface of Hi3518E V20X can connect to the serial peripheral interface (SPI)
NOR flash and SPI NAND flash. If the chip boots from an SPI flash memory based on
hardware configuration, the master chip boots from the SPI flash memory (which stores the
U-boot) connected to the SFC_CSN0 pin by default after its reset signal is released.

1.1.3.2 Flash Signals

Table 1-1 describes the recommended design when an external SPI flash memory is connected.

Table 1-1 Recommended design when an external SPI flash memory is connected

Signal 4-Layer PCB Design 6-Layer PCB

Design
SFC_CLK Connect a 22 Ω resistor in series at the Same as the 4-layer
Hi3518E V20X end. board design
SFC_DIO/SFC_DOI Directly connect the signals to the Same as the 4-layer
/SFC_WP/SFC_HOLD corresponding signals on the SPI flash. board design
Connect SFC_WP to a 4.7 kΩ pull-
/SFC_HOLD/SFC_CSN0 down resistor. Connect SFC_HOLD
and SFC_CSN0 to 4.7 kΩ pull-up
resistors. Figure 1-3 shows the
interconnection schematic diagram.

Figure 1-3 Recommended pull-up/-down design for the SFC interface

Table 1-2 describes the recommended design when two external SPI flash memories are
connected.

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Table 1-2 Recommended design when two external SPI flash memories are connected

Signal 4-Layer PCB Design 6-Layer PCB Design

SFC_CLK Use the T-type topology and Same as the 4-layer board
minimize the length of the trace design
between the T point and the SPI
flash.
Connect 22 Ω matched resistors in
series between two SPI flash
memories and the T point.
Connect a 22 Ω matched resistor in
series to SFC_CLK at the source
end. Figure 1-4 shows the typology.
SFC_DIO/SFC_DOI Use the T-type topology and Same as the 4-layer board
/SFC_WP/SFC_HOLD minimize the length of the trace design
between the T point and the SPI
/SFC_HOLD flash.
Connect SFC_WP to a 4.7 kΩ pull-
down resistor and SFC_HOLD to a
4.7 kΩ pull-up resistor.
SFC_CSN0/CSN1 Directly connect the signals to the Same as the 4-layer board
corresponding signals on the SPI design
flash. Connect the two signals to 4.7
kΩ pull-up resistors.

Figure 1-4 Typology when two external SPI flash memories are connected

Figure 1-4 shows only the typology when Hi3518E V20X interconnects with two SPI flash memories
(the pull-up and pull-down resistors are not drawn). During the actual design, the pull-up and pull-down
resistors need to be added to the signal lines based on Table 1-2.

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 When Hi3518E V20X interconnects with the SPI flash, the I/O interface voltage (3.3 V or
1.8 V) of the selected SPI flash must be consistent with the voltage of the power supply for
the DVDD3318_EMMC pin of Hi3518E V20X.
 The voltage of DVDD3318_EMMC can be 3.3 V or 1.8 V, depending on the I/O power of
the selected SPI flash. The DVDD3318_EMMC pin supplies power to universal
asynchronous receiver transmitter 1 (UART1)/UART2. When UART1/UART2 is used, its
level must be consistent with that of the interconnected component.

1.1.3.3 eMMC Interface

The embedded multimedia card (eMMC) interface of Hi3518E V20X is multiplexed with the
SPI flash interface and UART1/UART2 interface. The maximum frequency of the eMMC
interface clock is 100 MHz. For details, see the description of the eMMC interface in the
Hi3518E V20X/Hi3516C V200 Economical HD IP Camera SoC Data Sheet.

1.1.3.4 eMMC Signals

Table 1-3 describes the recommended eMMC design. Figure 1-5 shows the connection
between the eMMC and Hi3518E V20X.

Table 1-3 Recommended eMMC design

Signal 4-Layer PCB Design 6-Layer PCB Design

EMMC_CLK Connect a 22 Ω resistor in series at the Same as the 4-layer board

source end. design
EMMC_DAT[0:7] Directly connect the signals to the Same as the 4-layer board
corresponding signals on the eMMC. design
Minimize the trace length. Connect the
signals to 47 kΩ pull-up resistors.
EMMC_CMD Directly connect the signal to the Same as the 4-layer board
corresponding signal on the eMMC. design
Minimize the trace length. Connect the
signal to a 10 kΩ pull-up resistor.
EMMC_DS Connect a 22 Ω resistor in series at the Same as the 4-layer board
eMMC end. Minimize the trace length. design
Connect the signal to a 47 kΩ pull-
down resistor (the external pull-down
resistor is not required on the PCB if
the eMMC has an embedded pull-down
resistor).
EMMC_RST_N Directly connect the signal to the Same as the 4-layer board
corresponding signal on the eMMC. design
Connect the signal to a 47 kΩ pull-up
resistor.
EMMC_Power_EN Directly connect the signal to the Same as the 4-layer board
corresponding signal on the eMMC. design

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Figure 1-5 Connection between the eMMC and Hi3518E V20X

+3.3 V/1.8 V VCC

+3.3 V/1.8 V
+3.3 V/1.8 V

DVDD3318_EMMC VCCQ VCC

22
EMMC_CLK_OUT CLK
EMMC_CCMD CMD
EMMC_RSTN RSTN
EMMC_DS DS
22

EMMC_CDATA0 DAT0
EMMC_CDATA1 DAT1
EMMC_CDATA2 DAT2
EMMC_CDATA3 DAT3
EMMC_CDATA4 DAT4
EMMC_CDATA5 DAT5
EMMC_CDATA6 DAT6
EMMC_CDATA7 DAT7

47 kΩ

Figure 1-5 shows only the connection between Hi3518E V20X and the eMMC. The parameter
configuration and connection mode may vary according to the eMMC. Therefore, you need to design the
circuit and select parameters based on the component manual of the selected eMMC.

 When Hi3518E V20X interconnects with the eMMC, the I/O interface voltage (3.3 V or
1.8 V) of the selected eMMC must be consistent with the voltage of the power supply for
the DVDD3318_EMMC pin of Hi3518E V20X.
 The DVDD3318_EMMC pin of Hi3518E V20X must be always supplied with power, and
its power-on and power-off cannot be controlled by EMMC_POWER_EN.
 When Hi3518E V20X connects to the eMMC and the Wi-Fi module of the secure digital
input/output (SDIO) interface at the same time, it can only use the SDIO interface
multiplexed with the MAC to connect to the Wi-Fi module.

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1.1.4 System Configuration Circuit for Hardware Initialization

Hi3518E V20X can boot from the BOOTROM, SPI flash, or eMMC by configuring the
BOOTROM_SEL pin.
In BOOTROM boot mode, Hi3518E V20X boots from the BOOTROM after the serial port
communication mechanism is started, the connection between the serial port and the related
software running on the PC is established, and the boot program is downloaded. If the serial
port communication times out, Hi3518E V20X boots from an external SPI flash memory or
eMMC.
The working mode of each module is determined based on the pull-up/pull-down status of the
corresponding configuration pin during the power-on initialization of Hi3518E V20X. Table
1-4 describes hardware configuration signals.

Table 1-4 Hardware configuration signals

Signal Direction Description

JTAG_EN (internal I JTAG debug enable
pull-down) 0: disabled
1: enabled
BOOTROM_SEL I Boot mode select
(internal pull-down) 0: booting from an SPI flash memory or eMMC
1: booting from the BOOTROM
BOOT_SEL (internal I Select of the medium from which the system boots
pull-down) 0: SPI flash
1: eMMC
SFC_Device_Mode I Boot SPI flash select
(internal pull-down) 0: SPI NOR flash
1: SPI NAND flash
SFC_EMMC_BOOT_ I Boot mode select
MODE (internal pull- When the system boots from an SPI NOR flash
down) memory:
0: 3-byte boot mode
1: 4-byte boot mode
When the system boots from an SPI NAND flash
memory:
0: 1-wire boot mode
1: 4-wire boot mode
When the system boots from an eMMC:
0: 4-wire boot mode
1: 8-wire boot mode

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Signal Direction Description

TEST_MODE I Mode select

0: functional mode
1: test mode

1.1.5 POR and Watchdog

Hi3518E V20X supports internal power-on reset (POR) but not external reset.

After the 3.3 V power and core power of the master chip are turned on, the internal POR
circuit resets the chip, and the reset signal is output to peripherals (mainly the boot flash
memory) through the SYS_RSTN_OUT pin.
The integrated watchdog of Hi3518E V20X resets the chip when the system becomes
abnormal, and the reset signal is output through the SYS_RSTN_OUT pin to reset peripherals.

 Peripherals (especially the boot flash memory) must be reset before the system to ensure
that the system boots properly; otherwise, exceptions such as system boot failure may
occur.
 The high level output by the SYS_RSTN_OUT pin can be 3.3 V or 1.8 V (the voltage
must be consistent with that of the power supply for the DVDD3318_EMMC pin). When
the output signal is used for resetting peripherals, the signal levels must be consistent.

1.1.6 JTAG Debug Interface

Table 1-5 describes the signals of the JTAG debug interface.

Table 1-5 Signals of the JTAG debug interface

Signal Description
TCK JTAG clock input. This signal must connect to a 1 kΩ pull-down resistor on the
board when the JTAG function is used.
TDI JTAG data input. This signal must connect to a 4.7 kΩ pull-up resistor on the
board when the JTAG function is used.
TMS JTAG mode select input. This signal must connect to a 4.7 kΩ pull-up resistor
on the board when the JTAG function is used.
TRSTN JTAG reset input. This signal must connect to a 10 kΩ pull-down resistor on
the board when the JTAG function is used.
TDO JTAG clock output. This signal must connect to a 4.7 kΩ pull-up resistor on the
board when the JTAG function is used.

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Figure 1-6 shows the recommended pull-up/pull-down resistance, connection mode of JTAG
signals, and standard connector pins. If the JTAG function is used, you need to connect the
JTAG_EN pin on the board to a 4.7 kΩ pull-up resistor.

Figure 1-6 JTAG connection mode and standard connector pins

1.2 Power Design Recommendations

For details about the power design parameters for Hi3518E V20X, see the electrical
specifications in the Hi3518E V20X/Hi3516C V200 Economical HD IP Camera SoC Data
Sheet.
You are advised to design the chip power supplies by following the HiSilicon power design.

1.2.1 Core Power

The core power pin (VDD) connects to the 1.1 V digital power. It is required that the load
capacity of the DC-DC be 1 A or higher. The capacitance and quantity of the decoupling
capacitors for the core power must be designed by following the latest schematic diagram of
Hi3518E V20X/Hi3516C V200 demo board. It is recommended that the circuit implement the
selective voltage binning (SVB) function. See Figure 1-7 to Figure 1-9.

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Figure 1-7 Schematic diagram of the core power

Figure 1-8 Type of filter capacitors for the Hi3518E V20X core power

Figure 1-9 Type of filter capacitors for the Hi3516C V200 core power

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1.2.2 DDR Power

The DDR circuit design described in this section applies only to Hi3518E V200 and Hi3518E V201. The
DDR circuit design for Hi3516C V200 is described in chapter 4 "Differences Between Hi3518E V20X
and Hi3516C V200 and Design Recommendations for Hi3516C V200."

Hi3518E V20X has embedded DDR2 SDRAMs. The power design must comply with the
SSTL-18 level standard, the I/O power must be 1.8 V, and the reference voltage Vref must be
0.9 V.
It is recommended that an independent DC-DC circuit be designed on the board to supply
power to the 1.8 V DDR power pin, and the 0.9 V power obtained after voltage division by
using a 1 kΩ±1% resistor be used to supply power to the reference power pin Vref for the
embedded DDR2 SDRAM of Hi3518E V20X. Figure 1-10 shows the reference design of the
power voltage division network.

Figure 1-10 Reference design of the power voltage division network

The DDR phase-locked loop (PLL) power (pin name: AVDD_DDRPLL) is isolated from the
3.3 V I/O power of the master chip by using a 1 kΩ@100 MHz electromagnetic interference
(EMI) bead. See Figure 1-11.

Figure 1-11 Schematic diagram of AVDD_DDRPLL

The DDR power (pin name: VDDIO_DDR/VDDIO_CK_DDR) connects to the 1.8 V digital
power. See Figure 1-12.

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Figure 1-12 Schematic diagram of the DDR power

1.2.3 I/O Power

Table 1-6 describes the design requirements on the chip I/O power.

Table 1-6 Design requirements on the chip I/O power

Power Pin Application Scenario Processing Method

Chip I/O power DVDD33 All application scenarios Connect to the 3.3 V digital
power.
I/O power of DVDDIO_ The I/O level is 3.3 V. Connect to the 3.3 V digital
the network RMII power. The I/O level of the
port interconnected network
port PHY must be
consistent with the level of
the network port I/O
power.
The I/O level is 1.8 V. Connect to the 1.8 V digital
power. The I/O level of the
interconnected network
port PHY must be
consistent with the level of
the network port I/O
power.
eMMC/SPI DVDD3318 The I/O level is 3.3 V. Connect to the 3.3 V digital
FLASH _EMMC power. The I/O level of the
interface power interconnected eMMC or
SPI flash must be
consistent with the level of
the eMMC interface power.
The I/O level is 1.8 V. Connect to the 1.8 V digital
power. The I/O level of the
interconnected eMMC or
SPI flash must be
consistent with the level of
the eMMC interface power.

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Power Pin Application Scenario Processing Method

Interface DVDD3318 The mobile industry Connect to the 1.8 V digital
power for the _SENSOR processor interface (MIPI) power.
sensor clock, of the sensor is connected.
reset, and
configuration The 1.8 V complementary Connect to the 1.8 V digital
pins metal-oxide-semiconductor power.
(CMOS) interface of the
sensor is connected.
The 3.3 V CMOS interface Connect to the 3.3 V digital
of the sensor is connected. power.
MIPI power AVDD3318 The MIPI of the sensor is Connect to the 1.8 V digital
_MIPI connected. power.
The 1.8 V CMOS interface Connect to the 1.8 V digital
of the sensor is connected. power.
The 3.3 V CMOS interface Connect to the 3.3 V digital
of the sensor is connected. power.
Video input DVDD3318 The MIPI of the sensor is Connect to the 3.3 V or 1.8
(VI) interface _VI connected. V digital power based on
power the usage status of
GPIO1_0 to GPIO1_6.
The 1.8 V CMOS interface Connect to the 1.8 V digital
of the sensor is connected. power.
The 3.3 V CMOS interface Connect to the 3.3 V digital
of the sensor is connected. power.

When Hi3518E V20X connects to the sensor of the parallel interface with 1.8 V I/O level (the
levels of AVDD3318_MIPI and DVDD3318_VI are 1.8 V), the I/O levels of pins GPIO1_0 to
GPIO1_6 are 1.8 V. When the remaining signals of the seven pins are used as GPIOs, note
that the interface level of the interconnected component must be consistent with the pin I/O
level.

1.2.4 PLL Power

It is recommended that the PLL power be isolated from the digital power by using 1 kΩ@100
MHz EMI beads. Figure 1-13 shows the circuit design.

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Figure 1-13 Schematic diagram of the PLL power supply and GND pins

1.2.5 Power-on and Power-off Sequences

Figure 1-14 and Figure 1-15 show the requirements on the power-on and power-off sequences
of the core power, DDR_IO power, and DVDD33 chip power.

Figure 1-14 Power-on sequence

T1
Power-on sequence
DVDD33

T2

DDR_IO

T3

Core

0 < T1 ≤ 100 ms; T2 > 0; T3 > 0

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Figure 1-15 Power-off sequence

Threshold for triggering the POR

SYS_RSTN_OUT

Core

T4

 T4 > 0
 During power-off, the DVDD33 power is turned off first. When the DVDD33 power supply
decreases to the threshold for powering off the POR (2.1–2.6 V), the POR is triggered, and the core
power supplies start to be powered off.

The POR is in one the following three states when it is powered off:
 When the voltage of DVDD33 decreases from 3.3 V to 2.6 V, the timing starts. If the
voltage of DVDD33 is higher than 2.6 V at the 5 µs time point, occurrence of power
fluctuation is considered by the POR module, the POR reset is not triggered, and the
SYS_RSTN_OUT pin retains the high level.
 When the voltage of DVDD33 decreases from 3.3 V to 2.6 V, the timing starts. If the
voltage of DVDD33 is greater than 2.1 V but less than or equal to 2.6 V at the 5 µs time
point, the POR is triggered and the SYS_RSTN_OUT pin outputs low level.
 When the voltage of DVDD33 decreases from 3.3 V to 2.6 V, the timing starts. If the
voltage of DVDD33 is less than or equal to 2.1 V within 5 µs after timing starts, the POR
is triggered and the SYS_RSTN_OUT pin outputs the low level.

1.2.6 SVB Dynamic Voltage Scaling

If the dynamic voltage scaling function is added to the core power supplies of Hi3518E V20X,
the implementation is as follows:
Transmit the signal from the pulse width modulation (PWM) waveform output pins
(PWM0−3). The pins output the DC levels ranging from 0 V to 3.3 V after RC filtering. The
DC levels are overlapped at the input end of the DC-DC feedback voltage to implement DC-
DC output voltage scaling. Then adjust the PWM frequency and duty cycle by configuring
related registers of Hi3518E V20X. In this way, the DC-DC output voltage is dynamically
scaled. See Figure 1-16.

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Figure 1-16 Schematic diagram of dynamic voltage scaling

During SVB circuit design, connect the PWM pin of Hi3518E V20X to the SVB circuit and
then to the FB pin of the DC-DC circuit for the core power supply. Note the following during
design:
 The error range of the DC voltage of the 3.3 V power for Hi3518E V20X must fall
within ±50 mV.
 A resistor (R6) needs to be reserved before the FB pin in the DC-DC circuit to ensure the
loop stability of the DC-DC component.
 The impedance of R6 can be calculated by using the following equation (this calculation
method applies only to the MPS DC-DC. You need to confirm with the vendors whether
this equation applies to the DC-DC of other solutions).
 If R6 must be added, its impedance can be estimated based on the following formula:
R6 x (Vout/Vref) + R1 = 200 kΩ
where
Vout is the nominal voltage of the DC-DC output, Vref is the reference voltage of the
DC-DC, and R1 is the voltage-division resistor on the FB pin of the DC-DC.
The value 200 kΩ in the right of the equation is an empirical value, and it can be
changed to 100 kΩ if the capacitance of the DC-DC output capacitor is greater than the
reference capacitance in the DC-DC manual.
The obtained impedance of R6 is a reference value. The actual impedance fluctuates
around the calculation result, and is close to the reference value.

 The precision of all the resistors must be 1%, and the material of the capacitors must be
X5R or X7R.
 If the DC-DC component loop is stable, R6 can be removed.

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The parameter configuration of the SVB circuit must be consistent with those in Table 1-7.

Table 1-7 RC parameters for in the SVB voltage scaling circuit

Peripheral Resistors of the Power Supply (Vout (max) = 1.267 V; Vout (min) = 0.8
V; Vpwm = 3.3 V)

Vref (V) R1 R2 R3 R4 R5 C (µF)

(kohm) (kohm) (kohm) (kohm) (kohm)
0.6 30 30.9 180 30.1 2.49 2.2
0.608 30 31.6 180 30.1 2.49 2.2
0.765 30 58.2 180 30.1 2.49 2.2
0.8 33.2 75 180 51 2.49 2.2
0.803 30 68.1 180 30.1 2.49 2.2
0.807 35.7 82 180 68.1 2.49 2.2
0.925 9.09 39.2 47 14.7 2.49 2.2

1.2.7 Precautions
Ensure that the output voltage of each power supply meets the requirements even when
ripples and noises occur. For details about the power supply requirements of each module, see
the electrical specifications in the Hi3518E V20X/Hi3516C V200 Economical HD IP Camera
SoC Data Sheet.

1.3 Peripheral Interfaces

1.3.1 UART Interface
1.3.1.1 Features
For details, see the description of the UART interface in the Hi3518E V20X/Hi3516C V200
Economical HD IP Camera SoC Data Sheet.

1.3.1.2 Design Recommendations on the UART Circuit

Hi3518E V20X has three UART units. UART0 is used for debugging, and the fastboot boots
only from UART0.

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The voltage of DVDD3318_EMMC can be 3.3 V or 1.8 V, depending on the I/O power of the
selected SPI flash. The DVDD3318_EMMC pin supplies power to UART1/UART2. When
UART1/UART2 is used, its level must be consistent with that of the interconnected
component.

1.3.2 USB 2.0 Port

1.3.2.1 Features
For details about the features of the USB port, see the Hi3518E V20X/Hi3516C V200
Economical HD IP Camera SoC Data Sheet.

1.3.2.2 Design Recommendations on the USB 2.0 Circuit

The design recommendations on the USB 2.0 circuit are as follows:
 The USB_REXT pin must connect to a 135 Ω±1% pull-down resistor.
 The analog power AVDD33_USB must be isolated from the 3.3 V digital power by using
a 1 kΩ@100 MHz EMI bead, and filter capacitors must be placed close to the chip pin.
AVSS_USB must be protected from interference. Ensure that short and wide signal
traces are used.
 The ESD protection components with the parasitic capacitance less than 2 pF are
recommended for the USB interface.

1.3.3 MAC Interface

1.3.3.1 Features
For details about the features of the MAC interface, see the Hi3518E V20X/Hi3516C V200
Economical HD IP Camera SoC Data Sheet.

1.3.3.2 Design Recommendations on the MAC Interface

The MAC interface of Hi3518E V20X supports only the reduced media independent interface
(RMII) mode and does not support the energy efficient Ethernet (EEE) function. Figure 1-17
shows the signal connection when RTL8201F is taken as an example.

 The hardware connection mode of the Hi3518E V20X MAC interface described in this
document takes only RTL8201F as an example. If other PHY chip models are used, the
connection mode of the MAC interface needs to be determined based on the corresponding
data sheet and reference circuit of the selected PHY chip.
 The level of the MAC interface can be 3.3 V or 1.8 V. During circuit design, note that the
I/O level of the interconnected PHY chip must be consistent with the level of the MAC
interface.

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Figure 1-17 Signal connection in RMII mode (clocks are provided by Hi3518E V20X)

All MAC signals are connected using the point-to-point topology. The PCB signal traces must
be 6 inches or shorter. The design recommendations on matched resistors are as follows:
 The MDIO signal must connect to a 1.5 kΩ pull-up resistor.
 The MDCK signal must connect to a 22 Ω resistor in series at the MAC end.
 The TXD0 and TXD1 signals must connect to 22 Ω resistors in series at the MAC end.
 The RXD0 and RXD1 signals must connect to 22 Ω resistors in series at the PHY end.
 RMII_CLK can be output by Hi3518E V20X or the PHY chip, which can be specified
based on the features of the PHY chip and as required. A 22 Ω resistor needs to be
connected in series at the output end of RMII_CLK.
 For details about the configuration at the PHY chip end, see the PHY manual.

1.3.4 Audio Interfaces

1.3.4.1 Features
For details about the features of the audio interfaces, see the Hi3518E V20X/Hi3516C V200
Economical HD IP Camera SoC Data Sheet.

1.3.4.2 Design Recommendations on the Audio Interface

Analog Audio Interface

The AVDD33_AC power pin and AVSS_AC GND pin must be isolated from the 3.3 V power
and digital GND respectively. The AC_VREF pin needs to connect a 10 µF filter capacitor

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and a 100 nF filter capacitor, and the 100 nF filter capacitor must be placed close to the chip
pin. See Figure 1-18.

Figure 1-18 Schematic diagram of the power design for the audio module

 AC_INL and AC_INR can be used as the Line_In or MIC_In (single-ended MIC inputs
of the audio-left channel and audio-right channel, or the positive end and negative end of
the differential MIC input. For details, see Figure 1-19 and Figure 1-20) input channels.

Figure 1-19 Schematic diagram of the single-ended MIC input for the audio part

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Figure 1-20 Schematic diagram of the differential MIC input for the audio part

 If the input device is a passive MIC device, MIC_BIAS (MIC bias voltage) must be
added to the input signal. See Figure 1-21. If the input device is an active line-in device
(such as a PC), no bias is required.
 The audio input signal is isolated by using a 4.7 µF capacitor that is placed close to
Hi3518E V20X. See Figure 1-21.

Figure 1-21 Schematic diagram of the MIC_BIAS and input signal for the audio module

 The full-scale amplitude of the single-ended input of AC_INL and AC_INR is 2.8 Vpp
(the maximum amplitude of the differential input is 5.6 Vpp). The full-scale output
amplitude of AC_OUTL and AC_OUTR is 2.5 Vpp.
 It is recommended that the external audio operational amplifier and filter circuit be
connected to the audio output pins AC_OUTL and AC_OUTR. See Figure 1-22.

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Figure 1-22 Schematic diagram of the audio operational amplifier output

 The following are the overall design recommendations (including but not limited to) for
the intercom application scenario:
− Ensure that the MIC and speaker are as far as possible to minimize coupling between
them.
− The MIC must be sealed to prevent sound passing from the mechanical part to the
MIC. The speaker should also be sealed.
− Ensure that the size of the speaker cavity opening is more than 15% of the sectional
area of the cavity. Typically, a larger sound cavity indicates better low-frequency
audio quality but poorer echo cancellation effect.
− The MIC opening is typically a round hole with 0.8−1.2 mm diameter. No sound
cavity is designed for the MIC, that is, the MIC opening is a straight hole.
− The MIC is sealed with rubber or foam to prevent the crosstalk of the speaker in the
IP camera or crosstalk to the MIC due to the sound vibration of the IP camera. Ensure
that there is no crosstalk and resonance in the IP camera.

The preceding recommendations are the audio design recommendations on the mobile phones of Huawei
Device. The structure and application scenario of the IPC as well as the audio design requirements vary
according to the IPC model. Therefore, the preceding recommendations serve only as a reference for the
audio design of customers. It is not guaranteed that the product designed based on these
recommendations can meet certain requirements. However, it is considered that these recommendations
facilitate the audio circuit design of the IPC.

I2S Interface
Hi3518E V20X supports one inter-IC sound (I2S) interface. The I2S signals multiplexed with
the GPIO (GPIO1_0 to GPIO1_6), UART1/UART2, and JTAG pins are from the same source.
Figure 1-23 and Figure 1-24 show the 5-wire connection in I2S master mode and I2S slave
mode respectively.

Figure 1-23 5-wire connection in I2S master mode

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Figure 1-24 5-wire connection in I2S slave mode

The audio coder/decoder (CODEC) and I2S interface cannot be used at the same time.

1.3.5 VI Interface
1.3.5.1 Features
Hi3518E V20X has one multi-function VI interface that supports the parallel CMOS,
MIPI/LVDS/HiSPI, and BT.656/BT.601/BT.1120 video data. The pin functions can be
switched by configuring the corresponding registers. For details, see the description of the VI
interface in the Hi3518E V20X/Hi3516C V200 Economical HD IP Camera SoC Data Sheet.

1.3.5.2 Design Recommendations

 When the VI interface connects to the MIPI/HiSPI/LVDS interface of the sensor:
− The level of DVDD3318_SENSOR needs to be consistent with the I/O level of the
connected sensor. AVDD3318_MIPI needs to be supplied with the 1.8 V power.
− When the sensor with the 1.8 V I/O level is connected, the 1.8 V power can be
provided for both DVDD3318_SENSOR and AVDD3318_MIPI.
− The power supplies of DVDD3318_SENSOR and AVDD3318_MIPI can be
combined into a 1.8 V power supply.
− MIPI_D[0:3] can interconnect with the sensor data lanes in any sequence (the default
sequence is MIPI_D0 to MIPI_D3), whereas MIPI CLK interconnects with the sensor
data lanes in a fixed sequence and does not support the out-of-order mode.
− When the interconnected sensor has fewer than four lanes, the remaining data lane
pins can be floated.
 When the VI interface interconnects with the parallel CMOS interface of the sensor:
− The power supplies of DVDD3318_SENSOR, AVDD3318_MIPI, and
DVDD3318_VI can be combined into a 1.8 V or 3.3 V power supply (the level must
be consistent with the I/O level of the interconnected sensor).
− It is recommended that the 14-bit sensor be connected to D0−D13 in sequence (the
reverse order D13−D0 is also supported).
− It is recommended that the 12-/10-bit sensor be connected to D0−D11/D0−D9 in
sequence (the interconnection of any consecutive 12/10 bits is supported).

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− The horizontal sync (HS) and vertical sync (VS) signals must be those multiplexed on
GPIO1_5 and GPIO1_4.
− The software configuration must match the hardware design. The unused pins need to
be configured as GPIO outputs and floated.
 When the VI interface interconnects with the BT.1120 data signals:
− The Y data signal and the C data signal interconnect with the upper eight bits and
lower eight bits of the VI interface respectively (Y and C data signals can be
switched).
− The HS and VS signals are those multiplexed on GPIO0_6 and GPIO0_7.
− The software configuration must match the hardware design. The unused pins need to
be configured as GPIO outputs and floated.
 When the VI interface interconnects with the BT.656 data signals, the BT.656 data
signals interconnect with the VI interface in the sequence of D0−D7 (any consecutive
eight bits). The remaining VI pins can be configured as GPIO outputs and floated.
 When the VI interface interconnects with the BT.601 data signals:
− The BT.601 data signals interconnect with the VI interface in the sequence of D0−D7
(any consecutive eight bits). The remaining VI pins can be configured as GPIO
outputs and floated.
− The HS and VS signals are those multiplexed on GPIO0_6 and GPIO0_7.

 When the CMOS interface of the sensor is connected, the HS and VS signals must be
those multiplexed on GPIO1_5 and GPIO1_4.
 When the BT.1120 data signals are connected, the HS and VS signals are those
multiplexed on GPIO0_6 and GPIO0_7.

Figure 1-25 VI HS and VS signals

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The I/O level of GPIO1_0 to GPIO1_6 is consistent with that of DVDD3318_VI. When the
seven pins are used as GPIO pins, the interface level of the interconnected component must be
consistent with the pin level.

Table 1-8 describes the design recommendations on the default interconnection mode of the
VI interface.

Table 1-8 Design recommendations on the default interconnection mode of the VI interface
Signal Interconnection Interconnectio Interconnectio Interconnecti Interconnectio
with the n with the n with the on with the n with the
MIPI/HiSPI/LV CMOS BT.1120 Data BT.601 Data BT.656 Data
DS Interface of Interface of the Signals Signals Signals
the Sensor Sensor
MIPI_D3 Connect to sensor Connect to the Connect to the Connect to the Connect to the
M/VI_CL data lane 3. sensor pixel BT.1120 pixel BT.601 pixel BT.656 pixel
K clock. clock. clock. clock.
MIPI_D3 Connect to Connect to Connect to Connect to
P/VI_DA sensor data 0. BT.1120 data 0. BT.601 data 0. BT.656 data 0.
TA0
MIPI_D2 Connect to sensor Connect to Connect to Connect to Connect to
M/VI_DA data lane 2. sensor data 7. BT.1120 data 7. BT.601 data 7. BT.656 data 7.
TA7
MIPI_D2 Connect to Connect to Configure the Configure the pin
P/VI_DA sensor data 8. BT.1120 data 8. pin as GPIO as GPIO output
TA8 output and float and float it.
it.
MIPI_D1 Connect to sensor Connect to Connect to Connect to Connect to
M/VI_DA data lane 1. sensor data 1. BT.1120 data 1. BT.601 data 1. BT.656 data 1.
TA1
MIPI_D1 Connect to Connect to Connect to Connect to
P/VI_DA sensor data 2. BT.1120 data 2. BT.601 data 2. BT.656 data 2.
TA2
MIPI_D0 Connect to sensor Connect to Connect to Connect to Connect to
M/VI_DA data lane 0. sensor data 5. BT.1120 data 5. BT.601 data 5. BT.656 data 5.
TA5
MIPI_D0 Connect to Connect to Connect to Connect to
P/VI_DA sensor data 6. BT.1120 data 6. BT.601 data 6. BT.656 data 6.
TA6
MIPI_CK Connect to the Connect to Connect to Connect to Connect to
P/VI_DA sensor differential sensor data 4. BT.1120 data 4. BT.601 data 4. BT.656 data 4.
TA4 clock.
MIPI_CK Connect to Connect to Connect to Connect to
M/VI_DA

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Signal Interconnection Interconnectio Interconnectio Interconnecti Interconnectio

with the n with the n with the on with the n with the
MIPI/HiSPI/LV CMOS BT.1120 Data BT.601 Data BT.656 Data
DS Interface of Interface of the Signals Signals Signals
the Sensor Sensor
TA3 sensor data 3. BT.1120 data 3. BT.601 data 3. BT.656 data 3.
GPIO1_6/ Configure these Connect to Connect to Configure these Configure these
VI_DATA pins as GPIO sensor data 9. BT.1120 data 9. pins as GPIO pins as GPIO
9 outputs and float outputs and outputs and float
them. float them. them.
GPIO1_1/ Connect to Connect to
VI_DATA sensor data 10. BT.1120 data 10.
10
GPIO1_3/ Connect to Connect to
VI_DATA sensor data 11. BT.1120 data 11.
11
GPIO1_2/ Connect to Connect to
VI_DATA sensor data 12. BT.1120 data 12.
12
GPIO1_0/ Connect to Connect to
VI_DATA sensor data 13. BT.1120 data 13.
13
GPIO1_5/ Connect to the Connect to
VI_VS sensor VS signal. BT.1120 data 14.
GPIO1_4/ Connect to the Connect to
VI_HS sensor HS signal. BT.1120 data 15.
Flash_trig/ Configure these Connect to the Connect to the
VI_VS pins as GPIO BT.1120 VS BT.601 VS
outputs and float signal. signal.
them.
Shutter_tri Connect to the Connect to the
g/VI_HS BT.1120 HS BT.601 HS
signal. signal.
DVDD33 Connect to 1.8 V Connect to 1.8 V Connect to 1.8 V Connect to 1.8 Connect to 1.8 V
18_VI or 3.3 V digital or 3.3 V digital or 3.3 V digital V or 3.3 V or 3.3 V digital
power based on the power. The pin power. The pin digital power. power. The pin
design of level must be level must be The pin level level must be
GPIO1_0 to consistent with consistent with must be consistent with
GPIO1_6. the I/O level of the I/O level of consistent with the I/O level of
the the the I/O level of the
DVDD33 Connect to the 1.8 interconnected interconnected the interconnected
18_Sensor V digital power. sensor. BT.1120 data interconnected BT.656 data
AVDD33 Connect to the 1.8 signals. BT.601 data signals.
18_MIPI V digital power. signals.

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1.3.6 VO Interface
1.3.6.1 Features
Hi3518E V20X has one video output (VO) interface that is multiplexed with the MAC
interface. The VO interface supports the ITU-R BT.656 and liquid crystal display (LCD)
RGB565 outputs. For details, see the description of the VO interface in the Hi3518E
V20X/Hi3516C V200 Economical HD IP Camera SoC Data Sheet.

1.3.6.2 Design Recommendations

 The VO interface is multiplexed with the MAC interface. If the MAC interface is used,
the VO interface cannot be used.
 The VO interface supports external row/field synchronization when it interconnects to
the LCD by providing the HS and VS signals. It also supports 6-/8-bit serial output.

1.3.7 SDIO Interface

1.3.7.1 Features
Hi3518E V20X has two SDIO interfaces. One supports the SDIO 2.0 protocol and is
multiplexed with the MAC interface, and the other is an independent SDIO interface that
supports the secure digital extended capacity (SDXC) card and secure digital high capacity
(SDHC) card. For details, see the description of the SDIO interface in the Hi3518E
V20X/Hi3516C V200 Economical HD IP Camera SoC Data Sheet.

1.3.7.2 Design Recommendations

 For the SDIO 2.0 interface, the DATA, DETECT, and CMD signals must connect to 10
kΩ pull-up resistors and then to the 3.3 V power.
 For the SDXC, the DATA and CMD signals must connect to 10 kΩ pull-up resistors and
then to the SDIO_VOUT pin.
 For the CARD_DETECT and CWPR signals:
− When the SD card is connected, CARD_DETECT and CWPR must connect to 10 kΩ
external pull-up resistors.
− When the TF card is connected, SDIO0_CARD_DETECT must connect to a 10 kΩ
external pull-up resistor, and SDIO0_CWPR must connect to a 4.7 kΩ external pull-
down resistor.
− When the Wi-Fi, 4G, or IC module that is not related to the DETECT and CWPR
applications is connected, SDIO0_CARD_DETECT and SDIO0_CWPR must
connect to 4.7 kΩ external pull-down resistors.

For details about how to use SDIO interfaces that function as the GPIO interfaces, see the
description of GPIO interfaces in the Hi3518E V20X/Hi3516C V200 Economical HD IP
Camera SoC Data Sheet.

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1.3.8 SPI and I2C Interface

1.3.8.1 Features
For details, see the description of the SPI and inter-integrated circuit (I2C) interface in the
Hi3518E V20X/Hi3516C V200 Economical HD IP Camera SoC Data Sheet.

1.3.8.2 Design Recommendations

 The Hi3518EV20X has two groups of SPI pins. SPI0 is used to configure the sensor, and
the interface level can be 1.8 V or 3.3 V. SPI1 is used to connect to a peripheral, and the
interface level must be 3.3 V.
 The Hi351EV20X has three groups of I2C pins. I2C0 is used to configure the sensor and
is multiplexed with SCLK and SDO of SPI0, and the interface level can be 1.8 V or 3.3
V. I2C1 is used to connect to a peripheral and is multiplexed with SCLK and SDO of
SPI1, and the interface level must be 3.3 V. I2C2 is used to connect to a peripheral, and
the interface level must be 3.3 V.

1.3.9 RTC
1.3.9.1 Features
For details, see the description of the RTC in the Hi3518E V20X/Hi3516C V200 Economical
HD IP Camera SoC Data Sheet.

1.3.9.2 Design Recommendations

The timing precision of the embedded RTC depends on the external crystal. Select an
appropriate crystal based on its frequency error and temperature drift. If high timing precision
is required, the external high-precision RTC is recommended.

1.3.10 PWM Interface

1.3.10.1 Features
For details, see the description of the pulse-width modulation (PWM) interface in the
Hi3518E V20X/Hi3516C V200 Economical HD IP Camera SoC Data Sheet.

1.3.10.2 Design Recommendations

PWM0 is used for adjusting the voltage of the core power. The unused PWM interfaces can
be multiplexed as GPIOs.

1.3.11 Processing of Unused Pins

Table 1-9 describes the recommendations on processing unused pins.

Table 1-9 Recommendations on processing unused pins

Functional Module Pin Recommended Processing

Method

JTAG JTAG_TCK Configure these pins as GPIO

outputs and float them externally.
JTAG_TMS

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Functional Module Pin Recommended Processing

Method
JTAG_TRSTN
JTAG_TDO
JTAG_TDI
JTAG_EN Connect this pin to a 4.7 kΩ pull-
down resistor.
SPI0/1 SPI0_SCLK Configure these pins as GPIO
outputs and float them externally.
SPI0_SDO
SPI0_SDI
SPI0_CSN
SPI1_SCLK
SPI1_SDO
SPI1_SDI
SPI1_CSN
SAR_ADC SAR_ADC_CH0/1/2/3 Configure these pins as GPIO
outputs and float them externally.
Audio CODEC AVDD33_AC Supply power to this pin.
USB AVDD33_USB Supply power to this pin.
USB_OVRCUR Configure this pin as GPIO output
and float it externally.
USB_POWER_EN Configure this pin as GPIO output
and float it externally.
RTC ADDD33_RTC Supply power to this pin.
AVDD_BAT Float this pin.
RTC_IN Float this pin.
RTC_OUT Float this pin.

1.3.12 Sensor Board Design

 To ensure picture quality, it is recommended that the low dropout regulator (LDO) be
used to supply power to the sensor. Special attention needs to be paid to the sensor
analog power and PLL power filtering. The current of the sensor core power is large in
general. Therefore, the LDO efficiency and heat dissipation performance need to be
considered during sensor design.
 The analog power and GND pins must be isolated from the digital power and GND pins
to avoid interference and ensure picture quality.

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 If the sensor board is connected to the main board by using a connector, to avoid signal
quality deterioration, ensure that current return GNDs are sufficient for the data signals
from the connector during connector design.

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2 PCB Design Recommendations

2.1 Small System

2.1.1 Power Supplies for the Small System
2.1.1.1 Core Power

Routing Mode and Filter Capacitor Layout

The type, quantity, and layout of filter capacitors for the core power must be designed by
following those on the Hi3518E V20X demo board. For details, see the schematic diagram of
the Hi3518E V20X demo board. Figure 1-8 and Figure 1-9 show the type of filter capacitors
for the core power of Hi3518E V20X and Hi3516C V200 respectively.
The PCB design rules of the core power are as follows: the core power supplies power by
using the power plane (the width of the copper sheet is designed based on the 1 A through-
current capability), and each 1 µF filter capacitor must be placed close to the power pin to
reduce the parasitic inductance. Figure 2-1 and Figure 2-2 show the core power pins for
Hi3518E V20X and Hi3516C V200 respectively. Note the following when connecting
decoupling capacitors to these pins:
Hi3518E V20X:
 Place a 10 µF capacitor on the power channel.
 Place a 4.7 µF capacitor, a 1 µF capacitor, and a 100 nF capacitor close to J5, K5, K6, L6,
L7, and L8.
 Place a 2.2 µF capacitor and two 1 µF capacitors close to E5 to E9.
 Place a 1 µF capacitor close to K11.
 Place a 1 µF capacitor close to F11.
Hi3516C V200:
 Place a 10 µF capacitor on the power channel.
 Place a 2.2 µF capacitor and two 1 µF capacitors close to M6, N6, P7, and P8.
 Place a 100 nF capacitor and a 4.7 µF capacitor close to P10 and P11.
 Place a 1 µF capacitor close to M13, L13, and K13.
 Place a 1 µF capacitor close to H11 and H12.

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 Place a 1 µF capacitor close to H7 and H8.

Figure 2-1 Core power pins for Hi3518E V20X

Figure 2-2 Core power pins for Hi3516C V200

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2.1.1.2 DDR Power

The DDR circuit design described in this section applies only to Hi3518E V200 and Hi3518E V201. The
DDR circuit design for Hi3516C V200 is described in chapter 4 "Differences Between Hi3518E V20X
and Hi3516C V200 and Design Recommendations for Hi3516C V200."
 In the design of the DDR_I/O power, you are advised to place decoupling capacitors
close to the DDR_I/O power pin of Hi3518E V20X and connect at least one 10 µF
grounded filter capacitor on the DDR_I/O power channel.
 In the design of the DDR_Vref (DDR reference voltage), you are advised to connect the
DDR_Vref power module directly to the DDR_Vref ball of the chip to supply power by
using traces that are as wide as possible at the top layer, and place the power module
close to the chip pin.
 The design recommendations on the DDR_PLL power are as follows:
− Isolate the DDR_PLL power from other power supplies by using 1 kΩ@100 MHz
EMI beads.
− Prevent the decoupling capacitors for the DDR_PLL power from sharing the GND
via with other GNDs.

Figure 2-3 PCB design of AVDD_DDRPLL

During the PCB design of AVDD_DDRPLL, the 100 nF filter capacitor (C14) must be placed
close to the AVDD_DDRPLL pin, and must connect to the GND plane through separate vias
(it cannot share the GND via with the GNDs of the other modules).

2.1.1.3 I/O Power

In the I/O power design, at least one decoupling capacitor with high capacitance needs to be
placed on the DVDD33 power channel, and one 1 µF decoupling capacitor needs to be placed
close to each DVDD33 power pin. For details, see the PCB design documents of the Hi3518E
V20X demo board.

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2.1.2 Clock Circuit

The power and GND pins of the Hi3518E V20X PLL unit include AVDD11_PLL,
AVDD33_PLL, and AVSS_PLL. You are advised to design the PCB based on the following
guidelines:
 Isolate the 1.1 V PLL power (AVDD11_PLL) from the 1.1 V digital power by using a 1
kΩ@100 MHz EMI bead. The level deviation of the 1.1 V power must be within ±5%.
 Isolate the 3.3 V PLL power (AVDD33_PLL) from the 3.3 V digital power by using a 1
kΩ@100 MHz EMI bead. The level deviation of the 3.3 V power must be within ±5%.
 Combine the decoupling capacitors of AVDD11_PLL and AVDD33_PLL with the EMI
beads to form the π-shape filter circuit. The decoupling capacitors cannot share the GND
via with other GNDs. AVSS_PLL is the GND pin of the PLL module.

Figure 2-4 PCB design of the AVDD11_PLL power and GND pins

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Figure 2-5 PCB design of the AVDD33_PLL power and GND pins

During the PCB design, the 100 nF decoupling capacitors (C33 and C34) must be placed
close to the chip pins (AVDD11_PLL and AVDD33_PLL). The GND of the decoupling
capacitors must be isolated from other modules especially the digital GND (the GND of the
decoupling capacitors cannot share the GND via with the GND of other modules) and directly
connects to the AVSS_PLL ball.
 Ensure that the traces of the crystal oscillator circuit for the system clock are as short as
possible, and the traces are surrounded with GND traces.

Figure 2-6 PCB design of the 24 MHz system clock and RTC

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In Figure 2-6, the blue areas indicate the GND copper sheets, the yellow areas indicate the 24
MHz system clock and related traces, and the light green areas indicate the RTC module and
related traces.

2.1.3 ETH Signals

You are advised to design the PCB routing based on the following guidelines to reduce bus
signal crosstalk:
 Ensure that the spacing between adjacent signal traces complies with the 3W rule.
 Connect 22 Ω resistors in series to the clock signals at the source end.
 Connect 22 Ω resistors in series to the data signals at the source end.
 Avoid routing signal traces across power plane splits to maintain complete reference
planes for signal traces.
 Ensure that the signal traces in each differential trace pair (MDI+_0/MDI−_0 and
MDI+_1/MDI−_1, that is, traces between the network port PHY and the network
transformer) have the same length, the length deviation falls within ±5 mils, and the
impedance of each differential trace falls within 100 Ω±10%.

2.2 Typical Peripheral Interfaces

2.2.1 USB Port
PCB Routing
You are advised to design the PCB routing based on the following guidelines to provide the
480 MHz high-speed USB 2.0 port:
 Ensure that the differential data traces are as short and straight, the traces in each
differential trace pair have the same length, and the length deviation of each pair of
differential signal traces falls within ±5 mils.
 Ensure that the impedance of each differential data trace falls within 90 Ω±10%.
 Route differential data traces by referencing a complete plane (the GND layer is
recommended), and do not cross plane splits.
 Place the REXT resistor close to Hi3518E V20X.

USB Power Supply

The power pin and GND pin for the USB functional unit are AVDD33_USB and AVSS_USB
respectively. In the design, you are advised to isolate the 3.3 V analog USB power from the
3.3 V digital power on the board by using a 1 kΩ@100 MHz EMI bead, and place filter
capacitors close to AVDD33_USB and AVSS_USB.

Routing of the USB Protection Circuit

A protection circuit is required on the USB port to implement electrostatic discharge (ESD)
protection. To protect signals along USB traces from being attenuated by protective
components, you are advised to design the PCB based on the following guidelines:
 Place protective components close to the USB port connector.

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 Use the transient voltage suppressor (TVS) diodes with low parasitic capacitance as
protective components.
 Ensure that the parasitic capacitance of the protective components on the high-speed
USB 2.0 port is less than 2 pF.

2.2.2 Audio Circuit Design

Hi3518E V20X provides an analog audio CODEC. The routing requirements are as follows:
 Place the 100 nF decoupling capacitor of AC_VREF close to the master chip. See Figure
2-7.
 Isolate the AVDD33_AC power from the 3.3 V digital power by using a 1 kΩ@100 MHz
EMI bead. It is recommended that the power and capacitors form a π-shape filter circuit.
See Figure 2-8.
 Isolate the GNDs of the decoupling capacitors and the AVSS_AC ball from other digital
GNDs. The GNDs of the decoupling capacitors and the AVSS_AC ball cannot share the
vias with other GND networks. See Figure 2-8.
 Divide the signal into two channels at the MIC_BIAS pin of the chip end when dual MIC
inputs are used. See Figure 2-9.
 Route the analog audio input and output signal traces by referencing a complete GND
layer. Ensure that the signal traces are as short and wide as possible, the signal traces are
surrounded with GND traces, and the routing layer is not changed. See Figure 2-10.
 Surround the analog audio input and output signal traces with GND traces and isolate
them from the digital GND and other high-speed digital signal traces to avoid
interference. See Figure 2-11 and Figure 2-12.

Figure 2-7 PCB design of the AC_Vref power

In Figure 2-7, the yellow areas indicate the signal traces of AC_Vref, and the blue areas
indicate the GND copper sheets for AC_Vref.

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Figure 2-8 PCB design of AVDD33_AC and AVSS_AC

In Figure 2-8, the yellow areas indicate the power signals of AVDD33_AC, the blue areas
indicate the GND copper sheets, and the green areas indicate LB6 and C8.

Figure 2-9 PCB design of MIC_BIAS when dual MIC inputs are used

In Figure 2-9, the yellow areas indicate the audio input signals, the white areas indicate the
audio output signals, the green areas indicate the MIC_bias signals, and the blue areas
indicate the GND copper sheets. The traces on the top layer are routed by using the GND
layer as the reference plane and are isolated from adjacent high-speed digital signal traces.

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Figure 2-10 Mother board PCB design of the audio input and output signal traces

In Figure 2-10, the yellow areas indicate the audio input signals, the white areas indicate the
audio output signals, the green areas indicate the MIC_bias signals, and the blue areas
indicate the GND copper sheets. The traces on the top layer are routed by using the GND
layer as the reference plane and are isolated from high-speed digital signal traces.

Figure 2-11 PCB design for surrounding the audio signal traces with GND traces and isolating
them from other high-speed signal traces (1)
High-speed digital signal traces Low-speed digital signal traces
of the SDIO module of the SDIO module

Vias on the GND traces for

surrounding audio signal traces

In Figure 2-11, the green areas indicate the audio signal traces (at the top layer), the blue areas
indicate the high-speed digital signal traces of the SDIO module, the yellow areas indicate the
low-speed signal traces of the SDIO module (at the bottom layer), and the areas between the
yellow lines and green lines indicate the vias on the GND traces for surrounding audio signal
traces. By using the preceding PCB design, the vias on the GND traces for surrounding audio
signal traces are isolated from other high-speed signal traces.

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Figure 2-12 PCB design for surrounding the audio signal traces with GND traces and isolating
them from other high-speed signal traces (2)

In Figure 2-12, the red lines indicate the low-speed signal traces of the SDIO module, the blue
lines indicate the high-speed signal traces of the SDIO module, and the parts in the yellow
circles indicate the GND vias of the audio module. To protect the audio signal traces from
interference caused by the high-speed signal traces of the SDIO module through the GND
vias of the audio module, the GND copper sheets at the bottom layer are removed.

2.2.3 VI Interface
Hi3518E V20X has one VI interface. The routing requirements are as follows:
 When the VI interface needs to support the interconnection with the sensor with the
differential interface and that with the single-ended interface:
− Route the five pairs of MIPI signal traces in differential mode. Ensure that the signal
traces in each differential trace pair have the same length, the length deviation of each
pair of differential signal traces fall within ±5 mils, the length deviation between two
pairs of differential signal traces fall within ±100 mils based on the clock signal, and
the impedance of each differential signal trace fall within 100 Ω±10%. Route other
signal traces in single-ended mode. Ensure that the impedance of each single-ended
signal trace fall within 50 Ω±10%, and the trace spacing comply with the 3W rule.
− The VI interface supports the 1.8 V and 3.3 V power domains. You are advised to
route the traces of the VI data signal, HS signal, VS signal, and SPI0 at the top layer
by referencing the GND plane. This avoids the impedance mismatch issue when
signal traces are routed by referencing the 1.8 V or 3.3 V power plane.
− If the 1.8 V power domain is selected for the VI interface, it is recommended that the
signal traces be 4 inches or shorter.
 When the VI interface needs to support the interconnection with the sensor with the
differential interface:
Route the five pairs of MIPI signal traces in differential mode. Ensure that the signal
traces in each differential trace pair have the same length, the length deviation of each
pair of differential signal traces fall within ±5 mils, the length deviation between two
pairs of differential signal traces fall within ±100 mils based on the clock signal, and the
impedance of each differential signal trace fall within 100 Ω±10%.

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 When the VI interface needs to support the interconnection with the sensor with the
single-ended interface or BT.656/BT.1120 data signals:
Router the signal traces in single-ended mode. Ensure that the impedance of each single-
ended signal trace fall within 50 Ω±10%, and the trace spacing comply with the 3W rule.

Figure 2-13 PCB design of the VI interface

In Figure 2-13, the yellow areas indicate the five pairs of MIPI differential signal traces, the
green areas indicate other single-ended data signal traces of the VI interface, and the light blue
areas indicate the sensor configuration interface, reset, and clock signal traces.

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3 Design Recommendations on ESD and

Heat Dissipation

3.1 Background
Hi3518E V20X has passed the ±2 kV ESD test and complies with the industry standard.
However, you still need to evaluate the design of the board hardware and entire system based
on the ESD protection requirements of the product. This document provides some
recommendations on the ESD design of the entire system.

3.2 ESD Design Recommendations

 During the design of the 24 MHz system clock, use the 4-pin SMD crystal, and fully
connect its two GND pins to the board GND to improve the anti-ESD capability of the
system clock. Keep other signal traces far away from the crystal and avoid routing signal
traces under the crystal.
 During the PCB layout design, keep the circuit of the small system away from metal
interfaces to reduce the ESD risk of the entire system.
 Add ESD protection components for peripheral interfaces (such as the audio/video
input/output interface, USB port, network port, and alarm port) to improve the anti-ESD
capability.
 When the entire system is designed as a floating ground device, never use GND plane
splits on the board.
− Design only one digital GND on the board and never split the protective GND.
− Use metal vias as the positioning holes of the board and connect them to the digital
GND, and ensure that the board GND and the metal cover are completely in contact
through the positioning holes.
 When the entire system is designed as a grounding device, connect the metal cover to the
earth, and connect the protective GND splits to the board digital GND in single-point
mode. Ensure that the single point is far away from the circuits of the small system and
close to the power connector of the entire system.
 Use the metal cover for the interface connectors (such as the HDMI and USB port with
positioning screws or the RJ45 connector with a tab), and ensure that the connectors and
the metal cover of the entire system are completely in contact (using the conductive
pillar or conductive gasket if necessary).

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 Design the positioning holes of the board close to the backplane connectors and far away
from the small system, and ensure that the board GND and the metal cover of the entire
system are completely in contact.
 You are advised to use the full metal cover for the entire system. The design of a metal
base cover and a plastic upper cover may cause a high ESD risk, because the space
radiation is strong, and therefore a metal shielding cover is required.
 You are advised not to use the full plastic cover. If the full plastic cover design is used,
you need to lower ESD test standards or take more measures to shield the space radiation
(for example, installing a metal shielding cover on the back side of the small system).
You need to evaluate the preceding recommendations based on your standards and project
experience.

3.3 Recommendations on Heat Dissipation Design

3.3.1 Operating Conditions
For details about the power consumption, temperature, and thermal resistance parameters for
Hi3518E V20X, see the electrical specifications in the Hi3518E V20X/Hi3516C V200
Economical HD IP Camera SoC Data Sheet.

3.3.2 Reference Design for Circuit Heat Dissipation

The thermal design recommendations in this document are targeted at the small-sized board
with high thermal design requirements, such as the board that integrates Hi3518E V20X and
the sensor.

3.3.2.1 Principles

Power Supply
Considering that the power consumption varies according to the power supplies, note the
following when implementing multi-power solutions on a board:
 Do not design too many power conversion levels in a board power tree (too many power
conversion levels result in low power conversion efficiency), and do not design too many
separate power branches in the power tree (too many power modules occupy much PCB
space).
 Minimize the use of LDO for converting the power with large voltage difference to
reduce the heat generated during power conversion.
 Choose power chips with high conversion efficiency.
 Select the low-power mode for the functional modules on the board (for example, select
the IR-CUT that can retain the state after state switching even if the driving power of the
IR-CUT is disconnected. In this way, power consumption is reduced).

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 Set the unused modules (such as the USB flash drive and SD card) to the low-power
mode in the actual product application.
You need to design an appropriate power tree and select an appropriate power solution based
on the product form, power supply requirements, and PCB space.

3.3.2.2 PCB

Component Layout
Lay out components based on the product architecture and heat dissipation design as follows:
 Evenly place the components that consume a large amount of power (such as the
Hi3518E V20X, power supplies, sensor, network port PHY) on the board to avoid
overheating of some areas and affect the component reliability. It is recommended that
Hi3518E V20X and power supplies be placed close to the positioning hole so that most
of the heat generated on the board is dissipated through the screw holes and cover to the
outside.
 Keep thermo-sensitive components (such as the sensor and flash memory) as far away
from power-consuming components as possible (the sensor and flash memory can be
placed at a layer that is different from the layer where power-consuming components are
located). This minimizes the influence of the heat generated by power-consuming
components on the thermo-sensitive components, and avoids thermo-sensitive
component overheating that may affect the system stability and picture quality.
 Expose as much copper on the four screw holes of the PCB as possible to facilitate the
contact between the PCB and the cover.

Trace Routing
The heat dissipation design recommendations for routing traces are as follows:
 Select the full connection style for the vias to improve the chip heat dissipation
efficiency.
 Connect the GND pins and 1.1 V, 1.8 V as well as 3.3 V power pins of Hi3518E V20X to
the power and GND planes by using the copper sheets. When the power over-current
capability is ensured, punch as many vias as possible on the copper sheets to improve the
chip heat dissipation capability.

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Hi3518E V20X/Hi3516C V200 Hardware Design Hi3516C V200 and Design Recommendations for
User Guide Hi3516C V200

4 Differences Between Hi3518E V20X and

Hi3516C V200 and Design Recommendations
for Hi3516C V200

4.1 Differences Between Hi3518E V20X and Hi3516C V200

Hi3518E V200 has embedded 64 MB DDR2 SDRAMs, whereas Hi3518E V201 has
embedded 32 MB DDR2 SDRAMs. Hi3518E V200 and Hi3518E V201 share the same
hardware design and differ only in the capacity of the embedded DDR2 SRAM. The
preceding descriptions in this document apply to both Hi3518E V200 and Hi3518E V201.
Hi3516C V200 supports the external mounted DDR3/DDR3L SDRAM (no embedded
memory). The differences between Hi3516C V200 and Hi3518E V200/Hi3518E V201 in
hardware design are as follows:
 DDR_IO power
 Whether to design DDR signal traces on the PCB
The following sections describe the design recommendations for Hi3516C V200 based on the
differences.

4.2 Design Recommendations for Hi3516C V200

4.2.1 DDR3/DDR3L Interface
4.2.1.1 Introduction
Hi3516C V200 provides one DDRC interface. The width of the data bus is 16 bits and that of
the address bus is 15 bits. For details, see the description of memory interfaces in the
Hi3518E V20X/Hi3516C V200 Economical HD IP Camera SoC Data Sheet.

4.2.1.2 Circuit Design Recommendations

The schematic diagram and PCB design of the DDR must be the same as those of the
Hi3516C V200 demo board.

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4.2.2 Schematic Diagram of the DDR Power

The DDRC of Hi3516C V200 supports the DDR3/3L SDRAM. The voltage of the DDRIO
power is 1.5 V or 1.35 V, and the corresponding reference voltage (Vref) is 0.75 V or 0.675 V.
The DDRIO power of Hi3516C V200 must be consistent with the I/O power of the DDR
SDRAMs.
A separate power chip must be provided on the board to supply power to the DDR3/3L
SDRAM and the 1.5 V or 1.35 V DDR power pins of Hi3516C V200 (VDDIO_DDR and
VDDIO_CK_DDR). The type and quantity of filter capacitors for the DDR power must be the
same as those on the Hi3516C V200 demo board. See Figure 4-1 and Figure 4-2.

Figure 4-1 Filter capacitors for the DDR3/3L power (at the Hi3516C V200 end)

Figure 4-2 Filter capacitors for the DDR3/3L power (at the DDR SDRAM end)

The AVDD_DDRPLL pin must be isolated from the 3.3 V digital power by using a 1
kΩ@100 MHz EMI bead, and the filter capacitors must be placed close to the pin. For details,
see the schematic diagram.

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The 0.75 V/0.675 V power for Vref_CA and Vref_DQ of the DDR3/3L SDRAMs is obtained
after voltage division by using the 1 kΩ±1% resistor. Figure 4-3 shows the reference design of
the DDR3/3L power voltage division network.

VREFDQ and VREFCA must be separately supplied with power.

Figure 4-3 Reference design of the DDR3/3L power voltage division network

4.2.3 PCB Design Recommendations

4.2.3.1 PCB Design of the DDR_IO Power
The DDR_IO power must be designed by following the power design on the Hi3516C V200
demo board. Figure 4-4 shows the filter capacitor layout for the 1.5 V/1.35 V power, and
Figure 4-5 shows the design of the 1.5 V/1.35 V power module and power channel.

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Figure 4-4 Filter capacitor layout for the 1.5 V/1.35 V power

In Figure 4-4, the red areas indicate the decoupling capacitors for the 1.5 V/1.35 V power.

Figure 4-5 Design of the 1.5 V/1.35 V power module and power channels

In Figure 4-5, the yellow areas indicate the 1.5 V/1.35 V power channels.

4.2.3.2 Trace Routing

The DDR routing (including the trace width, spacing as well as length, GND surrounding
design, filtering, and matching mode) of Hi3516C V200 must be designed by completely
following the PCB design of the Hi3516C V200 demo board. Figure 4-6 and Figure 4-7 show
the trace routing at the top layer and the bottom layer respectively.

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Figure 4-6 Trace routing at the top layer

In Figure 4-6, the blue areas indicate the GND planes, and the yellow areas indicate the DDR
signal traces.

Figure 4-7 Trace routing at the bottom layer

In Figure 4-7, the red areas indicate the power planes, and the yellow areas indicate the DDR
signal traces.

4.2.3.3 External Resistor for the DDR SDRAM

A 240 Ω±1% external resistor (ZQ) is selected for the DDR3/3L SDRAM.

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