Scribd
Upload
124 views4 pages

Vinod Physical Design 3+years Exp-1

Uploaded by

vinod
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
124 views4 pages

Vinod Physical Design 3+years Exp-1

Uploaded by

vinod
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

Gaddam Vinod Babu

vinodece7447@gmail.com
+91 8431297978

SUMMARY 3+ years of experience in Physical Design.


 Have experience on floorplan,placement, CTS ,route and signoff .
 Experience in working on 5nm, 7nm and 16nm technologies from leading
foundries Samsung, TSMC.
 Involved in 4 different projects and responsible for block level design
implementation.
 Have Experience using Synopsys tools like DC, ICC2, PT and Calibre.
 Have Knowledge in using Cadence tools like Innovus, Genus.
 Experience on multi voltage design.
 Created voltage islands for Feedthroughs.
 Have Experience in Static Timing Analysis and Low power design techniques.
 Have experience crosstalk fixing, OCV, AOCV and POCV.
 Good Knowledge in writing scripts using Tcl and Perl.
 Have knowledge on Synthesis, DFT and RTL coding using Verilog.
 Have experience in fixing base and metal DRC’s.
 Experience in timing closure at MMMC’s.
 Have experience in fixing timing violations and aslo good understanding of
Synopsis Design Constraints.
 Energized by new challenges; capable of working on own initiative as well as in
team.

ADDITIONAL
QUALIFICATIONS
/AFFILIATIONS

 Secured AIR 7042 in GATE.

EMPLOYMENT
HISTORY

Aug 2020 – till date


DIGICOMM ( QUALCOMM (CLIENT) )

July 2018-August 2020


ALTRAN

EDUCATION

M.Tech – VLSI Design and Embedded System Design (2016- 2019)


Gayatri Vidya Parishad College of Engineering, Obtained: 9.1 CGPA
B.Tech – Electronics and Communication Engineering (2011- 2015)
Lakki Reddy Bali Reddy College of Engineering, Mylavaram, Obtained: 85%

1|P age
PROJECT
EXPERIENCE

Project1- Qualcomm

Description
 Technology Node : 5nm, 12layers
 No. of Blocks handled : 2
 Inst Count : 1 million
 Frequency : 1Ghz
 Macros : 42
 Tools : Icc2 (1st block), cadence Innovus (2nd block)

Responsibilities
 Responsible for hm level implementation from floorplan to signoff.
 Created volatge islands for feedthroughs.
 Performed Macro placement and provided proper channel spacing to avoid
channel congestion.
 Analysed and fixed congestion applying various techniques like using partial
blockages, cell padding, congestion driven placement and congestion driven
restructuring.
 Fixed Max cap, data max tran and clock max tran violations.
 Fixed special max tran violations.
 Implemented timing ecos for setup and hold.
 Fixed secondary grid resistance violations by redrawing the secondary grid.
 Fixed dynamic PDN violations by spreading the clustered cells, appying M2 ,M4
shunting techniques and Decap insertion.
 Fixed antenna violations by applying antenna diodes and metal jumping
techniques.
 Fixed base and metal drcs .
 Fixed PG and signal shorts.
 Ran through FV, PDN, CLP,PV sign off flows.
 Implemented TCL script to fix mismatch fillers, responsible for base violations.
Responsibilities

Project2 - Intel

Description  Technology Node : 7nm, 16 layers


 No. of Blocks handled : 2
 Inst Count : 500k
 Frequency : 450 MHz
 Macros : 55
 Tools : Synopsys Dc,Icc2, PT compiler, Menter graphics calibre.

Responsibilities  Responsible for block level implementation from floorplan to Signoff.


 Fixed TCIC errors in design by following TSMC guidelines.
 Congestion and Timing were the challenges faced.

2|P age
 Written Tcl script to solve boundary cell continuity issue after macro placement.
 Analysed and fixed congestion in various stages by applying different techniques.
 Fixing timing issues in placement stage using path grouping and bound creation.
 Fixed icg setup timing violations, pulse width violations and hold timing issues
in CTS
 Implemented timing ECO’s for DRC, setup, hold, noise, power recovery.
 Fixed timing Drvs like Slow slope and Max cap violations.
 Fixed side branch on output , Logic on Clock Path and Dangling in nets.
 Fixed shorts.
 Fixed Base DRC by applying placement blockages around the pads by following
TSMC guidelines, this is done using tcl scripting.
 Fixed metal DRC like metal spacing , via enclouser, via spacing, cut metal
spacing issues.

Project 3

Description  Technology Node : 16nm/10 layers


 Inst Count : 150k
 Frequency : 1 GHz
 Macros :4
 Tools : Synopsys Icc2, PT compiler and Mentor graphics caliber.
Responsibilities
 Worked on block level design with multiple power domains.
 Created volatge areas for different power domains.
 Worked on floor plan and PnR of the design using Synopsys ICC2 tool.
 Congestion and timing issues are resolved by using various techniques.
 Did signal integrity checks (DRV) and repairs for the design.
 Implemented timing eco at post route stage.

Project 4

Description  Technology No : 16nm/10 layers


 Inst Count : 120k
 Frequency : 500 MHz
 Macros : None
 Tools : Synopsys Icc2, PT compiler and Mentor graphics calibre

Responsibilities  Performed floorplan to route.


 Fixed congestion issue by applying various techniques.
 Solved timing problems using different techniques like increasing placement
effort, creating bounds, creating path groups applying weightage and critical
range to path groups and trail cts for fixing icg violations.
 Fixes timing issues with the help of swaps, upsize and net improvement.
 Implemented ECOs for timing.
 Written TCL scripts to reduce cell density (congestion) as well as routing density

3|P age
for a design.
 Fixed shorts.
 Ran calibre for fixing base and metal drcs.

4|P age

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy