16 Master Slave Flip Flops
16 Master Slave Flip Flops
Y
S S S Q
C C C
Y
R R R Q
FIGURE 5-9
SR Master–Slave Flip-Flop
master–slave triggering approach, since a properly constructed D flip-flop has the
same behavior for both triggering types.
Master–Slave Flip-Flops
The master–slave SR flip-flop, consisting of two latches and an inverter, is shown in
Figure 5-9. The symbol with S, C, and R on it is for the SR latch with a control
input (Figure 5-7), referred to here as a clocked SR latch. The left clocked SR latch
in Figure 5-9 is called the master, the right the slave. When the clock input C is 0,
the output of the inverter is 1. The slave latch is then enabled, and its output Q is
equal to the master output Y. The master latch is disabled, because C is 0. When a
logic-1 clock pulse is applied, the values on S and R control the value stored in the
master latch Y. The slave, however, is disabled as long as the pulse remains at the 1
level, because its C input is equal to 0. Any changes in the external S and R inputs
change the master output Y, but cannot affect the slave output Q. When the pulse
returns to 0, the master is disabled and is isolated from the S and R inputs. At the
same time, the slave is enabled, and the current value of Y is transferred to the out-
put of the flip-flop at Q.
A ModelSim logic simulation illustrating master–slave flip-flop SR behavior is
shown in Figure 5-10. Initially, all values are unknown including the clock C. When
S and R both go to 0, and the clock goes from 1 to 0, the output of the master, Y,
and of the slave, Q, both remain unknown, since the prior value is effectively being
stored. S is at 1 with R at 0 to set the flip-flop in response to the next clock pulse.
When C becomes 1, Y sets to 1. When C becomes 0, the slave copies the value of Y,
setting Q to 1. After S returns to 0, Y and Q remain unchanged, storing the 1 value
through the next clock period. Next, R becomes 1. After the clock-pulse transition
from 0 to 1, the master latch is reset, with Y changing to 0. The slave latch is not
affected, because its C input is 0. Since the master is an internal circuit, its change of
state is not presented at output Q. Even if the inputs S and R change during this
interval and the state of the master latch responds by changing, the output of the
flip-flop remains in its previous state. When the pulse returns to 0, the information
from the master is allowed to pass through to the slave. For the simulation exam-
ple, the value Y = 0 is copied to the slave latch, making the external output Q 0.
ManoCh05v4.fm Page 217 Wednesday, May 2, 2007 6:27 PM
FIGURE 5-10
Logic Simulation of an SR Master–Slave Flip-Flop
Note that these changes are delayed from the pulse changes by gate delays. Also,
the external inputs S and R can change anytime after the clock pulse goes through
its negative transition. This is because, as the C input reaches 0, the master is dis-
abled, and S and R have no effect until the next clock pulse.
The next sequence of signal changes illustrates the “1s catching” behavior of
the SR master–slave flip-flop. A narrow pulse to 1 occurs on S at the beginning of
a clock pulse. The master latch responds to the 1 on S by changing Y to 1. Then S
goes to 0 and a narrow 1 pulse occurs on R. The master latch responds to the 1 on
R by changing Y back to 0. Since there are no further 1 values on S or R, the mas-
ter continues to store 0, which is copied to the slave latch, changing Q to 0, in
response to the clock’s change to 0. Thus, the master latch “caught” both the 1 on
S and the 1 on R. Since the 1 on R was caught last, the output Q remained at 0. In
general, the “correct” response is assumed to be the response to the input values
when the clock goes to 0. So, in this case, the response happens to be correct,
although more by accident with the changing values in the master.
For the next clock pulse, a narrow 1 pulse occurs on S, setting the master
output Y to 1. The clock then goes to 0 and the value 1 is transferred to the slave
latch and appears on Q. In this case, the correct value on Q should be 0, since Q
was 0 before the clock pulse and both S and R are 0 just before the clock goes to
0. Since Q equals 1, due to “1s catching” on S, the flip-flop is in the wrong state.
For the final clock pulse of interest, both S and R become 1 before the clock
goes to 0. This applies the invalid combination to the master latch, making both Y
and Y equal to 1. When the clock changes to 0, the SR latch within the master
sees its inputs change from (0, 0) to (1, 1), causing the master latch to enter an
unknown state, which is immediately transferred to the inputs of the slave,
which also enters an unknown state. This demonstrates that S = 1, R = 1 is an
invalid input combination for the SR master–slave flip-flop.
Now consider a sequential system containing many master–slave flip-flops,
with the outputs of some flip-flops going to inputs of other flip-flops. Assume that
the clock pulses to all of the flip-flops are synchronized and occur at the same
time. At the beginning of each clock pulse, some of the masters change states, but
ManoCh05v4.fm Page 218 Wednesday, May 2, 2007 6:27 PM
all the slaves remain in their previous states. This means that the flip-flop slaves
are still in their original states, while the flip-flop masters have changed to the new
states. After the clock pulse returns to 0, some of the flip-flop slaves change state,
but none of the new states have an effect on any of the masters until the next
pulse. Thus, the states of flip-flops in a synchronous system can change simulta-
neously for the same clock pulse, even though outputs of flip-flops are connected
to inputs of the same or other flip-flops. This is possible because the inputs affect
the state of the flip-flop only while the clock pulse is 1, and the new state appears
at the outputs only after the clock pulse has returned to 0, ensuring that the flip-
flops are not transparent.
For reliable sequential circuit operation, all signals must propagate from the
outputs of flip-flops, through the combinational circuit, and back to inputs of mas-
ter–slave flip-flops, while the clock pulse remains at the logic-0 level. Any changes
that occur at the inputs of flip-flops after the clock pulse goes to the logic-1 level,
whether intentional or not, affect the flip-flop state and may result in the storage of
incorrect values. Suppose that the delay in the combinational circuit is such that S is
still changing after the clock pulse has gone to the logic-1 level. Suppose also that, as
a consequence, the master is set to 1 by the presence of S = 1. When S finally stops
changing, it is at 0, indicating that the state of the flip-flop was not to be changed
from 0. Thus, the 1 value in the master, which will be transferred to the slave, is in
error. There are two consequences of this behavior. First, the master–slave flip-flop is
also referred to as a pulse-triggered flip-flop, since it can respond to input values that
cause a change in state and occur anytime during its clock pulse. Second, the circuit
must be designed so that combinational circuit delays are short enough to prevent S
and R from changing during the clock pulse.
A master–slave D flip-flop can be constructed from the SR master–slave flip-
flop by simply replacing the master SR latch with a master D latch. The resulting
circuit is shown in Figure 5-11. The resulting circuit changes its value on the nega-
tive edge of the clock pulse just as the master–slave SR flip-flop does. However,
the D type of flip-flop does not demonstrate the usual pulse-triggered behavior.
Instead it demonstrates edge-triggered behavior—in this case, negative edge-trig-
gered behavior. Thus, a master–slave D flip-flop constructed as shown is also an
edge-triggered flip-flop.
Edge-Triggered Flip-Flop
An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers
only during a transition of the clock signal. Some edge-triggered flip-flops trigger on
the positive edge (0-to-1 transition), whereas others trigger on the negative edge (1-to-
0 transition), as illustrated in the previous subsection. The logic diagram of a D-type
positive-edge-triggered flip-flop to be analyzed in detail here appears in Figure 5-12.
This flip-flop takes exactly the form of a master–slave flip-flop, with the master a D
latch and the slave an SR latch or a D latch. Also, an inverter is added to the clock
input. Because the master latch is a D latch, the flip-flop exhibits edge-triggered
rather than master–slave or pulse-triggered behavior. For the clock input equal to