NCP1200PAK/D

Rev. 0, May-2001

NCP1200 Literature Pack

 NCP1200
PWM Current Mode Controller
Description

Self-supplied from the DC rail (up to 450V)

Drives external MOSFET

Low standby power

Short circuit protected Applications

Meets next IEA recommendations: PIN < 500mW
Off-line power supplies

Internally fixed frequency at 40kHz, 60kHz and 100kHz
AC-DC adapters & battery chargers

Auxiliary power supplies

Features Benefits

Current mode control
Easier to stabilize and fast response

Self-supplied from the DC rail (lower cost)
Eliminates need for auxiliary winding

Built-in frequency jitter
Reduce EMI

Peak current reduction at no load
Reduces acoustic noise under open circuit conditions

Low standby power <0.5mW
Meets European low power directives

Higher integration than UC384x
Low external parts count

Drives external MOSFET
Offer increase flexibility of design to maximize thermal

performance and scale power requirements
Ordering Information
Device Package Shipping Additional Information
NCP1200P40 PDIP-8 50 per rail
Visit us at onsemi.com/ncp1200
NCP1200D40R2 SO-8 2500 per reel

Datasheet
NCP1200P60 PDIP-8 50 per rail
NCP1200D60R2 SO-8 2500 per reel
Case outline
NCP1200P100 PDIP-8 50 per rail
App note AND8023/D
NCP1200D100R2 SO-8 2500 per reel
Transient and averaged SPICE models available

For details, contact your sales representative, local distributor, or visit

ON Semiconductor
www.onsemi.com
NCP1200

PWM Current-Mode
Controller for Low-Power
Universal Off-Line Supplies
Housed in SO–8 or DIP–8 package, the NCP1200 represents a
major leap toward ultra–compact Switch–Mode Power Supplies. http://onsemi.com
Thanks to a novel concept, the circuit allows the implementation of a
complete off–line battery charger or a standby SMPS with few MARKING
external components. Furthermore, an integrated output short–circuit DIAGRAMS
protection lets the designer build an extremely low–cost AC/DC wall
8
adapter associated with a simplified feedback scheme.
SO–8 1200D
With an internal structure operating at a fixed 40 kHz, 60 kHz or 100 D SUFFIX ALYW
kHz, the controller drives low gate–charge switching devices like an 8 CASE 751
IGBT or a MOSFET thus requiring a very small operating power. 1 1
High
Thanks to current–mode control, the NCP1200 drastically simplifies
Efficiency 8
the design of reliable and cheap off–line converters with extremely
low acoustic generation and inherent pulse–by–pulse control. DIP–8
NCP1200P
P SUFFIX
When the current setpoint falls below a given value, e.g. the output CASE 626
AWL
power demand diminishes, the IC automatically enters the skip cycle 8 YYWW
mode and provides excellent efficiency at light loads. Because this 1 1
occurs at low peak current, no acoustic noise takes place.
Finally, the IC is self–supplied from the DC rail, eliminating the A = Assembly Location
L = Wafer Lot
need of an auxiliary winding. This feature ensures operation in Y, YY = Year
presence of low output voltage or shorts. W, WW = Work Week
Features
Allows Smaller,
Lower Cost Transformer
• No Auxiliary Winding Operation
PIN CONNECTIONS
• Internal Output Short–Circuit Protection Meet Next IEA
• Extremely Low No–Load Standby Power Requirements Adj 1 8 HV
• Current–Mode with Skip–Cycle Capability FB 2 7 NC
• Internal Leading Edge Blanking Stable and
CS 3 6 VCC
Fast Response
• 110 mA Peak Current Source/Sink Capability Gnd 4 5 Drv
• Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz
• Direct Optocoupler Connection For Lower EMI (Top View)
• Built–in Frequency Jittering
• SPICE Models Available for TRANsient and AC Analysis
• Internal Temperature Shutdown ORDERING INFORMATION
See detailed ordering and shipping information on the
Typical Applications Fast, Easy complete version of this data sheet.
• AC/DC Adapters Design
• Off–line Battery Chargers
• Auxiliary/Ancillary Power Supplies (USB, Appliances, TVs, etc.)

 Semiconductor Components Industries, LLC, 2001 1

March, 2001 – Rev. 4
NCP1200

PWM Current-Mode
Controller for Low-Power
Universal Off-Line Supplies
Housed in SO–8 or DIP–8 package, the NCP1200 represents a
major leap toward ultra–compact Switch–Mode Power Supplies. http://onsemi.com
Thanks to a novel concept, the circuit allows the implementation of a
complete offline battery charger or a standby SMPS with few external MARKING
components. Furthermore, an integrated output short–circuit DIAGRAMS
protection lets the designer build an extremely low–cost AC/DC wall
8
adapter associated with a simplified feedback scheme.
SO–8 200Dy
With an internal structure operating at a fixed 40 kHz, 60 kHz or 100 D SUFFIX ALYW
kHz, the controller drives low gate–charge switching devices like an 8 CASE 751
IGBT or a MOSFET thus requiring a very small operating power. 1 1
Thanks to current–mode control, the NCP1200 drastically simplifies
the design of reliable and cheap offline converters with extremely low 8
acoustic generation and inherent pulse–by–pulse control. DIP–8
1200Pxxx
P SUFFIX
When the current setpoint falls below a given value, e.g. the output CASE 626
AWL
power demand diminishes, the IC automatically enters the skip cycle 8 YYWW
mode and provides excellent efficiency at light loads. Because this 1 1
occurs at low peak current, no acoustic noise takes place.
Finally, the IC is self–supplied from the DC rail, eliminating the xxx = Device Code: 40, 60 or 100
need of an auxiliary winding. This feature ensures operation in y = Device Code:
presence of low output voltage or shorts. 4 for 40
6 for 60
Features 1 for 100
• No Auxiliary Winding Operation A
L
= Assembly Location
= Wafer Lot
• Internal Output Short–Circuit Protection Y, YY = Year
• Extremely Low No–Load Standby Power W, WW = Work Week

• Current–Mode with Skip–Cycle Capability

• Internal Leading Edge Blanking PIN CONNECTIONS
• 110 mA Peak Current Source/Sink Capability
1 8
• Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz
Adj HV

• Direct Optocoupler Connection FB 2 7 NC

• Built–in Frequency Jittering for Lower EMI CS 3 6 VCC

• SPICE Models Available for TRANsient and AC Analysis Gnd 4 5 Drv

• Internal Temperature Shutdown
Typical Applications (Top View)

• AC/DC Adapters
• Offline Battery Chargers ORDERING INFORMATION
• Auxiliary/Ancillary Power Supplies (USB, Appliances, TVs, etc.) See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

May, 2001 – Rev. 6 NCP1200/D
 NCP1200

6.5 V @ 600 mA
C3 + +
D2 C2
10 F 1
Adj
HV 8
1N5819 470 F/10 V
400 V 2 FB NC 7
3 CS VCC 6 M1 Rf
4 Gnd Drv 5 MTD1N60E 470
EMI
Filter
+
C5 Rsense
10 F D8
Universal Input 5 V1

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Figure 1. Typical Application

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PIN FUNCTION DESCRIPTION

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Pin No.

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Pin Name

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Adj
Function
Adjust the skipping peak current
Description
This pin lets you adjust the level at which the cycle skipping process

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takes place

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2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand

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3

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CS

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Current sense input

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This pin senses the primary current and routes it to the internal
comparator via an L.E.B

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4

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5 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Gnd

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The IC ground

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Drv Driving pulses The driver’s output to an external MOSFET

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6

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7 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VCC

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Supplies the IC

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NC No Connection
This pin is connected to an external bulk capacitor of typically 10 µF
This un–connected pin ensures adequate creepage distance

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8

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HV

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Generates the VCC from the line

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Connected to the high–voltage rail, this pin injects a constant current into
the VCC bulk capacitor

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 NCP1200

1 8
Adj HV Current HV
Source

Skip Cycle
75.5 k 1.4 V Comparator
+
Internal UVLO
2 - 7
FB VCC High and Low NC
Internal Regulator
29 k

Q Flip–Flop
Current 3 250 ns 40, 60 or Set DCmax = 80% Q 6
100 kHz VCC
Sense L.E.B. Reset
Clock

+
8k 60 k
4 - 5
Ground Drv
+ Vref 1V
20 k ±110 mA
- 5.2 V
Overload?

Fault Duration

Figure 2. Internal Circuit Architecture

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MAXIMUM RATINGS

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Rating Symbol Value Units

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Power Supply Voltage VCC 16 V

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Thermal Resistance Junction–to–Air, PDIP8 version RJA 100 °C/W

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Thermal Resistance Junction–to–Air, SOIC version RJA 178
°C

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Maximum Junction Temperature TJmax 150
Typical Temperature Shutdown – 140

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Storage Temperature Range

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ESD Capability, HBM model (All pins except VCC and HV)
Tstg
–
–60 to +150
2.0
°C
kV

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ESD Capability, Machine model

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Maximum Voltage on pin 8 (HV), pin 6 (VCC) grounded
–
–
200
450
V
V

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Maximum Voltage on pin 8 (HV), pin 6 (VCC) decoupled to ground with 10 µF – 500 V

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 NCP1200

ELECTRICAL CHARACTERISTICS (For typical values TJ = +25°C, for min/max values TJ = –25°C to +125°C, Max TJ = 150°C,
VCC= 11 V unless otherwise noted)
Rating Pin Symbol Min Typ Max Unit
DYNAMIC SELF–SUPPLY (All frequency versions, otherwise noted)
VCC increasing level at which the current source turns–off 6 VCCOFF 10.3 11.4 12.5 V
VCC decreasing level at which the current source turns–on 6 VCCON 8.8 9.8 11 V
VCC decreasing level at which the latch–off phase ends 6 VCClatch – 6.3 – V
Internal IC Consumption, no output load on pin 6 6 ICC1 – 710 880 µA
Note 1
Internal IC Consumption, 1 nF output load on pin 6, FSW = 40 kHz 6 ICC2 – 1.2 1.4 mA
Note 2
Internal IC Consumption, 1 nF output load on pin 6, FSW = 60 kHz 6 ICC2 – 1.4 1.6 mA
Note 2
Internal IC Consumption, 1 nF output load on pin 6, FSW = 100 kHz 6 ICC2 – 1.9 2.2 mA
Note 2
Internal IC Consumption, latch–off phase 6 ICC3 – 350 – µA
INTERNAL CURRENT SOURCE
High–voltage current source, VCC = 10 V 8 IC1 2.8 4.0 – mA
High–voltage current source, VCC = 0 8 IC2 – 4.9 – mA
DRIVE OUTPUT
Output voltage rise–time @ CL = 1 nF, 10–90% of output signal 5 Tr – 67 – ns
Output voltage fall–time @ CL = 1 nF, 10–90% of output signal 5 Tf – 28 – ns
Source resistance (drive = 0, Vgate = VCCHMAX – 1 V) 5 ROH 27 40 61 
Sink resistance (drive = 11 V, Vgate = 1 V) 5 ROL 5 12 20 
CURRENT COMPARATOR (Pin 5 un–loaded)
Input Bias Current @ 1 V input level on pin 3 3 IIB – 0.02 – µA
Maximum internal current setpoint 3 ILimit 0.8 0.9 1.0 V
Default internal current setpoint for skip cycle operation 3 ILskip – 350 – mV
Propagation delay from current detection to gate OFF state 3 TDEL – 100 160 ns
Leading Edge Blanking Duration 3 TLEB – 230 – ns
INTERNAL OSCILLATOR (VCC = 11 V, pin 5 loaded by 1 k)
Oscillation frequency, 40 kHz version – fOSC 36 42 48 kHz
Oscillation frequency, 60 kHz version – fOSC 52 61 70 kHz
Oscillation frequency, 100 kHz version – fOSC 86 103 116 kHz
Built–in frequency jittering, FSW = 40 kHz – fjitter – 300 – Hz/V
Built–in frequency jittering, FSW = 60 kHz – fjitter – 450 – Hz/V
Built–in frequency jittering, FSW = 100 kHz – fjitter – 620 – Hz/V
Maximum duty–cycle – Dmax 74 80 87 %
FEEDBACK SECTION (Vcc = 11 V, pin 5 loaded by 1 k)
Internal pull–up resistor 2 Rup – 8.0 – k
Pin 3 to current setpoint division ratio – Iratio – 4.0 – –
SKIP CYCLE GENERATION
Default skip mode level 1 Vskip 1.1 1.4 1.6 V
Pin 1 internal output impedance 1 Zout – 25 – k
1. Max value @ TJ = –25°C.
2. Max value @ TJ = 25°C, please see characterization curves.

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 NCP1200

60 11.70
100 kHz
50 11.60

11.50 60 kHz
LEAKAGE (µA)

40

VCCOFF (V)
30 11.40
40 kHz
20 11.30

10 11.20

0 11.10
–25 0 25 50 75 100 125 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 3. HV Pin Leakage Current vs. Figure 4. VCC OFF vs. Temperature
Temperature

9.85 900
100 kHz
9.80
850
9.75 60 kHz
800
9.70
VCCON (V)

ICC1 (µA)

9.65 750
100 kHz
9.60 40 kHz
700
9.55
60 kHz
650
9.50
40 kHz
9.45 600
–25 0 25 50 75 100 125 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 5. VCC ON vs. Temperature Figure 6. ICC1 vs. Temperature

2.10 110
104
100 kHz
1.90 98 100 kHz
92
1.70 86
FSW (kHz)
ICC2 (mA)

80
1.50 74
60 kHz 68 60 kHz
1.30 62
40 kHz 56
1.10 50
40 kHz
44
0.90 38
–25 0 25 50 75 100 125 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 7. ICC2 vs. Temperature Figure 8. Switching Frequency vs. TJ

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 NCP1200

6.50 460
430
6.45
400
VCCLATCHOFF (V)

6.40 370

ICC3 (µA)
340
6.35
310
6.30 280
250
6.25
220
6.20 190
–25 0 25 50 75 100 125 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 9. VCC Latchoff vs. Temperature Figure 10. ICC3 vs. Temperature

60 1.00

50 Source CURRENT SETPOINT (V)

0.96

40
0.92
Ω

30
0.88
20 Sink
0.84
10

0 0.80
–25 0 25 50 75 100 125 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 11. DRV Source/Sink Resistances Figure 12. Current Sense Limit vs. Temperature

1.34 86.0

1.33 84.0
DUTY–MAX (%)

1.32 82.0
Vskip (V)

1.31 80.0

1.30 78.0

1.29 76.0

1.28 74.0
–25 0 25 50 75 100 125 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 13. Vskip vs. Temperature Figure 14. Max Duty–Cycle vs. Temperature

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 NCP1200

APPLICATIONS INFORMATION

INTRODUCTION Dynamic Self–Supply

The NCP1200 implements a standard current mode The DSS principle is based on the charge/discharge of the
architecture where the switch–off time is dictated by the VCC bulk capacitor from a low level up to a higher level. We
peak current setpoint. This component represents the ideal can easily describe the current source operation with a bunch
candidate where low part–count is the key parameter, of simple logical equations:
particularly in low–cost AC/DC adapters, auxiliary supplies POWER–ON: IF VCC < VCCOFF THEN Current Source
etc. Thanks to its high–performance High–Voltage is ON, no output pulses
technology, the NCP1200 incorporates all the necessary IF VCC decreasing > VCCON THEN Current Source is
components normally needed in UC384X based supplies: OFF, output is pulsing
timing components, feedback devices, low–pass filter and IF VCC increasing < VCCOFF THEN Current Source is
self–supply. This later point emphasizes the fact that ON ON, output is pulsing
Semiconductor’s NCP1200 does NOT need an auxiliary Typical values are: VCCOFF = 11.4 V, VCCON = 9.8 V
winding to operate: the product is naturally supplied from To better understand the operational principle, Figure 15’s
the high–voltage rail and delivers a VCC to the IC. This sketch offers the necessary light:
system is called the Dynamic Self–Supply (DSS).

VCCOFF = 11.4 V
10.6 V Avg. VCC
VCCON = 9.8 V

ON

OFF Current
Source

Output Pulses
10.00M 30.00M 50.00M 70.00M 90.00M
Figure 15. The Charge/Discharge Cycle
Over a 10
F VCC Capacitor

The DSS behavior actually depends on the internal IC . 0.16 = 256 mW. If for design reasons this contribution is
consumption and the MOSFET’s gate charge, Qg. If we still too high, several solutions exist to diminish it:
select a MOSFET like the MTD1N60E, Qg equals 11 nC 1. Use a MOSFET with lower gate charge Qg
(max). With a maximum switching frequency of 48 kHz (for 2. Connect pin through a diode (1N4007 typically) to
the P40 version), the average power necessary to drive the one of the mains input. The average value on pin 8
MOSFET (excluding the driver efficiency and neglecting 2*V
mains PEAK. Our power contribution
becomes 
various voltage drops) is:
example drops to: 160 mW.
Fsw  Qg  V cc with
Fsw = maximum switching frequency Dstart
Qg = MOSFET’s gate charge 1N4007
VCC = VGS level applied to the gate
To obtain the final driver contribution to the IC C3 + NCP1200
consumption, simply divide this result by VCC: Idriver = 4.7 F
Fsw  Qg = 530 µA. The total standby power consumption 400 V 1
Adj
HV 8
at no–load will therefore heavily rely on the internal IC 2 FB NC 7
consumption plus the above driving current (altered by the 3 CS VCC 6
driver’s efficiency). Suppose that the IC is supplied from a EMI 4 Gnd Drv 5
400 V DC line. To fully supply the integrated circuit, let’s Filter
imagine the 4 mA source is ON during 8 ms and OFF during Figure 16. A simple diode naturally reduces the
50 ms. The IC power contribution is therefore: 400 V . 4 mA average voltage on pin 8

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 NCP1200

3. Permanently force the VCC level above VCCH with When FB is above the skip cycle threshold (1.4 V by
an auxiliary winding. It will automatically default), the peak current cannot exceed 1 V/Rsense. When
disconnect the internal start–up source and the IC the IC enters the skip cycle mode, the peak current cannot go
will be fully self–supplied from this winding. below Vpin1 / 4 (Figure 19). The user still has the flexibility
Again, the total power drawn from the mains will to alter this 1.4 V by either shunting pin 1 to ground through
significantly decrease. Make sure the auxiliary a resistor or raising it through a resistor up to the desired
voltage never exceeds the 16 V limit. level.

Skipping Cycle Mode

The NCP1200 automatically skips switching cycles when
the output power demand drops below a given level. This is P1
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop P2
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so–called skip cycle mode, also P3
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18 ).
Suppose we have the following component values:
Lp, primary inductance = 1 mH Figure 18. Output pulses at various power levels
(X = 5
s/div) P1<P2<P3
FSW, switching frequency = 48 kHz
Ip skip = 300 mA (or 350 mV / Rsense)
Max Peak
The theoretical power transfer is therefore: Current
1  Lp  Ip 2  Fsw  2.2 W
2
If this IC enters skip cycle mode with a bunch length of
10 ms over a recurrent period of 100 ms, then the total power Skip Cycle
transfer is: 2.2 . 0.1 = 220 mW. Current Limit
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight:

FB

4.8 V
3.8 V
Figure 19. The skip cycle takes place at low peak
Normal Current Mode Operation
currents which guarantees noise free operation

1.4 V
Skip Cycle Operation
Ipmin = 350 mV / Rsense

Figure 17. Feedback Voltage Variations

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 NCP1200

Power Dissipation Overload Operation

The NCP1200 is directly supplied from the DC rail In applications where the output current is purposely not
through the internal DSS circuitry. The current flowing controlled (e.g. wall adapters delivering raw DC level), it is
through the DSS is therefore the direct image of the interesting to implement a true short–circuit protection. A
NCP1200 current consumption. The total power dissipation short–circuit actually forces the output voltage to be at a low
can be evaluated using: (V HVDC  11 V)  ICC2. If we level, preventing a bias current to circulate in the
operate the device on a 250 VAC rail, the maximum rectified optocoupler LED. As a result, the FB pin level is pulled up
voltage can go up to 350 VDC. As a result, the worse case to 4.1 V, as internally imposed by the IC. The peak current
dissipation occurs on the 100 kHz version which will setpoint goes to the maximum and the supply delivers a
dissipate 340 . 1.8 mA@Tj = –25°C = 612 mW (however rather high power with all the associated effects. Please note
this 1.8 mA number will drop at higher operating that this can also happen in case of feedback loss, e.g. a
temperatures). A DIP8 package offers a broken optocoupler. To account for this situation, the
junction–to–ambient thermal resistance of RJ–A 100°C/W. NCP1200 hosts a dedicated overload detection circuitry.
The maximum power dissipation can thus be computed Once activated, this circuitry imposes to deliver pulses in a
knowing the maximum operating ambient temperature (e.g. burst manner with a low duty–cycle. The system recovers
70°C) together with the maximum allowable junction when the fault condition disappears.
T Jmax  T Amax During the start–up phase, the peak current is pushed to
temperature (125°C): Pmax  = 550 mW. the maximum until the output voltage reaches its target and
R RJA
As we can see, we do not reach the worse consumption the feedback loop takes over. This period of time depends on
budget imposed by the 100 kHz version. Two solutions exist normal output load conditions and the maximum peak
to cure this trouble. The first one consists in adding some current allowed by the system. The time–out used by this IC
copper area around the NCP1200 DIP8 footprint. By adding works with the VCC decoupling capacitor: as soon as the
a min–pad area of 80 mm2 of 35  copper (1 oz.) RJ–A drops VCC decreases from the VCCOFF level (typically 11.4 V) the
to about 75°C/W which allows the use of the 100 kHz device internally watches for an overload current situation.
version. The other solutions are: If this condition is still present when VCCON is reached, the
1. Add a series diode with pin 8 (as suggested in the controller stops the driving pulses, prevents the self–supply
above lines) to drop the maximum input voltage current source to restart and puts all the circuitry in standby,
down to 222 V ((2
350)/pi) and thus dissipate consuming as little as 350 µA typical (ICC3 parameter). As
less than 400 mW a result, the VCC level slowly discharges toward 0. When
2. Implement a self–supply through an auxiliary this level crosses 6.3 V typical, the controller enters a new
winding to permanently disconnect the self–supply. startup phase by turning the current source on: VCC rises
SO–8 package offers a worse RJ–A compared to that of toward 11.4 V and again delivers output pulses at the
the DIP8 package: 178°C/W. Again, adding some copper UVLOH crossing point. If the fault condition has been
area around the PCB footprint will help decrease this removed before UVLOL approaches, then the IC continues
number: 12 mm x 12 mm to drop RJ–A down to 100°C/W its normal operation. Otherwise, a new fault cycle takes
with 35  copper thickness (1 oz.) or 6.5 mm x 6.5 mm with place. Figure 20 shows the evolution of the signals in
70  copper thickness (2 oz.). As one can see, we do not presence of a fault.
recommend using the SO–8 package for the 100 kHz version
with DSS active as the IC may not be able to sustain the
power (except if you have the adequate place on your PCB).
However, using the solution of the series diode or the
self–supply through the auxiliary winding does not cause
any problem with this frequency version. These options are
thoroughly described in the AND8023/D.

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9
 NCP1200

VCC
Regulation
Occurs Here
11.4 V
Latch–off
9.8 V Phase
6.3 V

Time

Drv

Driver Driver
Pulses Pulses
Time
Internal
Fault
Flag

Fault is
Relaxed
Time
Startup Phase Fault Occurs Here
Figure 20. If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes.
If the fault persists when VCC reached UVLOL, then the controller cuts everything off until recovery.

Calculating the VCC Capacitor C equals 8 µF or 10 µF for a standard value. When an

As the above section describes, the fall down sequence overload condition occurs, the IC blocks its internal
depends upon the VCC level: how long does it take for the circuitry and its consumption drops to 350 µA typical. This
VCC line to go from 11.4 V to 9.8 V? The required time appends at VCC = 9.8 V and it remains stuck until VCC
depends on the start–up sequence of your system, i.e. when reaches 6.5 V: we are in latch–off phase. Again, using the
you first apply the power to the IC. The corresponding calculated 10 µF and 350 µA current consumption, this
transient fault duration due to the output capacitor charging latch–off phase lasts: 109 ms.
must be less than the time needed to discharge from 11.4 V
to 9.8 V, otherwise the supply will not properly start. The test A Typical Application
consists in either simulating or measuring in the lab how Figure 21 depicts a low–cost 3.5 W AC/DC 6.5 V wall
much time the system takes to reach the regulation at full adapter. This is a typical application where the wall–pack
load. Let’s suppose that this time corresponds to 6ms. must deliver a raw DC level to a given internally regulated
Therefore a VCC fall time of 10 ms could be well apparatus: toys, calculators, CD–players etc. Thanks to the
appropriated in order to not trigger the overload detection inherent short–circuit protection of the NCP1200, you only
circuitry. If the corresponding IC consumption, including need a bunch of components around the IC, keeping the final
the MOSFET drive, establishes at 1.5 mA, we can calculate cost at an extremely low level. The transformer is available
the required capacitor using the following formula: from different suppliers as detailed on the following page.

t 
V  C, with
V = 2V. Then for a wanted
t of 10 ms,
i

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10
 NCP1200

R7
Clamping
L5 Network L4
330 H
2.2 H
Rclamp 6.5 V @ 600 mA
D3 + +
C5 C10
C3 + C2 1N5819
+ 470 F/ 4.7 F/
4.7 F 4.7 F Clamp T1 10 V 10 V
400 V 400 V NCP1200
Dclamp
1 HV 8 Snubber
Adj
2 FB NC 7 Optional
Networks
3 CS VCC 6 RSnubber R2
220
4 Gnd Drv 5
M1 CSnubber
Universal MTD1N60E
Input
+
L6 C9 R6
R9 330 H 10 F 2.8 D6
10 IC1 5 V1
SFH615A–2

Figure 21. A typical AC/DC wall adapter showing the reduced part count thanks to the NCP1200

T1: Lp = 2.9 mH, Np:Ns = 1:0.08, leakage = 80 µH, E16 core, NCP1200P40
To help designers during the design stage, several manufacturers propose ready–to–use transformers for the above
application, but can also develop devices based on your particular specification:
Eldor Corporation Headquarter Atelier Special de Bobinage
Via Plinio 10, 125 cours Jean Jaures
22030 Orsenigo 38130 ECHIROLLES FRANCE
(Como) Italia Tel.: 33 (0)4 76 23 02 24
Tel.: +39–031–636 111 Fax: 33 (0)4 76 22 64 89
Fax : +39–031–636 280 Email: asb@wanadoo.fr
Email: eldor@eldor.it ref. 1: NCP1200–10 W–UM: 10 W for USB
www.eldor.it (Lp = 1.8 mH, 60 kHz, 1:0.1, RM8 pot core)
ref. 1: 2262.0058C: 3.5 W version Coilcraft
(Lp = 2.9 mH, Lleak = 80 µH, E16) 1102 Silver Lake Road
ref. 2: 2262.0059A: 5 W version Cary, Illinois 60013 USA
(Lp = 1.6 mH, Lleak = 45 µH, E16) Tel: (847) 639–6400
EGSTON GesmbH Fax: (847) 639–1469
Grafenbergerstraβe 37 Email: info@coilcraft.com
3730 Eggenburg http://www.coilcraft.com
Austria ref. 1: Y8844–A: 3.5 W version
Tel.: +43 (2984) 2226–0 (Lp = 2.9 mH, Lleak = 65 µH, E16)
Fax : +43 (2984) 2226–61 ref. 2: Y8848–A: 10 W version
Email: info@egston.com (Lp = 1.8 mH, Lleak = 45 µH, 1:01, E core)
http://www.egston.com/english/index.htm
ref. 1: F0095001: 3.5 W version
(Lp = 2.7 mH, Lleak = 30 µΗ, sandwich configuration, E16)

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11
 NCP1200

Improving the Output Drive Capability

1 8
The NCP1200 features an asymmetrical output stage used
to soften the EMI signature. Figure 22 depicts the way the 2 7
2N2222
driver is internally made: 3 NCP1200 6 Rd
4 5 To Gate
VCC
2N2907

Q
2 7

40
Figure 23. Improving Both Turn–On and
1
Turn–Off Times

12 1 8

5 2 7
NCP1200
Q\ 3 6 1N4148
3
4 5 To Gate

2N2907
Figure 22. The higher ON resistor slows down
the MOSFET while the lower OFF resistor
ensures fast turn–off.
In some cases, it is possible to expand the output drive
capability by adding either one or two bipolar transistors. Figure 24. Improving Turn–Off Time Only
Figures 23, 24, and 25 give solutions whether you need to
improve the turn–on time only, the turn–off time or both. Rd
is there to damp any overshoot resulting from long copper
1 8
traces. It can be omitted with short connections. Results
showed a rise fall time improvement by 5X with standard 2 7
NCP1200 2N2222
2N2222/2N2907: 3 6
4 5 To Gate
1N4148

Figure 25. Improving Turn–On Time Only

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12
 NCP1200

If the leakage inductance is kept low, the MTD1N60E can Vripple: the clamping ripple, could be around 20 V
withstand accidental avalanche energy, e.g. during a Another option lies in implementing a snubber network
high–voltage spike superimposed over the mains, without which will damp the leakage oscillations but also provide
the help of a clamping network. If this leakage path more capacitance at the MOSFET’s turn–off. The peak
permanently forces a drain–source voltage above the voltage at which the leakage forces the drain is calculated
MOSFET BVdss (600 V), a clamping network is mandatory
and must be built around Rclamp and Clamp. Dclamp shall
react extremely fast and can be a MUR160 type. To calculate
by: V
max  Ip   C
L
leak where Clump represents the
lump
the component values, the following formulas will help you: total parasitic capacitance seen at the MOSFET opening.
Rclamp = Typical values for Rsnubber and Csnubber in this 4W
2 V  (V  (V
out  Vf sec)  N)
application could respectively be 1.5 k and 47 pF. Further
clamp clamp
tweaking is nevertheless necessary to tune the dissipated
L  Ip 2  Fsw
leak power versus standby power.
V
clamp Available Documents
C 
clamp V  Fsw  R
ripple clamp “Implementing the NCP1200 in Low–cost AC/DC
with: Converters”, AND8023/D
Vclamp: the desired clamping level, must be selected to be “Conducted EMI Filter Design for the NCP1200’’,
between 40 to 80 volts above the reflected output voltage AND8032/D
when the supply is heavily loaded. “Ramp Compensation for the NCP1200’’, AND8029/D
Vout + Vf: the regulated output voltage level + the secondary TRANSient and AC models available to download at:
diode voltage drop http://onsemi.com/pub/NCP1200
Lleak: the primary leakage inductance NCP1200 design spreadsheet available to download at:
N: the Ns:Np conversion ratio http://onsemi.com/pub/NCP1200
FSW: the switching frequency

ORDERING INFORMATION
Device Type Marking Package Shipping
NCP1200P40 FSW = 40 kHz 1200P40 PDIP8 50 Units / Rail
NCP1200D40R2 FSW = 40 kHz 200D4 SO–8 2500 Units /Reel
NCP1200P60 FSW = 60 kHz 1200P60 PDIP8 50 Units / Rail
NCP1200D60R2 FSW = 60 kHz 200D6 SO–8 2500 Units /Reel
NCP1200P100 FSW = 100 kHz 1200P100 PDIP8 50 Units / Rail
NCP1200D100R2 FSW = 100 kHz 200D1 SO–8 2500 Units / Reel

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13
 NCP1200

PACKAGE DIMENSIONS

DIP8
P SUFFIX
CASE 626–05
ISSUE L

8 5 NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
–B– FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
1 4
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

F MILLIMETERS INCHES
DIM MIN MAX MIN MAX
NOTE 2 –A– A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
L C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
C H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
J K 2.92 3.43 0.115 0.135
–T– L 7.62 BSC 0.300 BSC
SEATING N M --- 10
--- 10

PLANE N 0.76 1.01 0.030 0.040
M
D K
H G
0.13 (0.005) M T A M B M

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14
 NCP1200

PACKAGE DIMENSIONS

(SO–8)
D SUFFIX
CASE 751–07
ISSUE W

–X–
NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
8 5 3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
B S 0.25 (0.010) M Y M SIDE.
1 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
4
K PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
–Y– EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
–Z– D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0
8
0
8

N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244

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15
AND8023/D

Implementing the NCP1200

in Low-Cost AC/DC
Converters
Prepared by: Christophe Basso
ON Semiconductor http://onsemi.com

APPLICATION NOTE

INTRODUCTION  External MOSFET connection: by leaving the external

The NCP1200 implements a standard current mode MOSFET external to the IC, you can select avalanche
architecture where the switch–off time is dictated by the proof devices which, in certain cases (e.g. low output
peak current setpoint. This component represents the powers), let you work without an active clamping
ideal candidate where low part–count is the key network. Also, by controlling the MOSFET gate signal
parameter, particularly in low–cost AC/DC adapters, flow, you have an option to slow down the device
auxiliary supplies etc. Thanks to its proprietary Very commutation, therefore reducing the amount of
High–Voltage Integrated Circuit (VHVIC) technology, ElectroMagnetic Interference (EMI).
ON Semiconductor NCP1200 will please experts as well  SPICE model: a dedicated model to run transient
as non–experts in the Switch–Mode Power Supplies cycle–by–cycle simulations is available but also an
(SMPS) arena as the following features demonstrate: averaged version to help you closing the loop.
 No need of auxiliary winding: the VHVIC technology Ready–to–use templates can be downloaded in OrCAD’s
lets you supply the IC directly from the high–voltage DC PSpice, INTUSOFT’s IsSpice and Spectrum–Software’s
rail. We call it Dynamic Self–Supply (DSS). In battery µCap from the ON Semiconductor web site,
charger applications, you no longer need to design a www.onsemi.com, NCP1200 related section.
special primary circuitry to cope with the transient lack of  Low external part–count: by integrating the principal
auxiliary voltage (e.g. when Vout is low). electronic blocks in one die, the final NCP1200
 Short–circuit protection: by permanently monitoring implementation reveals an obvious gain in component
the feedback line activity, the IC is able to detect the reduction compared to other offers:
presence of a short–circuit, immediately reducing the – Built–in clock generator without external R–C
output power for a total system protection. Once the short elements. Operating frequencies at 40 kHz, 60 kHz or
has disappeared, the controller resumes and goes back to 100 kHz.
normal operation. For given applications (e.g. constant – The optocoupler is directly wired to the feedback pin,
output power supplies), you can easily disconnect this the internal IC control taking care of the signal flow.
protective feature. – The 250 ns Leading Edge Blanking (LEB) circuitry
 Low standby–power: if SMPS naturally exhibit a good also saves an external R–C network.
efficiency at nominal load, they begin to be less efficient
when the output power demand diminishes. By skipping Dynamic Self–Supply
un–needed switching cycles, the NCP1200 drastically To avoid the use of a dissipative resistor, NCP1200
reduces the power wasted during light load conditions. In implements a controlled current source whose technology
no–load conditions, the NPC1200 allows the total allows a direct connection to the high–voltage rail (up to
standby power to easily reach next International Energy 450 VDC). Figure 1a depicts the component arrangement.
Agency (IEA) recommendations.
The current source always operates in the ON or OFF
 No acoustic noise while operating: instead of skipping
states, either delivering 4 mA or zero. As a result, the
cycles at high peak currents, the NCP1200 waits until the
internal VCC pin ramps up and down with a 2 V ripple
peak current demand falls below a user–adjustable 1/3rd
centered around 10.6 V (Figure 1b).
of the maximum limit. As a result, cycle skipping can take
place without having a singing transformer … You can
thus select cheap magnetic components free of noise
problems.

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

April, 2001 – Rev. 3 AND8023/D
 AND8023/D

Pin 8

VCCOFF = 11.4 V
2
10.6 V VCC
+
4 ON/OFF Avg.
VCCON = 9.8 V
- 3

Pin 6 ON
+
10 V/12 V C
OFF Current
Source

Output Pulses
10.00M 30.00M 50.00M 70.00M 90.00M

Figure 1a. Internal Implementation Figure 1b. DSS Waveforms During Start–Up
of the Dynamic Self–Supply and Normal Mode (CVCC = 10 F)

As one can see from Figure 1a, the current source current necessary to drive the MOSFET (excluding the driver
supplies the IC and the Vcc capacitor. Thanks to the efficiency and neglecting various voltage drops) is:
circuitry nature, the current source duty–cycle will Fsw  Qg  530 A
automatically adjust depending on the IC average current
Fsw = maximum switching frequency (Hertz)
consumption. Because this is a controlled source, this
Qg = MOSFET’s gate charge (Coulomb)
current stays constant whatever the high–voltage rail
excursion (VHV): from 100 VDC up to 370 VDC. The IC If we now add this number to the normal IC consumption,
contribution to the total SMPS power budget is therefore: we reach a typical total of 1.2 mA. The total IC power
VHV . Ipin8. contribution alone is therefore: 330 V . 1.2 mA = 396 mW.
The internal IC consumption is made of the internal Decreasing the Standby Power
electronic blocks (clock, comparators, driver etc.) but also Below stands the future stand–by power recommendations
depends on the MOSFET’s gate charge, Qg. If we select a issued by International Energy Agency (IEA). It concerns
MOSFET like the MTD1N60E, Qg equals 11 nC (max) and stand–by power when there is no output power demand:
with a maximum switching frequency of 48 kHz, the average

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
Rated Input Power

ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
0.3 W and 15 W
ÁÁÁÁÁÁÁÁÁ
Phase 1, January 2001
1.0 W
Phase 2, January 2003
0.75 W
Phase 3, January 2005
0.30 W

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
15 W and 50 W

ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
50 W and 75 W
ÁÁÁÁÁÁÁÁÁ
1.0 W
1.0 W
0.75 W
0.75 W
0.50 W
0.75 W

A typical 4 W universal mains AC/DC wall adapter using through pin 8 (actually the total NCP1200
the NCP1200 will exhibit a no–load power consumption of consumption + a few losses) and integrate over a
less than 380 mW @ Vin = 230 VAC. If a lower power half–sine only. This leads to the final formula:
consumption is required, you have several options to 2 * Vmainspeak * lavg (Pin 8)
Pavg   . Our previous
achieve it:
number drops to 250 mW. If you carefully look at
1. Use a MOSFET with lower gate charge Qg, but as we
Figure 2a, you will notice that the reverse voltage is
saw the driver’s contribution is small.
sustained by the diode bridge. The maximum anode
2. Connect pin 8 through a diode to one of the mains input
voltage of the Dstart diode is also clamped at the
to apply a rectified half–wave on pin 8. Since we have
high–voltage rail. Therefore, a standard fast diode like
either 4.0 mA or 0 synchronized with this half–sine
the 1N4148 can safely be used in this option. However,
wave, we should integrate the V–I product over a cycle
because of the lack of synchronization between the DSS
to obtain the final average power. However,
and the mains, it is necessary to equilibrate the diode
depending on the VCC capacitor, we may have some
voltage when both diode and DSS are inactive. This can
half–sine portions where the current source if OFF:
be done by wiring a 220 kΩ in parallel with the diode.
the VCC capacitor level has not reached UVLOLow and
Otherwise, a standard 1N4937 can also do the job
the current source is left opened. To simplify the
without any resistor in parallel…
curves, we can assume a constant current flowing

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2
 AND8023/D

220 k

Aux

1N4148 D4 D5
15 V 1N4148
C3 + NCP1200 400 mW
4.7 F
350 V 1 HV 8 NCP1200
Adj
2 FB NC 7
1 Adj HV 8
3 CS VCC 6 2 FB 7
4 Gnd Drv 5 3 CS VCC 6 M2
4 Gnd Drv 5 MTD1N60E
R3
1K

Figure 2a. A simple diode naturally reduces the

+ 10 µF
average voltage on pin 8.
C6

Figure 2b depicts the VCC voltage obtained when using this Figure 3. By wiring an auxiliary winding, you further
method. Despite the lack of synchronization between the decrease the standby power.
mains and the DSS, the average VCC level is not affected.
The typical operating voltage can be set at 12 V, with an
overvoltage protection at 15 V. As a benefit, if the
optocoupler fails, the SMPS turns into primary regulation
mode and prevents any output voltage runaway. Typical
measurements using this method gave a standby power of
84 mW at 230 VAC.
VCC
2 V/div Skip Cycle Mode
The NCP1200 automatically skips switching cycles
when the output power demand drops below a given level.
Vpin8 This is accomplished by monitoring the FB pin (pin 2). In
50 V/div normal operation, pin 2 imposes a peak current accordingly
to the load value. If the load demand decreases, the internal
loop asks for less peak current. When this setpoint reaches
a determined level, the IC prevents the current from
Figure 2b. By wiring a diode in series with pin 8, you decreasing further down and starts to blank the output
do not affect the average VCC level. pulses: the IC enters the so–called skip cycle mode, also
named controlled burst operation. Because this operation
3. If you permanently force the VCC level above VCCOFF takes place at low peak currents, you will not hear any
with an auxiliary winding, you will automatically acoustic noise in your transformer. Figure 4a depicts how
disconnect the internal start–up source and the IC will be the IC implements the cycle skipping while Figure 4b
fully self–supplied from this winding. Again, the total shows typical switching patterns at different load levels.
power drawn from the mains will significantly decrease.
However, make sure the auxiliary voltage never exceeds
the 16 V limit, particularly in overshoot transients (e.g.
the load is suddenly removed). To avoid this trouble and
also implement an efficient Over Voltage Protection
(OVP), Figure 3 schematic offers a possible solution:

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 AND8023/D

Clock
Max Peak
S Current
G To Driver
Q
R
Skip Cycle
Current Limit
1/4
GAIN
FB +
LEB -
CS

+
1.4 V -
Adj

+ Figure 4c. The skip cycle takes place at low peak

currents which guarantees noise–free operation.
Figure 4a. NCP1200 Skip Cycle Implementation
The power transfer now depends upon the width of the
pulse bunches (Figure 4b). Suppose we have the following
component values:
Lp, primary inductance = 1 mH
P3 Fsw , switching frequency = 48 kHz
Ip skip = 300 mA (or 350 mV/Rsense)
P2 The theoretical (η = 100%) power transfer is therefore:
1  Lp  Ip 2  Fsw  2.16 W (eq. 2)
2
If this IC enters skip cycle mode with a bunch length of
10 ms over a recurrent period of 100 ms, then the total
power transfer is: 2.1 . 0.1 = 216 mW.
P1 Skip Adjustment
By altering the DC voltage present on pin 1, you have the
Figure 4b. Output pulses at various power levels ability to adjust the current level at which skip cycle
(X = 5 s/div) P3 < P2 < P1 operation will take place. By default, skip cycle occurs
when the peak current demand falls below one third of the
When FB is above the skip cycle threshold (1.4 V by maximum peak current. If your design needs to enter
default), the peak current cannot exceed 1 V/Rsense. When standby at a higher or lower current (e.g. for noise reasons),
the IC enters the skip cycle mode, the peak current cannot you can alter the internal setpoint by imposing a different
go below Vpin1/4, 350 mV/Rsense by default (Figure 4c). level than 1.4 V on pin 1. This can be achieved by using a
The user still has the flexibility to alter this 1.4 V by either resistor bridge between VCC and ground. Pin 1 impedance
shunting pin 1 to ground through a resistor or raising it is typically 25 kΩ.
through a resistor up to the desired level.

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 AND8023/D

Overload Operation on normal output load conditions and the maximum peak
current allowed by the system. The time–out used by this
In applications where the output current is purposely not
IC works with the VCC decoupling capacitor: as soon as the
controlled (e.g. wall adapters delivering raw DC level), it is
VCC decreases from the VCCOFF (typically 11.4 V) the
mandatory to implement a true short–circuit protection. A
device internally watches for an overload current situation.
short–circuit actually forces the output voltage to be at a
If this condition is still present when the VCCON is reached,
low level, preventing a bias current to circulate in the
the controller stops the driving pulses, prevents the
optocoupler LED. As a result, the FB pin level is pulled up
self–supply current source to restart and puts all the
to 4.8V, as internally imposed by the IC. The peak current
circuitry in standby, consuming as little as 350 µA typical
setpoint goes to the maximum and the supply delivers a
(ICC3 parameter). As a result, the VCC level slowly
rather high power with all the associated effects. Please
discharges toward 0. When this level crosses 6.3 V typical,
note that this can also happen in case of feedback loss, e.g.
the controller enters a new startup phase by turning the
a broken optocoupler. To account for this situation, the
current source on: VCC rises toward 11.4 V and again
NCP1200 hosts a dedicated overload detection scheme.
delivers output pulses at the VCCOFF crossing point. If the
Once activated, this circuitry imposes to deliver pulses in a
fault condition has been removed before V CCON
burst manner with a low duty–cycle. The system recovers
approaches, then the IC continues its normal operation.
when the fault condition disappears.
Otherwise, a new fault cycle takes place. Figure 5 shows
During the start–up phase, the peak current is pushed to
the evolution of the signals in presence of a fault.
the maximum until the output voltage reaches its target and
the feedback loop takes over. This period of time depends

VCC
Regulation
Occurs Here
11.4 V
Latch–off
9.8 V Phase
6.3V

Time

Drv

Driver Driver
Pulses Pulses
Time
Internal
Fault
Flag

Fault is
Relaxed
Time
Startup Phase Fault Occurs Here

Figure 5. If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes. If the
fault still persists when VCC reached UVLOL, then the controller enters burst mode until recovery.

∗ Always make sure that the output power you are looking the overload protection activates at roughly twice this value,
for asks for an FB level less than the maximum value to especially if you implement a low–gain single zener
avoid a false overload circuitry trigger. feedback loop. You need to be sure that the output
∗ Because of component dispersions (NCP1200 frequency components sustain the corresponding current. Fortunately,
span, Rsense tolerance etc.), the overload protection will not because of temperature, the transformer core permeability
be active as soon as you exceed the nominal power by a will decrease as well as the primary inductance. This means
small amount. If you shoot for a given Pout, it is likely that less maximum power at higher temperatures.

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5
 AND8023/D

Deactivating the Overload Detection the power (except if you have the adequate place on your
By wiring a 20 kΩ resistor from FB to ground, you PCB). However, using the solution of the series diode or the
permanently deactivate the overload protection circuitry. self–supply through the auxiliary winding does not cause
This is a very useful feature, especially if you need to build any problem with this frequency version.
a constant output power converter.
Calculating the VCC Capacitor for Overload
Power Dissipation As the above section describes, the fall down sequence
depends upon the VCC level: how long does it take for the
The NCP1200 is directly supplied from the DC rail VCC line to go from 11.4 V to 9.8 V? The required time
through the internal DSS circuitry. The current flowing depends on the start–up sequence of your system, i.e. when
through the DSS is therefore the direct image of the you first apply the power to the IC. The corresponding
NCP1200 current consumption. The total power dissipation transient fault duration due to the output capacitor charging
can be evaluated using: (VHVDC  11 V)
ICC2. If we must be less than the time needed to discharge from 11.4 V
operate the device on a 250 VAC rail, the maximum rectified to 10 V, otherwise the supply will not properly start. The
voltage can go up to 350 VDC. As a result, the worse case test consists in either simulating or measuring in the lab
dissipation occurs on the 100 kHz version which will dissipate how much time the system takes to reach the regulation at
340 . 1.8 mA @ Tj = 25°C = 612 mW (however this 1.8 mA full load. Let’s suppose that this time corresponds to 6ms.
number will drop at higher operating temperatures). A DIP8 Therefore a VCC fall time of 10 ms could be well
package offers a junction–to–ambient thermal resistance appropriated in order to not trigger the overload detection
RθJ–A of 100°C/W. The maximum power dissipation can circuitry. If the corresponding IC consumption, including
thus be computed knowing the maximum operating the MOSFET drive, establishes at 1.5 mA, we can calculate
ambient temperature (e.g. 70°C) together with the the required capacitor using the following formula:
maximum allowable junction temperature (125°C):
Tj max  TA max
t 
V  C, with ∆V = 2 V (eq. 3). Then for a wanted ∆t
P max   550 mW. As we can see, we do i
R J  A of 10 ms, C equals 8 µF or 10 µF for a standard value.
not reach the worse consumption budget imposed by the When an overload condition occurs, the IC blocks its
100 kHz version. Two solutions exist to cure this trouble. internal circuitry and its consumption drops to 350 µA
The first one consists in adding some copper area around typical. This happens at VCC = 10 V and it remains stuck
the NCP1200 DIP8 footprint. By adding a min–pad area of until VCC reaches 6.3 V: we are in latch–off phase. Again,
80mm
of 35µ copper (1 oz.), RθJ–A drops to about using the calculated 9.8 µF and 350 µA current
75°C/W which allows the use of the 100 kHz version. The consumption, this latch–off phase lasts: 109 ms.
other solutions are a) add a series diode with pin 8 (as
Protecting the Power MOSFET
suggested in the above lines) to drop the maximum input
voltage down to 225 V (707/π) and thus dissipates less than If the leakage inductance is kept low, an avalanche
410 mW b) implement a self–supply through an auxiliary rugged MOSFET such as the MTD1N60E can withstand
winding to permanently disconnect the self–supply. accidental avalanche energy, e.g. during a high–voltage
SO–8 package offers a worse RθJ–A compared to that of spike superimposed over the mains, without the help of a
the DIP8 package: 178°C/W. Again, adding some copper clamping network. However, if this leakage path
area around the PCB footprint will help decreasing this permanently forces a drain–source voltage above the
number: 12mm x 12mm to drop RθJ–A down to 100°C/W MOSFET BVdss (e.g. 600 V), a clamping network is
with 35µ copper thickness (1 oz.) or 6.5mm x 6.5mm with mandatory and must be built around a passive RC network
70µ copper thickness (2 oz.). As one can see, we do not or a Transient Voltage Suppressor (TVS). Figure 6a depicts
recommend using the SO–8 package for the 100 kHz the phenomenon while the below lines details the
version with DSS active as the IC may not be able to sustain calculation steps:

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6
 AND8023/D

RC network or TVS
BV dss HV rail HV rail

You need

1
4

3 5

TVS

Ultra–fast

Figure 6a. Care must be taken to ensure a safe operation of the MOSFET

1. RC Network 2. Transient Voltage Suppressor

The RC network will permanently impose a fixed Despite the low–cost offered by the above RC solution,
clamping level that will oppose to the leakage voltage. the clamping level unfortunately varies with the peak
As a result, the drain will be clamp to VHVrail + current. If you need a very precise clamping level, you
Vclamp. You normally select a clamping level between must implement a zener diode or a TVS. There are little
40 to 80 volts above the reflected output voltage when technology differences behind a standard zener diode
the supply is heavily loaded. and a TVS. However, the die area is far bigger for a
To calculate the component values, the following transient suppressor than that of zener. A 5 W zener
formula will help you: diode like the 1N5388B will accept 180 W peak power
if it lasts less than 8.3 ms. If the peak current in the
2  Vclamp  (Vclamp  (Vout  Vf sec)  N)
Rclamp  worse case (e.g. when the PWM circuit maximum
Lleak  Ip 2  F SW
current limit works) multiplied by the nominal zener
(eq. 4) voltage exceeds these 180 W, then the diode will be
Vclamp destroyed when the supply experiences overloads. A
Cclamp  transient suppressor like the P6KE200 still dissipates
Vripple  F SW  Rclamp
5 W of continuous power but is able to accept surges up
(eq. 5)
to 600 W @ 1 ms. If the peak power is really high, then
The power dissipated by Rclamp can also be expressed turn to a 1.5 KE200 which accepts up to 1.5 kW @
by: 1 ms.
Vclamp Select the zener or TVS clamping level between 40 to
(Vout  Vf sec)  N 80 volts above the reflected output voltage when the
P Rclamp  1  Lleak  Ip 2  F SW  supply is heavily loaded.
2 Vclamp
1
(Vout  Vf sec)  N 3. Snubber Network
with: Another option lies in implementing a snubber network
Vclamp: the desired clamping level. which will damp the leakage oscillations but also
Ip: the maximum peak current (e.g. during overload) provide more capacitance at the MOSFET’s turn–off.
Vout + Vf: the regulated output voltage level + the The peak voltage at which the leakage forces the drain
secondary diode voltage drop
Lleak: the primary leakage inductance
is calculated by: V max  Ip  Clump
Lleak (eq. 6) where

Clump represents the total parasitic capacitance seen at

N: the Ns:Np conversion ratio
the MOSFET opening. Depending on the output power,
Fsw: the switching frequency you can either wire a simple capacitor across the
Vripple: the clamping ripple, could be around 20 V MOSFET or an R–C network, as shown by Figure 6b.

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7
 AND8023/D

To lower the dissipated heat, you can wire a capacitor C

Csnubb Csnubb
in series with R: C  1 (eq. 8). If the output
  F ring  R
power is low, you can directly wire this capacitor
Rsnubb
between the MOSFET drain and ground (not between
drain–source to avoid substrate injection). Unfortunately,
RS RS
you discharge this capacitor in the MOSFET every time it
turns on... Further tweaking is thus necessary to tune the
dissipated power versus standby power.
Figure 6b. If the output power is low, you can wire a ON Semiconductor Protection Devices
simple capacitor MOSFET’s drain and ground. SMPS protection clearly needs fast switching components
to ensure a reliable operation in the event of dangerous
To calculate the values of this RC snubber, you need to transients. ON Semiconductor portfolio offers a
measure the ringing frequency imposed by the leakage comprehensive list of semiconductors dedicated to
inductance and all the stray capacitances. Make sure you protection: fast diodes, zeners, TVS etc. Below is a small list
use a low capacitance probe, otherwise you might affect of typical component you can select to protect the MOSFET
the observed frequency. Once you have it, calculate the in your application. The complete list of TVS devices can be
impedance of the leakage inductance at the ringing found at the following URL: www.onsemi.com or by
frequency: Z  2    F ring  L leak (eq. 7). Wiring a ordering the selection guide TVSPROMO1299/D by
resistor R whose value equals Z should solve the sending an email to: ONlit@hibbertco.com:
problem but at the expense of a large power dissipation.

Clipping Elements

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Reference Nominal Voltage (V) Average Power (W) Maximum Peak Power

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1N5953B 150 1.5 98 W @ 1 ms

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1N5955B 180 1.5 98 W @ 1 ms

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1N5383B 150 5.0 180 W @ 8.3 ms

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1N5386B 180 5.0 180 W @ 8.3 ms

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1N5388B 200 5.0 180 W @ 8.3 ms

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P6KE150A 150 5.0 600 W @ 1 ms

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P6KE180A 180 5.0 600 W @ 1 ms

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P6KE200A 200 5.0 600 W @ 1 ms

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1.5KE150A 150 5.0 1.5 kW @ 1 ms

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1.5KE180A 180 5.0 1.5 kW @ 1 ms

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1.5KE200A 200 5.0 1.5 kW @ 1 ms

Fast Diodes

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Reference VRRM Ton (typical) IF max

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MUR160 600 V 50 ns 3A

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MUR1100E 1000 V 25 ns 3A

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1N4937 600 V 200 ns 1A

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MSR860* 600 V 100 ns 8A

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MSRB860–1* 600 V 100 ns 8A
*Soft recovery diodes

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8
 AND8023/D

Calculating the Component Values for a Typical To simplify the calculation, we will neglect the
Application charging period and thus consider a total discharge time
Suppose that we would like to build a simple AC/DC equal to 1 . From the design characteristics, we can
wall adapter with an NCP1200 delivering a raw DC voltage 2  Fline
with the following specs: evaluate the equivalent current (Iload) drawn by the
charge at the lowest input line condition. Let’s us adopt
 Pout = 3.5 W a 40% ripple level, or a 50 V drop from the corresponding
 Target efficiency: η = 75% → Pin = 4.66 W Vinpeak. To evaluate the equivalent load current (which
 Vout = 6 V, Rload = 10.3 Ω, Iout = 580 mA discharges Cbulk between the peaks), we divide the
 VACin = 100 VAC to 250 VAC input power by the average rectified voltage:
The first step lies in calculating the peak rectified value Pin  Pout
Iload  (eq. 10) = 46 mA
obtained from this line range: Vrect avg Vripple
  Vpeak  2
Vin peak  Vin  2  2  Vf with : (eq. 9) @ 100 VAC input voltage. Thanks to Figure 7b
information, we can evaluate the capacitor value which
Vin: the AC input voltage
allows the drop from Vpeak down to Vavg – (Vripple/2) to
Vf: a forward drop of a bridge diode, 0.7 V @ Id
s t a y w i t h i n o u r 5 0 V t a r g e t : dV  C  i load  dt:
→ Vinpeak = 140 V at low line Pout
Cbulk 
→ Vinpeak = 352 V at high line 2    Fline  Vripple  Vpeak 
Vripple
2

Bulk Capacitor = (eq. 11) 9.3 F or 10 F for a normalized value.

The bulk capacitor supplies the high–frequency current
pulses to the SMPS, while it is refueled at low rate by the High–voltage DC Rail Range
mains. Figure 7a shows a typical rectifying configuration. From the above formula, we can extract the ripple
However, the bulk capacitor should be dimensioned to amplitude at any line level:
provide enough energy between the line peaks. The worse
case appears at the lowest line level combined with the Vripple  Vpeak  1  1  Cbulk   Pout
Fline  Vpeak 2
maximum output current. Figure 7b depicts the voltage
waveform observed over Cbulk in Figure 7a example. (eq. 12)
Iout
Let us now calculate the final average DC value
delivered to the SMPS at high but also low line:
Vout 4.67/V(out) Vripple
Bridge
B1 V HVavg  Vin  2  2  Vf  (eq. 13)
out Current 2
+
+ → 115 VDC @ 100 VAC with a 50 Vpp ripple (initial target)
1 5
+ Cbulk → 343 VDC @ 250 VAC with 19 Vpp ripple (calculated)
Vline N
10 µ To confirm the validity of our calculation, a simple
2
– SPICE simulation can be run where the load is replaced by
a current source. However, thanks to the feedback loop of
Figure 7a. A Full–Wave Rectification Configuration the converter, the input current will vary depending on the
line level. To avoid tweaking the current source at different
Vripple
line levels, Figure 7a’s B1 element computes the input
P SMPS
Vinpeak current according to the required power: Iload 
Vbulk
exactly as the final SMPS would do. Simulations gave a
29 Vpp ripple at low line (VHVavg = 126 V), turning into
12 Vpp at high line (VHVavg = 342 V). The calculations
VHVavg gave less pessimistic results simply because we have
neglected the capacitor re–charge time which reduces its
discharge time.

Diode Bridge Selection

10 ms
To select the right rectifiers, it is necessary to know the
RMS current flowing through its internal diodes. Prior to
reach this final result, we need to evaluate the diode
conduction time. From Figure 8a, we can see that the diode
starts to conduct when VACin reaches Vmin and stops when
Figure 7b. A Typical Ripple Voltage
over the Bulk Capacitor
reaching Vinpeak:

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 AND8023/D

a surge current (when you plug the SMPS in the AC outlet)

less than the diode maximum peak current (Ifsm).
tc
Vinpeak
Thanks to these numbers, we compute the apparent
Vmin
power at low line: 86 mA x 100 V = 8.6 VA which
compared to our 4.66 Watts of active power (neglecting the
Vbulk
input diode bridge and Cbulk losses) gives a power factor
of: PF  W  0.54 (eq. 19) conform to what we could
V.A
expect from this kind of offline power supply. With a
reverse voltage of 400 V, you can select either a 1 A/400 V
bridge or 4 x 1N4007 diodes.

Transformer Calculation
300
mA Idiode VAC in
Transformer calculation can be done in several manners:
X–2 ms/div
a) you evaluate ALL the transformer parameters, electrical
but also physical ones, including wire type, bobbin
stack–up etc. b) you only evaluate the electrical data and
Figure 8a. When VACin reaches Vpeak, the diode leave the rest of the process to a transformer manufacturer.
stops conducting. We will adhere to the latest option by providing you with a
list of potential transformer manufacturers you can use for
From a mathematical point of view, we can calculate the prototyping and manufacturing. However, as you will
time VACin takes to reach Vmin: discover, designing a transformer for SMPS is an iterative
V ACin  sin(  t)  Vmin. Since Vpeak is reached at process: once you freeze some numbers, it is likely that
the input sinusoid top (or one fourth of the input period), they finally appear either over or under estimated. As a
then the diode conducting time tc is simply: result, you re–start with new values and see if they finally
fit your needs. To help you speed–up the transformer
sin 1 V min
design, an Excel design–aid sheet is available from the
V in2
1 AC
tc   = 2 . 1 m s @ Vi n = ON Semiconductor web site, www.onsemi.com/NCP1200.
4  Fline 360  Fline Let’s start the process with the turn ratio calculation:
100 VAC (eq. 14). During these 2.1 ms, Vbulk is the seat
of a rising voltage equal to Vripple or 29 Vpp. Turn Ratio and Output Diode Selection
This corresponds to a brought charge Q of: The primary/secondary turn ratio affects several
Qbulk  Vripple  Cbulk = 290 µC (eq. 15). parameters:
From Figure 8a, we can calculate the amount of charge Q  The drain plateau voltage during the OFF time: the
drawn from the input by integrating the input current over lowest plateau gives room for the leakage inductance
tc spike before reaching the MOSFET’s BVdss:
Np
the diode conduction time: Qin  i diode(t).dt (eq. 16). The Vplateau   (Vout  Vf)  VinDC max (eq. 20).
Ns
0  The secondary diode Peak Inverse Voltage (PIV) is linked
expression of idiode(t) is: Ipeak  tc  t (eq. 17). After to the turn ratio and the regulated output voltage by:
tc
PIV  Ns  VinDC max  Vout (eq. 21). If you lower the
proper integration, it comes: Qin  1  Ipeak  tc . If we Np
2
now equate Qbulk and Qin and solve for Ipeak, it comes: plateau voltage, you will increase the reverse voltage the
Qbulk  2
secondary diode must sustain.
Ipeak  (eq. 17) or 280 mA peak, as confirmed  The amp–turns equation Np . αIp = Ns . Is should satisfy
tc
by the simulation. We can now evaluate the RMS the average output current demand with
c u r r e n t flowing through the diodes: Irms = Ip  toff  Fsw  


Iout avg  Np
(eq. 22). The α parameter
tc 2  Ns
Fline  (idiode(t)) 2  dt  Ipeak  tc3  2  Fline = illustrates the energy diverted by the leakage inductance
at the switch opening (take 0.95 for low leakage designs).
0
With these numbers in mind, you can tweak the turn ratio
(eq. 18) 86 mA @ VAC = 100. A 400 V/1A diode bridge or according to the MOSFET BVdss and the diode. Below are
four 1N4007 can thus be selected for the rectifying given ON Semiconductor references for Schottky diodes:
function. A small resistor is however put in series to ensure

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 AND8023/D

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Reference

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MBRM120LT3
VRRM (V)
20
Io (A)
1.0
Case
PowerMite

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MBRM130LT3

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MBRA130LT3
30
30
1.0
1.0
PowerMite
SMA

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MBRA140LT3

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MBRS120LT3
40
20
1.0
1.0
SMA
SMB

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MBRS130LT3

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ÁÁÁÁÁÁÁÁ
MBRS140LT3
30
40
1.0
1.0
SMB
SMB

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ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
MBRS190T3

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MBRS1100T3
90
100
1.0
1.0
SMB
SMB

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ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
MBRS320T3

ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
MBRS330T3
20
30
3.0
3.0
SMC
SMC

ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
MBRS340T3

ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
MBRS360T3
40
60
3.0
3.0
SMC
SMC

ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1N5817
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1N5818
ÁÁÁÁÁÁÁÁ
20
30
1.0
1.0
Axial
Axial

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ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1N5819
ÁÁÁÁÁÁÁÁ 40
*Please see brochure BR1487/D for thermal and package details.
1.0 Axial

If we select an MBRA140LT3 (VRRM = 40 V), then the current to build up with a slope of VinDC . Because the
PIV should be selected around 35 V at high line: Lp
NCP1200 operates in current–mode, the ON time expires
N  PIV  Vout (eq. 23). If we select Np:Ns = 1: 0.08,
VinDC max when the current setpoint Ip has been reached:
then PIV = 34 V at 350 VDC input voltage which is okay Lp  Ip
ton  (eq. 28). In DCM, we must satisfy equation
with the selected diode. The plateau voltage at the drain VinDC
will establish around 430 VDC: it leaves up to 170 V for the 27. That is to say, the OFF time lasts until the core is fully
leakage spike. reset or the secondary current has come back to zero:
The average diode Idavg current is the converter’s DC Lp  Ip
toff  (eq. 29), with N the turn ratio
output current which is 580 mA, in line with our 1 A N  (Vout  Vf)
MBRA140LT3. The repetitive peak current seen by the between the secondary and the primary and Vf the
Np secondary rectifier forward drop at a given current (≈1 V).
diode is: Ipeak sec    Ip  (eq. 24). The diode In a FLYBACK SMPS, the input power flow is evaluated
Ns
R M S c u r r e n t I drms c a n b e e v a l u a t e d u s i n g : using the formula: Pin  1  Lp  Ip 2  Fsw (eq. 30) with
Id rms  Ipeak sec  Fsw3 toff (eq. 25). Finally, the
2
Lp the primary inductance, Ip the primary current at the end
of the ON time and Fsw the converter’s switching
total conduction losses of the diode can be
frequency. Pin is linked to Pout by the efficiency using:
assessed through the following equation:
Pdiode avg  Vf  Id avg  Rd  Id rms 2 (eq. 26) with Vf the Pin  Pout
 (eq. 31). Combining equations 27, 28, 29, 30,
forward drop at Id = Ipeaksec and Rd, the dynamic 31 and solving for Lp we obtain the critical inductance
resistance dVf @Id = Ipeaksec. value above which we would go into Continuous
dId Conduction Mode (CCM) at the lowest input voltage
Once Ip have been evaluated, you will need to confirm Vripple
the agreement with the diode maximum rating specs. VinDC avg  and maximum output power:
2
Primary Inductance and Peak Current 2
N  (Vout  Vf)  VinDC 
When the SMPS operates in the Discontinuous Lp  
N  (Vout  Vf)  VinDC 2  Pout  Fsw
Conduction Mode (DCM), the sum of the ON and OFF
(eq. 32). Finally, the peak current corresponding to this
times equal the switching period: ton  toff  1
Fsw inductance value can be computed from equations 30, 31:
(eq. 27). From the FLYBACK equations, we can easily
calculate ton and toff. During the ON time, the converter Ip   2Lp Pout
 Fsw
(eq. 33). With our example data in
applies VinDC to the primary inductance which forces the

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 AND8023/D

mind, the calculation gives a primary inductance of 6.4 mH Ip2

Id Ip1 You have that
at Fsw = 40 kHz (nominal NCP1200 switching frequency).
The corresponding Ip is 190 mA. You expect this
In equation 30, two unknowns exist: Lp and Ip. The
above calculations show how to select Lp from a
conduction mode point of view (always stay in DCM), Vg
which leads to a final operating peak current. However,
from equation 6, we can see that a high peak current leads
to a large inductance spike when the switch opens. We
should then try to work at a low primary peak current to
Prop. Delay
avoid this potentially lethal voltage kick. However,
working at a low peak current means a higher primary Figure 9a. The NCP1200 propagation delay leads to a
inductance to satisfy equation 30 which, in turn, induces a slightly higher peak current than expected.
larger leakage energy (the leakage inductance is
proportional to the square of the primary turns)…We thus The data we have are: Lp = 6.4 mH ±10%, Fsw = 40 kHz
need a balance between the low primary current ±15%, Rsense = 3.9 Ω ±5% and Vsensemax = 0.9 ±5%.
requirements combined with our low leakage inductance From these values, we can combine worse case together to
needs. Let’s go over the whole process and see how we can see a) are we always able to deliver our 3.5 W? b) what is
tweak the parameters, keeping in mind that the lowest turn the maximum output power capability?:
number also ensures the lowest manufacturing cost… 2
Vsense min VinDC min
Step 1: Pout min  1  Lp min    t prop
2 Rsense max Lp min
Evaluate the critical inductance value with eq. 32. Ip is
 Fsw min 3.3 W (eq. 37)
calculated via eq. 33 → Lp = 6.4 mH, Ip = 190 mA.
2
Step 2: Vsense max VinDC max
0.9 V Pout max  1  Lp max    t prop
The NCP1200 limits the peak current to: 2 Rsense min Lp max
Rsense
(eq. 34), 0.9 V varying ±10%. We should then select a sense  Fsw max 6.3 W (eq. 38)
resistor from the E24 series, also affected by a ±5% From the above numbers, we can see that we cannot
tolerance, which authorizes the peak current to grow up to deliver the target power in the worse case. Let’s reduce the
the number calculated by eq. 33. The E24 shunt series looks Rsense value to the next reference, 3.3 Ω: (you can use the
like the following for medium output powers: …0.56 Ω, spreadsheet to speed–up this process)
0.68 Ω, 0.82 Ω, 1 Ω, 1.2 Ω, 1.5 Ω, 1.8 Ω, 2.2 Ω, 2.7 Ω,
Poutmin = 4.6 W
3.3 Ω, 3.9 Ω, 4.7 Ω… As you can see, it will be easier to
Poutmax = 8.8 W
pick up an available reference from the E24 series then
Rsense = 3.3 Ω, Lp = 6.4 mH
refine the inductance value to reach our goal. This option
avoids to freeze the inductance without having the From these results, we can consider that 4.6 W is more
necessary flexibility on the shunt. From step 1 and equation than we need. By reducing the inductance value to 5.5 mH,
34, Rshunt = 4.24 Ω. If we select 4.7 Ω, we will have the numbers are updated to:
difficulties to reach our peak current with the previous Poutmin = 4 W
inductance (remember that we cannot increase it otherwise Poutmax = 7.6 W
we go into CCM). Another problem would be the FB Rsense = 3.3 Ω, Lp = 5.5 mH
permanently pushed to the maximum current demand and With this case, the 4 W output power offers a guardband
triggering the overload mode. Therefore, let’s select 3.9 Ω above 14% (4 W compared to 3.5 W) and it will thus leave
from the E24 series and later on diminish the inductance some dynamic on the FB level without triggering the
value to fit eq. 30. Now, we need to apply worse cases of overvoltage protection circuitry.
tolerance variations to see how they affect the final output
power result. To refine the calculation, we will include the Step 3:
NCP1200 overcurrent propagation delay which is 120 ns This final step should give us the type of transformer we
typical. Propagation delay corresponds to the actual time can use for our application. In FLYBACK converters, we
taken by the internal chain to really pull the MOSFET’s need a gap to expand the storage capability of a given
gate to ground when the peak current setpoint has been un–gapped core. The gap presence imposes a decrease in
reached. During this time, the primary current keeps the remnant flux density Br and allows a larger field
excursion before reaching the saturation (a gap does not
growing up with a slope of VinDC (eq. 36). Figure 9a
Lp change the saturation level Bsat nor the coercitive field
details this principle. values Hc). However, the gap is usually made by grinding

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 AND8023/D

the center leg of the selected core (E or RM etc.). This 3. You now need to calculate the specific inductance value
operation can be difficult, especially on small cores used Lp
by applying: AL 
for powers as the one we are looking for. For this reason, N2
most of the manufacturers do not recommend gaps above 4. Evaluate the desired gap length lg (in mm) through the
0.6 mm. Large gaps also generate fringing flux which can following formula:
lead to disturbing ElectroMagnetic Interference (EMI) o  a  N 2  Ae  Lp  lm
lg   1000 (eq. 41) with
leaks. Lp  a
Two methods can be used for the design of the µo the air permeability (4.π.10–7), µa the amplitude
transformer depending on the information given by the core permeability (the core permeability at high flux
manufacturer: excursions), N the turn number, lm the mean magnetic
path length (m).
First Method
Numerical Application
1. From eq. 34 and Lp value, evaluate the maximum
required storage energy capability Lpmax.Ip2max. For our 3.5 W charger operating a 40 kHz, we have
2. Depending on your application constraints (dimensions, selected an E16 core in B2 material (Thomson–LCC)
weight etc.) select a given core geometry (E, RM etc.). offering the following parameters:
3. From the core manufacturer handbook, look at the graph Ae = 0.0000198m

which gives L.I
versus AL curves. Draw a horizontal Bsat = 300mT @ 100°C
line which corresponds to the above required L.I2 µa > 1000 (T° > 100°C, B = 330mT)
number for the selected geometry. Any core references lm = 0.0348 meter
appearing below this curve can be used. However, in an To lower the turn numbers (for leakage but also for
attempt to minimize the leakage inductance (less winding time reasons), we have purposely decreased the
primary turns), try to select the largest AL . previously calculated Lp value down to 2.7 mH which
4. Plot a vertical line which passes through the intersection gives an operating peak current of 290 mA and a sense
point step 3 created. This gives you the AL. resistor of 2.7 Ω.
5. From the AL versus air–gap length curve, extract the
corresponding air–gap and check if it is machinable Applying method 1 leads to:
(< 600 µm?). AL = 60 nH/turn2
6. From the AL, calculate the primary turn number with: Np = 212 turns

N ALLp (eq. 39)

Ns = 17 turns
The manufacturer will need the primary and secondary
7. Finally, check that Bs . N . Ae > Lpmax . Ipmax with Bs RMS currents calculated at the lowest line level:
the core saturation limit at 100°C and Ae the effective
core area. If it fails, reduce the AL value by keeping the
Isec rms  Ipeak sec  Fsw3 toff or 2.7 A (eq. 42)
air–gap within reasonable limits and check that the The primary current is obtained with:
updated turn numbers are still in agreement with the
bobbin capability (the transformer manufacturer will
Iprim rms  Ipeak prim  Fsw3 ton or 184 mA (eq. 43)
normally tell you about it).
8. With the help of the spreadsheet, you have the choice to MOSFET Selection
tweak Lp in order to decrease the turn number to finally The transformer being designed, we can look at the
reduce the leakage inductance. MOSFET type. From equation 20, the plateau voltage
(during the toff duration) rises up to 438 V. By selecting a
Second Method 600 V device, we ensure enough headroom for the leakage
1. Depending on your application constraints (dimensions, spike. If this spike is finally too energetic, we can either
weight etc.) select a given core geometry (E, RM etc.) clamp it with an adequate network or choose a 800 V
2. From the calculated Lp value, evaluate the minimum MOSFET. From equation 43, a 1 A MOSFET is suitable
Lp max  Ip max and can be selected from the below devices:
turn number with: N  (eq. 40)
Bs  Ae

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 AND8023/D

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
Reference

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
NTB10N60 ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
BVdss (V)
600
RDS(ON) (
)
0.75
Peak Current (A)
–
Package
TO–220

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
NTB10N60

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
NTD4N60 ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
600
600
0.75
2.3
–
–
D2PAK
DPAK

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
NTP6N60

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
NTP6N60 ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
600
600
1.1
1.1
–
–
TO–220
D2PAK

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
MTP4N80E

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MTD1N80E ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
800
800
3.0
12
4.0
1.0
TO–220
DPAK

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
MTD1N60E

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MTB3N60E ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
600
600
8.0
2.2
1.0
3.0
DPAK
D2PAK

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
MTP2N60E

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MTP3N60E ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
600
600
3.8
2.2
2.0
3.0
TO–220
TO–220

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MTP6N60E
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ 600 1.2 6.0 TO–220

Let’s pick–up an MTD1N60E which features the needed to push enough Coulomb in the gate to properly bias
following specs: the MOSFET. However, the time during which the drain
BVdss = 600 V falls corresponds to the charging time of the Miller
capacitance or the VGS “plateau” duration. This plateau,
RDS(ON) = 13 Ω @ Tj = 100°C
which occurs at 6 V for the MTD1N60E is not the VGSth
Case = DPAK
parameter (≈3 V). From the MOSFET’s gate–charge chart,
RθJA = 71 °C/W on min pad area
we can extract the amount of necessary Coulomb Qg2 to
Max junction temperature = 150°C cross–over the plateau area: 3.2 nC. The time needed to push
Qg = 11 nC max. (VGS = 10 V) or extract this charge with a given gate resistor is:
Coss = 40 pF Qg2  Rsource Qg2  Rsink
tson  (eq. 48) and tsoff 
If we operate at an ambient of 70°C, the maximum power Vcc  Vplateau Vplateau
the component can dissipate on free–air is given by: (eq. 49), with VCC the lowest supply level delivered by the
Tj max  T A DSS (9.2 V). To minimize the EMI problems, the NCP1200
Pmax  = 1.1 W (eq. 45). The total MOSFET output impedance is asymmetrical: Rsource = 40 Ω
R JA
(turn–on) while Rsink = 12 Ω (turn–off), as already
losses are a combination of the conduction losses and the accounted for in eq. 47 and 48. With these values, we obtain
switching losses. From equation 43, we can compute the tson = 45 ns and tsoff = 6.4 ns. These numbers are rather low
MOSFET conduction losses: Pcond  RDS (ON)  Id 2RMS = because of the small parasitic elements constituting the
440 mW (eq. 46). MTD1N60E. At the switch opening, the MOSFET current
Switching losses appear because of the overlap immediately drops thanks to a small tsoff. But the leakage
between drain current and drain–source voltage during inductance forces Ip to circulate through all the stray
transitions. We have losses during the switch closing capacitance (Clump) and pulls up the drain with a slope of
(Pswon) but also during the switch opening (Pswoff). In Ip
(eq. 50). Because the MOSFET is fully open when
DCM, the turn–on losses are mainly created by the recurrent Clump
discharge of the stray parasitic capacitors in the MOSFET. Vds rises, there are very few associated losses. In the case
The MOSFET contributes to these losses via its Coss Vds (rising) and Ip (decreasing) would intersect together in
capacitor. Unfortunately, Coss does not linearly vary with their middle, the final Pswoff losses could be computed by:
Vds during the transition and an accurate calculation would Vds max  Ip max  ts off  Fsw max
P swoff  (eq. 51) with Vds
require the use of an equivalent capacitor, resulting from the 6
Coss integral over the switching period. To simplify the the highest drain–source level (600 V in worse case and
evaluation, we will stick to the classical Coss given in the without a clamping network). After computation, we obtain
data–sheet, 40 pF max and neglect the other stray 14 mW a slightly optimistic number. The total power
capacitance (e.g. from the transformer or a snubber): dissipation is thus: 440 mW + 175 mW + 14 mW = 630 mW,
Coss  (Vds plateau) 2  Fsw max neglecting the gate losses. This number is below eq. 45 result
P swon  (eq. 47) with and offers a comfortable theoretical security margin. We
2
Vdsplateau given by eq. 20. We obtain 175 mW. To estimate will confront these results with practical measurements on
this ON transition duration, we can calculate the time ts the board to ensure reliable operation.

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 AND8023/D

Output Capacitor Selection is fully reset (toff caption). First, let’s calculate this toff
To evaluate the output capacitor value Cout, we need to duration knowing that the secondary downslope is:
define a given, acceptable level of ripple. The ripple finds (Vout  Vf)  N 2
S sec  or 405 mA/µs. With a secondary
its root in two different sources: Lp
1. The natural integration of the secondary current peak current Isec equal to N . Ip = 0.29 . 12.5 = 3.6 A, toff
(amputed by the DC current delivered to the load) will last 8.9 µs for a 3.5 W nominal output power (IoutDC =
through the capacitance gives birth to a capacitive 500 mA). With this value in mind, we can calculate the
integrated voltage over Cout when subject to a ramping
voltage of Vcap  1  i (t)  dt. This integral is down current starting from (Isec – IoutDC) and lasting 8.9
Cout
toff
valid during the secondary current decay until DCM is
µs: Vcap  1  toff  t 
reached (Isec = 0). The remaining portion of time Cout toff
includes the dead–time (if any) plus the switch ON time. 0
2. The total parasitic contribution of Equivalent Series (Isec  Iout DC)  dt  toff  (Isec  Iout DC). Thanks to
Resistor (ESR) and Inductor (ESL) that produce a 2C
voltage spike at every switch openings. The ESR this formula, we can extract the Cout value by:
toff  (Isec  Iout DC)
contribution only is usually culprit for the majority of Cout  or 490 µF with Vcap = 30 mV
the ripple amplitude. 2  Vcap
ripple. The simulation show higher ripple numbers because
Thanks to simulation, Figure 9b is able to show these of an output power of 4.5 W.
components separately and how they combine together: Unfortunately, the ESR contribution is by far the higher
contributor to the output ripple. This ohmic loss will
generate a thin voltage spike equal to: R ESR .
(Isec–IoutDC). In our case, a 100 mΩ ohmic loss produces
Total Secondary
ripple, 200 Mv/div
up to 300 mV and adds up with the capacitor voltage ripple.
The ESR also affects the capacitor dissipation by: PCout =
I2capRMS . RESR. You can smooth the ESR spike by
Q brought
Icap, 2 A/div inserting a secondary LC filter, as proposed by the various
to Cout
sketches of this application note.
Iout, DC On Duration
Simulating the NCP1200
To ease your design phase, we have developed a transient
and an AC averaged SPICE model for the NCP1200.
Vcap, 20 mV/div Ready–to–use templates are available to download at
www.onsemi.com in these three versions: INTUSOFT’s
IsSpice4, OrCAD’s PSpice and Spectrum–Software’s
VESR, 200 mV/div Cap. Describing these models is beyond the scope of this
application note. However, we will show some typical
waveforms you could quickly get with the help of these
Figure 9b. The final ripple is made of the ESR and tools. Figure 10a portrays a typical IsSpice transient
the output capacitance. simulation using the NCP1200 in our 3.5 W charger
application.
By looking at Figure 9b’s INTUSOFT’s IsSpice plot, we
can evaluate the output capacitor voltage rise until the core

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 AND8023/D

Isec Iout

X1 Vsec
XFMR D1 L1 R16
MBR140P 2.2 µH Vout
RATIO = 0.08 10 m
+
Vout
12 4 31 17
R3 1
200 m
R4
3 100 m R17
Iprim
300 m Rload
L2 Iripple 8
6 32
2.7 mH
+ C1
IHV 470 µF C2
IC = 5.9 10 µF
16
L5
80 µH
+VInput X2 R15
NCP1200 VDrain 470
126 Fs = 40 kHz +
IDrain 19
Vadj 1 8
15
NCP1200

2 7 Drv 10

3 6 VCC X7 X4
5 C3 MOC8101
MTD1N60E 470 pF
4 5
13
18
R5
100 m
D3
1N752

Vsense

23 Rsense
CVCC
10 µF 2.8
IC= 12.1

VFB

Figure 10a. A typical transient analysis of the NCP1200 with a dedicated SPICE model. C3 is
purposely wired between drain–source to highlight the potential substrate injection problems.

The model includes the start–up source, various shown on Figure 10b and 10c. Thanks to short simulation
propagation delays, the short–circuit protection and the times, the NCP1200 SPICE model will help you confirming
driver dual impedance concept. Typical waveforms are the theoretical results you have already calculated.

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 AND8023/D

Vsense
200 mV/div

Vdrain Vdrain
100 V/div 100 V/div

Gate current
contribution
Vgate
5 V/div
Vsense
500 mV/div Possible substrate
injection

Figure 10b. Steady–State Figure 10c. Zoomed portion of MOSFET

Drain–Source and Sense Voltages switch–off time when the snubber capacitor
is wired between drain and source.

By feeding the various components with the choices you The Final Application Schematic
have made (e.g. transformer turn ratio), you can Figure 11a depicts the complete application schematic
immediately verify that you do not exceed the safety limits. used in our NCP1200 AC/DC demoboard. Thanks to the
Such verifications could end–up into smoke on a real weak leakage inductance exhibited by the transformer
prototype test … (≈80 µH), a simple capacitor in parallel with the MOSFET
allows a safe operation up to 250 VAC, but to a slight
detriment of switching losses (eq. 47).

L1 D2 I2
330 µH MBRA140LT3 4.7 µH
+ + 6 V @ 600 mA
C1 C2 + +
4.7 µF 4.7 µF C6 C7
SMD 400 V 400 V 470 µF/10 V 10 µF/10 V
1 Adj HV 8 Ground
T1
2 FB 7 M1
MTD1N60E C4
Universal 3 CS1 VCC 6 470 pF
Input 1 kV D3
4 Gnd Drv 5 Thru Holes MMSZ5V1
10
R1
1W

C3 +
10 µF 1WSMD R4 IC1
16 V 2.7 SFH6156–2 R6
 470

C5
2.2 nF
Y Type

Figure 11a. The 3.5 W AC/DC adapter available as a demoboard

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 AND8023/D

The PCB exhibits compact dimensions (64mm x 35mm) slow it down a little bit by inserting a resistor between pin 5
and includes a simplified EMI filter (L1). In case the and its gate. Below are some typical oscilloscope shots
common mode noise induced by M1 switching too fast taken from the board:
exceeds the standard limits, you still have the option to

Normal Mode Vdrain

VCCH
100 V/div

VCCL

Short Circuit

Latch–Off
Phase Start
and Stop Vsense
500 V/div
0V

Figure 11b. The NCP1200 DSS behavior in normal Figure 11c. Typical 3 W operation that can be
and short circuit conditions. compared to Figure 10b.

Vdrain
Vdrain Vsense 100 V/div
100 V/div 200 V/div

Possible
Substrate
Injection

Vsense
200 V/div
Gate Gate
5 V/div 5 V/div

Figure 11c. This shot confirms our turn–on 45 ns Figure 11d. As predicted by the calculations, the
calculation and shows the absence of immediate turn–off time is extremely fast and does not
drain current. The capacitive peak is blanked with engender losses. The switch is immediately closed
the NCP1200 LEB. and the current is capacitive. This plot can be
compared to Figure 10c.

Figure 11d represents the turn–off stage when the as the injected electrons can go anywhere, possibly
snubber capacitor is wired between drain and source. When engendering an erratic behavior of the IC. To prevent this
the leakage starts to ring, the induced dV/dt forces a situation, simply wire the snubber between the drain and
capacitive current to circulate inside the MOSFET Coss ground, as indicated by Figure 6b and confirmed by
and the snubber. This current unfortunately creates a Figure 11e. In application where you do not install any
negative ringing over Rsense and can potentially inject into snubber, the problem should not appear.
the NCP1200 substrate. This situation is highly undesirable

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 AND8023/D

Vdrain
Vdrain
100 V/div, X = 500 µs/div
100 V/div
Vsense
500 V/div

Vdrain
100 V/div, X = 5 µs/div
Zoomed Current
50 ns/div

Figure 11e. Wiring the snubber between drain and Figure 11g. Standby operation, upper curve is
source avoids the substrate injection. Vdrain with X = 500 s/div.

However, in some higher power applications, the case Depending on the layout, the FB pin can pick–up some
can arise where the spike is present without the snubber in noise which leads to spurious oscillations. To cure this
place. In that later case, we advise to wire a small low–pass problem, wire a 1 nF capacitor between pins 2 and 4.
RC filter between the sense resistor and pin 3. Typical
values are R = 1 kΩ C = 220 pF. Another options lies in
connecting a Schottky diode between pin 3 and ground
(cathode to pin 3). VCC, 5 V/div

Vout
100 V/div

Vgate, 2 V/div

Figure 11h. Typical Operating Curves in

Short–Circuit Conditions

Figure 11f. Demoboard transient response when

banged from 10 mA to 800 mA.

Typical measurements on the 3.5 W AC/DC adapter:

ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
DC Input Level Input Power Output Power 

ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
120 134 mW 0 –

ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
120 732 mW 480 mW 65%

ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
120 1.44 W 1.0 W 69.5%

ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
120 4.08 W 3.3 W 80.6%

ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
325 339 mW 0 –

ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
325 1.06 W 480 mW 45%

ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
325 1.84 W 1.0 W 54%

ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
325 4.3 W 3.11 W 72%

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 AND8023/D

At low line, the DSS contribution is low at about your SMPS into a precise Constant Voltage–Constant
100 mW. It represents nearly all the power consumption Current (CV–CC) generator. For less precise requirements,
and does not significantly affect the efficiency. At higher Figure 12a depicts a configuration where a second loop has
line levels, because of the DSS constant current nature, its been added. This loop operates in parallel with the standard
contribution increases and degrades the efficiency at weak zener one and deviates the LED bias current to regulate the
output power levels. To greatly improve these numbers, current (Q1 active). Of course, the current reference being
you can apply Figure 2 trick or work with an auxiliary the transistor Vbe, it is likely to change over temperature
winding (Figure 3): it will save more than 200 mW. With (–2.2 mV/°C)… However, this design can be selected
the prototype under test, we measure an overload activation where ± 10% current precision is enough. More precise
at a power level of 7 W. designs can be made through a TL431 for better output
precisions but also by combining the bipolar with a CTP to
Battery Charger Configuration compensate the current loop temperature drift.
Certain applications require the control of the output Figure 12a shows a typical configuration plugged into
current, e.g. battery chargers. To precisely monitor the our NCP1200 averaged SPICE model. Thanks to this
output current flow, dedicated circuits already exist from model, we can test for the open–loop stability by drawing a
ON Semiconductor such as the MC33341. This IC has been Bode plot of both loops (I or V) and transient test the
tailored to directly drive an SMPS optocoupler and turn validity of the CV–CC behavior:

Iout

X1
XFMR D1
RATIO = 0.08 MBR140P out 1 L1 R1
out 2
NCP1200 89.6 2.2 µH 10 m + 6.80
IN Averaged OUT
X1 2 1
7.17 6.81 6.81 6.80
NCP1200_AV CTRL FB GND
Fs = 40 k
L = 2.7 mh LoL R4 R17
RI = 2.7 1.37 1 kH 100 m 300 m

∆
12 6.81
120 11 7 Vout
+VIn CoL 6.80 Rload
1 kF 6
120 V 0 C1 25
470 µF C2
13 10 µF
+ Vstim 0.547
AC = 1 5

out 1 out 2
FB

1.37 R8
1 470

X4
MOC8101 R9
68 6.12
6.14
10 15
R3
47 D3
1N752
C4
100 nF 6.14
17
Q1 0.222
2N2222 19
R6 R5
68 100

Rshunt
2.2

Figure 12a. An Averaged SPICE Simulation in a Battery Charger Application

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 AND8023/D

By reflecting the bias points to the schematic, the and is off). By sweeping Vstim, Figure 12b and 12c reveal
simulator (IsSpice4 in this example), indicates which loop the Bode plot of the whole configuration where both loops
is active: the voltage loop in this case (Q1’s Vbe is 203 mV have been represented.

VFB (dB) No comp.

VFB (dB) With comp.

Pm = 90° Pm = –57°
VFB (°) VFB (°) Pm = 42°

0 0

10 dB/div 10 dB/div
45°/div 45°/div

Figure 12b. The voltage sweep does not reveal Figure 12c. However, the current loop is unstable
any problem with a 90° PM... with a large bandwidth.

As the below curves show, there is no problem when the

voltage loop operates. The high gain finds one of its root in Vout in Y
the NCP1200 internal collector resistance which equals 1 V/div
6.4 kΩ. But as you can see, it offers a good theoretical CV Operation
bandwidth associated with a safe phase margin. If we now
activate the current loop, Figure 12c details a strong CC Operation
instability because of the bipolar presence. To cure this
problem in the simplest manner, we can wire a 100 nF
capacitor between FB and ground to roll–off the gain at
lower frequencies. Updated Bode plots confirm the
stability gained by this capacitor addition. This instability
was observed on the evaluation board and also eradicated
by the 100 nF capacitor.
Iout in X
By decreasing LoL and CoL elements down to 1p, we
100 mA /div
actually close the feedback loop. By sweeping the output
load through a variable resistor, we plot the CC–CV curve
as shown by Figure 12d. Figure 12d. The simulated CC–CV output shape
as delivered by Figure 12a.

Please note that these average simulation circuits work with the demo versions of INTUSOFT, OrCAD and
Spectrum–Software.
The complete battery charger schematic appears on Figure 13 and is available as another NCP1200 demoboard.

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 AND8023/D

L1 D2 I2
330 µH MBRA140LT3 4.7 µH
+ + 6 V @ 600 mA
C1 C2 +
4.7 µF 4.7 µF C6 +
SMB 400 V 400 V 470 µF C7
1 Adj HV 8 10 V 10 µF/10 V
T1
2 FB 7 M1 Ground
Universal MTD1N60E C4
3 CS1 VCC 6 470 pF/1 kV R10
Input
4 Gnd Drv 5 Thru Holes 470
R5
10 68
R1
1W C8 C3 +
100 nF 10 µF SMD R4 IC1
16 V 2.7 SFH6156–2 D3
 R6
47 MMSZ5V1

Q1
2N2222
R7 R8
68 100

C5 R9
2.2 nF 2.2
Y Type SMD

Figure 12e. The Complete Battery Charger Demonstration Board

Different scheme will allow various bandwidth and

response times. In that case, the averaged NCP1200 SPICE
model appears as an invaluable tool to help you to place
1V / div poles/zeroes at the correct location.

D1
MBR140P
Vout
L1
330 µH
1
C2 C1
10 µF 470 µF

300 mA / div GND

R15 Vout
270
Figure 12f. The Resulting I–V Curve of the NCP1200 16
R2
Charger Demoboard X4 14 k
MOC8101
Figure 12f depicts the resulting CV–CC obtained when 15
sweeping the charger’s output through a MOSFET and
C5
displaying the values with an X–Y oscilloscope. X3 100 nF
TL431
14 R7
Precise Secondary Regulation 10 k
Any TL431–based regulation scheme can be employed GND
with NCP1200. Figure 13 gives in example the feedback
section only when using a TL431 reference voltage. The Figure 13. A Precise Regulation Option using a
TL431 is usually compensated by wiring a capacitor TL431 Reference Voltage
between the resistor bridge middle–point and the cathode.

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 AND8023/D

Primary Regulation Option are depicted in Figure 13a and 13b sketches. To avoid
Despite the lack of internal error amplifier, two kind of classical peak rectification, a light load e.g. 470 Ω can be
primary regulation options can be implemented: one in connected to load the auxiliary supply. Auxiliary and main
which the short–circuit works as usual and another one power winding ratio should be adjusted to match the
where this option is permanently invalidated. Both options desired output voltage.

HV Rail
D6
1N5819
D5 6 V @ 600 mA
1N4148 + C3
Aux 470 µF
10 V
C2
10 µF
10 V

NCP1200
D4 1 HV 8
5 V1 Adj
2 FB 7
3 CS1 VCC 6 M2
MTD1N60E
4 Gnd Drv 5
R1
470

+
C1 Rsense1
Q1 10 µF
2N3904

Figure 13a. A primary regulation possibility where the short–circuit protection still operates.

HV Rail
D6
1N5819
D5 6 V @ 600 mA
R2 Vaux 1N4148
220 + C3
Aux 470 µF
10 V
C2
10 µF
10 V
D4
6 V2
NCP1200

1 HV 8
Adj
2 FB 7
VCC M2
3 CS1 VCC 6
MTD1N60E
4 Gnd Drv 5
R1
1k

+
R1 C1
20 k 10 µF Rsense1

Figure 13b. Another primary regulation possibility where the short–circuit protection no longer operates.

Transformer Availability E16 version corresponds to a 3.5 W charger operating with

T1 transformer for the depicted circuits (charger and AC an NCP1200P40 (40 kHz) while the 1.8 mH version should
adaptor) is immediately available from several be used for a 5 W NCP1200P60 version (60 kHz).
manufacturers whose details are given below. The 2.7 mH

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 AND8023/D

Eldor Corporation Headquarter Email: asb@wanadoo.fr

Via Plinio 10,
ref. 1: NCP1200–10 W–UM: 10 W for USB
22030 Orsenigo
(Lp = 1.8 mH, 60 kHz, 1:0.1, RM8 pot core)
(Como) Italia
Tel.: +39–031–636 111 Coilcraft
Fax : +39–031–636 280 1102 Silver Lake Road
Email: eldor@eldor.it Cary, Illinois 60013 USA
www.eldor.it Tel: (847) 639–6400
ref. 1: 2262.0058C: 3.5 W version Fax: (847) 639–1469
(Lp = 2.9 mH, Lleak = 80 µH, E16) Email: info@coilcraft.com
ref. 2: 2262.0059A: 5 W version http://www.coilcraft.com
(Lp = 1.6 mH, Lleak = 45 µH, E16) ref. 1: Y8844–A: 3.5 W version
EGSTON GesmbH (Lp = 2.9 mH, Lleak = 65 µH, E16)
Grafenbergerstraβe 37 ref. 2: Y8848–A: 10 W version
3730 Eggenburg (Lp = 1.8 mH, Lleak = 45 µH, 1:01, E core)
Austria SPICE Editors
Tel.: +43 (2984) 2226–0 As mentioned in the text, NCP1200 ready–to–use SPICE
Fax : +43 (2984) 2226–61 platforms are available to download from the ON
Email: info@egston.com Semiconductor Web site in the following formats:
http://www.egston.com/english/index.htm O r C A D ’s P S p i c e , I N T U S O F T ’s I s S p i c e a n d
ref. 1: F0095001: 3.5 W version Spectrum–Software’s µCap. You will find both transient
(Lp = 2.7 mH, Lleak = 30 µΗ, sandwich configuration, E16) and AC analysis templates as described by Figures 10a and
12a. Some of these examples can work on the editor’s demo
Atelier Special de Bobinage
versions, some will require the full version to operate.
125 cours Jean Jaures
Editors demo versions can be downloaded at the following
38130 ECHIROLLES FRANCE
locations: www.orcad.com (PSpice), www.intusoft.com
Tel.: 33 (0)4 76 23 02 24
(IsSpice) and www.spectrum–soft.com (µCap).
Fax: 33 (0)4 76 22 64 89

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AND8029/D

Ramp Compensation
for the NCP1200
Prepared by: Christophe Basso
ON Semiconductor
http://onsemi.com

APPLICATION NOTE
INTRODUCTION Lowering the Peaking
A current mode controlled SMPS exhibits one low
As any current–mode controllers, the NCP1200 can be
frequency pole, ωp, and two poles which are located at
subject to subharmonic oscillations. Oscillations take place
Fswitching/2. These poles move in relation to the duty cycle
when the Switch–Mode Power Supply (SMPS) operates in
and the external compensation ramp, when present. The two
Continuous Conduction Mode (CCM) together with a
high frequency poles present a Q that depends on the
duty–cycle near or greater than 50%. For Discontinuous
compensating ramp and the duty–cycle. Ridley
Conduction Mode (DCM) designs, this normally does not
demonstrated that the Q becomes infinite at D = 0.5 with no
happen. However, at the lowest line levels and when the
external ramp (mc = 1), confirming the inherent instability
SMPS is pushed to its upper output power capability, CCM
of a CCM current–mode SMPS operating at a duty cycle
can engender these oscillations within the current loop. This
greater than 0.5. Below stands the definition of this quality
application note details how to properly cure this problem by
coefficient:
injecting the correct amount of ramp compensation.
Q 1 where mc = 1 + Se/Sn. Se is the
 · (mc · D 0.5)
Origin of the Problem
external ramp slope, Sn is the inductor on–time slope and
A current–mode power supply is a two–loop system: one
D′= 1 – D.
loop controls the inductor peak current while the other
For designers, once the system’s Q has been determined,
monitors the output voltage. The current loop is actually
they should look for the amount of ramp compensation that
embedded into the voltage loop which fixes the final
current setpoint. In CCM operation, the action of the 
will make this number equal to 1: mc  1
0.5 . 1 .  D
current loop can be compared to a sample and hold device.
This sampling action creates a pair of RHP zeroes in the How to Create a Ramp?
current loop which are responsible for the boost in gain at On the NCP1200, you do not have access to any oscillator
Fswitching/2 but also stress the phase lag at this point. If the sawtooth. However, you can easily charge a capacitor when
gain margin is too low at this frequency, any perturbation the gate drive is high, and immediately discharge it when the
in the current will make the system unstable since, as we MOSFET switches off. Figure 1a shows how to simply
said, both voltage and current loops are embedded. You can generate a sawtooth from the gate drive:
fight the problem by providing the converter with an
external compensation ramp. This ramp will oppose the
duty cycle action by lowering the current–loop DC gain,
correspondingly increasing the phase margin at DRV
2
Fswitching/2, finally damping the high Q poles in the R D
Vout/Vcontrol transfer function. As other benefits of ramp Radd1 3
CS
compensation, Ray Ridley [1] confirmed that an external 1 Rsense
ramp whose slope is equal to 50% (mc = 1.5) of the inductor C
downslope could nullify the audio susceptibility in a
BUCK converter, as already calculated by Holland [2]. As Radd2
more external ramp is added, the low frequency pole ωp 150
moves to higher frequencies while the double poles will be
Figure 1a
split into two distinct poles. The first one will move
towards lower frequencies until it joins and combines with A very simple way to generate a ramp
from a square wave signal.
the first low frequency pole at ωp. At this point, the
converter behaves as if it is operating in voltage mode.

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

March, 2001 – Rev. 1 AND8029/D
 AND8029/D

Calculating the RC component values is a rather easy task. 250 µA. With a gate plateau of 11 V, this leads to a resistor of
By drawing the smallest current from the drive to avoid ≈11 V/250 µA = 44 kΩ. With a charging current of 250 µA,
increasing the standby power, R shall be of high value. If this what capacitor do we need to generate a ramp that reaches
is the case, you can consider this system as a current 250 · 8.33 
5.0 V in 8.33 µs? Well, C   416 pF.
generator. By applying Vc · C  i · t , you calculate R and C. 5
Suppose we want to create a ramp that goes up to 5.0 V when However, because the charging current varies during the
a 60 kHz NCP1200 is operating at 50% duty–cycle. The ON ramping (we actually obtain an exponential), we will to
1 reduce both elements to their next lower normalized values,
time is therefore  8.3 s . In order to not bothering
2 · 60 k e.g., 39 kΩ and 390 pF. If we feed our SPICE simulator with
the NCP1200 operation, let’s select a charging current of these values, Figure 1b and 1c confirms the calculations:

4.50
3.50
Vdrive 2.50
1.50
2 500M
R1 D1 Vramp
+ 39k 1N4148
14.0
Vdrv
Vramp 10.0
1
C1
390pF 6.00
2.00
–2.00
10.0U 30.0U 50.0U 70.0U 90.0U

Figure 1b Figure 1c
A simple simulation schematic confirms the calculations: the capacitor voltage ramps up from a few hundred of mV up to nearly 5.0 V.

By ramping from 0.6 V to 4.5 V in 8.3 µs, we have created The external ramp injection will keep Q below 1. To
a signal exhibiting a slope of 468 mV/µs. adhere to this requirement, we must inject a compensating

“What compensation level shall I inject?”  

ramp mc equal to 1
0.5 . 1  1.9. By applying mc
D
Let’s suppose the following specs for our FLYBACK definition, we can deduct the final amount of external ramp
converter:
we must inject: mc  1
Se or Se  (mc  1) · Sn. In a
Sn
VHVDC = 110 V FLYBACK, the ON slope Sn is given by the rectified DC rail
Fsw = 60 kHz
Lp = 1.8 mH applied over the primary inductance Lp: Sn  VHVDC.
Lp
η = 80% With Lp = 1.8 mH, Rsense = 1.5 Ω and the lowest main
N = Np:Ns = 0.1 equals 110 V, then Sn = 91.5 mV/µs once reflected in volts
Poutmax = 15 W over Rsense. To get the final level of ramp compensation,
To calculate the operating duty–cycle D, we need let’s compute Se by: Se  (mc  1) · Sn or 82 mVs . To
to compute the peak current authorizing a 15 W output obtain this ramp from our ramping generator, we must create
power flow from the 1.8 mH primary inductance: a division ratio of 0.082/468 or 175 m. If we select a 10 kΩ
resistor to convey the current sense information, then the
Pin  1 · Lp · Ip? · Fsw. From our specs, we know that
ramp resistor is calculated using: 10 k  0.175 · 10 k or
2
Pin = 15/08 = 18.8 W. At the boundary between DCM 0.175
and CCM, the peak current is evaluated to: 47 k
in this example.

Ip  Lp2 ·· Pin
Fsw
 590 mA. To reach this value, we need to Simulation of the Converter
To check our calculation, we can use the NCP1200 SPICE
Lp model. Figure 2a portrays the application schematic for this
apply VHVDC over Lp during: Ip ·  9.6 s.
VHVDC converter with INTUSOFT’s IsSpice4 model version:
Compared to a 60 kHz switching frequency, it corresponds
to a 58% duty–cycle or D = 0.58.

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 AND8029/D

Iout
X1
XFMR Vsec D4
R3 RATIO = –0.1 1Nxxxxx L1 R16
Vout
200 m BV = 60 10 µH 10 m
+ +
Clp 6 28 4 7 31 17
10 nF Iprim 1
Vclamp Lp R17
R4
1.8 mH 100 m 300 m
+ Rclp Isec Rload
Istartup Iripple1 32 12
16 22 k
12 9
8 C2
+
Vinput L5 C1 220 µF
X2 D3 30 µH
110 NCP1200 220 µF IC = 13.5
MUR160
Fs = 60 k IC = 13.5
Iclamp Vdrain
Vadj 1 8 +
11 Drv Idrain
2 7
5 10 R15
3 6 VCC
18 20 X6 470
4 5
MTP6N60m
NCP1200 13 19
R9 D2 R5
39 k X4
Rconv 1N4148 100 m MOC8101
10 k 21
Vsense 14
Rcomp 15
1 Meg
Vsum 23 Rsense D1
Vramp CVCC 1N964
1.5
C6 22 µF
390 pF
IC = 12.1

VFB
C3
10 n

Figure 2a
The current–mode SMPS built with the NCP1200 SPICE model.

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 AND8029/D

The system enters CCM for a load of 12 Ω and unwanted oscillations (Figure 2c). Rcomp was kept to a high
subharmonic oscillations take place, as shown by Figure 2b. value to suppress any compensating action.
Measurements on the board confirm the presence of these

700M
500M
300M
100M
Primary Current
100M
–

350 Drain Voltage

250
150
50.0
–50.0
1.020M 1.030M 1.040M 1.050M 1.060M

Figure 2b Figure 2c

Oscillations take place when entering CCM with a duty–cycle greater than 50% as confirmed by both models and measurements.

Let’s now diminish Rcomp to 47 kΩ as previously Figure 2d and confirmed by Figure 2e:
calculated and run a new simulation. Results are depicted by

700M
500M
300M
100M
–100M Primary Current
1.01M 1.03M 1.05M 1.07M 1.09M
350 Drain Voltage
250
150
50.0
–50.0
1.01M 1.03M 1.05M 1.07M 1.09M

Figure 2d Figure 2e

The right amount of ramp compensation stabilizes the converter (2d simulated, 2c measured).

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 AND8029/D

The previous default has disappeared and the converter is the NCP1200 pins shall be kept as short as possible to avoid
stabilized. However, the designer shall keep in mind that undesirable peaking. In case of troubles, the solutions
injecting a compensation ramp diminishes the current loop consists in lowering the ramp generator’s output impedance
gain. This has the same effect as raising Rsense on the and re–iterating the other elements.
small–signal point of view. As a result, the controller grows
its operating feedback voltage VFB (that sets Ip) to impose
the same peak current. If before compensation VFB was References
already close to the maximum limit, the ramp injection will 1. R. B. RIDLEY, “A new small–signal model for
make it raise and the possibility exists that the NCP1200 current–mode control’’, PhD. dissertation, Virginia
goes into short–circuit protection (VFB ≈ 4.1 V). Polytechnic Institute and State University, 1990
We deliberately selected a rather high value for the ramp (e–mail : RRIDLEY@AOL.COM). This document
generator resistor in order to not load the NCP1200 can also be ordered from Ray Ridley’s homepage:
(otherwise the standby power can be degraded). As a http://www.ridleyengineering.com/index.html
consequence, the summing resistor Rcomp cannot be too 2. HOLLAND, “Modelling, Analysis and Compensation
low to prevent from disturbing the ramp generator. In a noisy of the Current Mode Converter”, Powercon 11, 1984
environment, the electrical paths conveying these signals to Record, Paper H–2.

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AND8032/D

Conducted EMI Filter

Design for the NCP1200
Prepared by: Christophe Basso
ON Semiconductor
http://onsemi.com

APPLICATION NOTE

INTRODUCTION The Bulk Capacitor is a Natural Shield

As Figure 1a depicts, an SMPS is supplied by a network
If the NCP1200 easily lends itself to designing made of a diode bridge rectifier and a bulk capacitor. Every
Switch–Mode Power Supplies (SMPS) in a snap–shot, its time the mains peak voltage exceeds the bulk capacitor
presence among other equipments necessitates an adequate level, two diodes of the input bridge conducts for a period of
ElectroMagnetic Interference (EMI) input filter. time given by the DC rail ripple: the larger the ripple, the
Fortunately, friendly methods such as SPICE exist to isolate longer the conduction time (≈ 1–3 ms). As a result, Cbulk is
the guilty harmonics and make them stay below the limit. recharged at a rather low rate (every 10 ms for a 50 Hz
This application note briefly describes the mechanism of mains) while the SMPS load draws pulses at its high
conducted EMI noise generation and depicts a way to switching frequency. During the refueling by the diodes,
circumvent it. Cbulk stores energy and delivers this energy during the time
the diodes are off (high series resistance, but still weakly
capacitive).

D
Input Bridge

Co RLoad

+
Cbulk

Mains M1

Figure 1a. A typical component arrangement for an SMPS (here a FLYBACK).

The current flowing through Cbulk is thus the ON time refined into Figure 1b where parasitic elements appear: the
drain current for a FLYBACK converter. Cbulk is Equivalent Series Inductance (ESL) and the Equivalent
unfortunately not a perfect element and Figure 1a can be Series Resistor (ESR).

Input Bridge DC Rail

Cbulk
CM

+ ESR SMPS
DM Signature
Mains
ESL
CM
Ground

Figure 1b. A more realistic way to represent the EMI generation mechanism.

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

April, 2001 – Rev. 2 AND8032/D
 AND8032/D

These technology dependent elements work together to higher frequencies, Z goes up because ESL dominates: this
prevent the capacitor from being a true capacitor. At low is depicted by the well know impedance versus frequency
frequency, the impedance is capacitive (Z goes down when plot as shown by Figure 1c (a 400 V 33 µF snap–in
F goes up, C dominates), at medium frequency the capacitor, Y axis in dBΩ). In SPICE, this is rather easy to
impedance is resistive (Z stays flat, ESR dominates) and at model, as portrayed by Figure 1d.

Mag (dB)
33.00
29.00
25.00 3
C1
21.00 34.4 u
17.00 1
13.00 R1 C2
674 m 640 nF
9.00
5.00 2
1.00 R2
96 m
4
100 1k 10 k 100 k 1M 10 M

Figure 1c Figure 1d

A typical impedance plot of a 33
F 400 V capacitor . . . and its equivalent SPICE

model showing the resonating elements.

Differential and Common Mode Measuring the Noise

As you can see on Figure 1b, there are three current Standards have been established to fix a limit below which
generators: one is for the differential mode (DM) currents your SMPS will not disturb the surrounding equipment
that flow 180° out of phase on each branch while the sharing the same line or outlet (e.g. CISPR22, FCC15 etc.).
remaining two generators depict the common mode (CM) However, since we deal with circulating currents, the
current flowing in phase on both the DC rail and ground. The reference impedance used to measure their action takes on
DM level is caused by the weakness of Cbulk to perform its importance: the mains impedance in ON Semiconductor
filtering function over a large frequency range due to its labs is not quite the same as in your building for instance . . .
friends ESL and ESR. The CM noise finds one of its roots As a matter of fact, international standards have defined a
in capacitive current displacements induced by high dV/dt reference impedance on which the measurements will be
over a key node: the MOSFET drain. This quickly varying made. This impedance is guaranteed by a Line Impedance
voltage present on this pin pushes currents into capacitive Stabilization Network (LISN) and precisely defined by
elements exhibited by the transformer (disposed between all CISPR16 document. Figure 2 portrays how this device is
terminals), the MOSFET (Coss or an additional snubber) made. The LISN offers a 50 Ω impedance over the
and the various capacitive leaks. Instead of coming back to frequency of interest (e.g. 150 kHz–30 MHz for CISPR22)
drain through Cbulk, they continue to transit via the Ground and shields the measurement against unwanted incoming
and the DC rail and come back to the drain after exciting the noises. Please note that the high values of some capacitors
measurement network (a LISN, see its definition below). connected between Live and Earth require the adjunction of
DM currents usually cause troubles in the low frequency an isolating transformer between your mains and the LISN.
range of interest while CM currents bother the designers in
the remaining higher portion of the spectrum. As you can
read, it is of importance to be able to identify who is hurting
the measurement the most in order to take the adequate
solution: CM and DM cures are not the same. Finally, DM
disturbances are rather easy to predict, to the opposite of CM
currents which depend on various stray paths (copper traces
position, stray capacitance etc.) and are extremely difficult
to estimate. Furthermore, because of the unsymmetrical
nature of stray elements, combinations of currents can lead
to an unequilibrated noise distribution over Live and
Neutral . . .

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 AND8032/D

Live Equipment CM inductors are usually of high values (≈ 1 mH to

250 UH 50 UH 50 mH) and strive to route the CM noise current through
1.2 UF 8 UF 0.25 UF earth via Y–type capacitors. However, since earth leakage
current is limited for security reasons, Y capacitors rarely
Measuring
Receiver exceed a few nano–farads thus requiring large CM
inductors. Due to their winding technique (same directions),
10 5 50
CM inductors do not offer any opposition to the DM mode
Hearth (DM currents cancel the internal field). True DM inductors
are either single component or coupled ones (values up to
Figure 2. CISPR16 Network 1 mH). Fortunately, when these CM inductors are crossed by
(Duplicated for the other line(s)) DM currents, the internal field is cancelled: the remaining
inductances are the leakage inductances. If these leakage
Fighting Against Conducted EMI elements are of sufficient values, we can use them for
As we said, DM solutions differ from CM solutions. filtering DM noise. Otherwise we need to add an external
However, some parasitic elements can this time play in our single coil for DM only (Figure 3c).
favor . . . DM will usually be combated using the component
arrangement of Figure 3a while CM requires Figure 3b Lleak
Lcm
arrangement.
Mains To Diode
Bridge
Ldm
+
Lleak
Mains Cdm IN Cbulk
Figure 3c. When crossed by DM current, a
– CM inductor unveils two “leakage
Ldm
inductances”. Typical value would be 300
H
for a 27 mH type, but it really depends on the
Figure 3a. By connecting two inductors (coupled way the manufacturer winds the coils.
or not), you attenuate the differential mode noise.

In some designs, there is no third earth conductor. In that

case, you cannot wire two Y capacitors on the filter input. As
Lcm + we said, these Y capacitors are used to route most of the
current displaced by the drain voltage back to the originator,
Mains IN Cbulk a little crossing the LISN network but low enough to stay
–
below the standard limit. The solution consists in providing
this path through another Y capacitor but connected between
primary and secondary grounds as shown by Figure 3d.
Ccm Again, this capacitor cannot exceed a given value in order to
keep the leakage current within the level imposed by the
security standard (250 µA for all class II equipment).
Figure 3b. Two coupled inductor (wounded in
opposite directions) route the noise to earth
via two Y–type capacitors.

D
Lleak
Lcm +

Mains X–Type IN Cbulk CO

–
Lleak

M1

Y–Type

Figure 3d. A typical two–wire implementation when there is no earth conductor.

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 AND8032/D

Evaluating the SMPS Signature In both cases, we need to evaluate the harmonic content
Before calculating any filter, we need to know the enemy: through Fourier decomposition. In that area, SPICE can
“what harmonic frequency hurts me the most?” On the really help us through its Fast Fourier Transform (FFT)
paper, by hand or with a simulator, we can reasonably algorithm. Without entering into the details (see reference
estimate the amount of DM noise the SMPS will deliver [1]), you can tailor the analysis bandwidth by adjusting the
thanks to a good knowledge of the generation mechanism. duration of your transient simulation:
CM will require a true measurement because many physical
factors influence its content (PCB layout, stray capacitances .TRAN TSTEP TSTOP [TSART] [TMAX] [UIC]
etc.). [optional]
Depending on our topology and its operating mode .TRAN 100NS 801US 400US 50NS UIC
(Continuous or Discontinuous Conduction Mode, CCM or ; 5.2MHz sweep range, 2.493kHz analysis BW, 4010 points (1)
DCM), we can draw the drain current signature. Figure 4a .TRAN 24.44NS 500US 400US 12.22NS UIC
gives the typical plot for a DCM and a CCM FLYBACK ; 20.48MHz sweep range, 10kHz analysis BW, 4091 points (2)
converter. .TRAN 489NS 2.1MS 100US 244.5NS UIC
; 1.024MHZ sweep range, 500Hz analysis BW, 4090 points (3)
Id Id
CISPR22 specifies a 10 kHz analysis bandwidth above
150 kHz up to 30 MHz. This corresponds to the second
Ip
Ip .TRAN command line (2). But SPICE can even help more
by predicting the exact operating point whatever input or
output conditions. Figure 4b and 4c show a complete
INTUSOFT’s IsSpice4 application using the NCP1200
t t together with a LISN built according to Figure 2. The
DCM CCM complete SPICE netlist for the LISN is provided at the end
of this document.
Figure 4a. Typical SMPS signature with two
different operating modes.

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 AND8032/D

Iout
X1 Vsec D4
R3 XFMR 1Nxxxxx L1 R16
10 µH Vout
200 m RATIO = –0.1 BV =60 10 m
+
Vout
6 2 4 7 31 17
Iprim 1
Vclamp
Clp Lp

∆
10 nF R4
1.8 mH R17
Isec 100 m
Rclp 300 m Rload
22 k 14.4
12 Iripple 32
+ 8
Istartup 9 C2
C1 220 µF
16 470 µF IC = 12
L5 IC = 5.9
Iclamp D3 30 µH
MUR160
+VInput
330 VDrain
X2 R15
NCP1200 +
IDrain 470
Fs = 66 k

Vadj 18 19
1 8
11
NCP1200

2 7 Drv 10

3 6 VCC X6 X4
5 MTP6N60m MOC8101
4 5
13
14
R5
100 m
D1
1N962
Vsense
15
23
Rsense
Vsum CVCC
22 µF 1.5
IC= 12.1

C3
1 nF
VFB

Figure 4b. A complete offline simulation template to unveil the desired operating point . . .

X3 F1
LISN –1
CISPR16LISN Controlling Vsource = Vinput
Neutral Neutral
26
Source D.U.T C8
Live Live 34.4 u
Sig. N Sig. L IC =
21

VN 25 R12 C9
674 m 640 nF
13 24

R18 R14
50 R13
50 96 m

Figure 4c. . . . while the input EMI fixture lets you analyze the SPMS signature.

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 AND8032/D

This application represents a 10 W universal input Once the simulation is done, the data manipulation
AC/DC wall adapter operating during given load/line interface lets you run the FFT over VN node. After proper
conditions. To unmask the harmonics, F1 formatting, a graph such as Figure 4d is obtained where the
current–controlled current source routes the high frequency vertical axis is displayed in dBµV (0 dBµV = 1 µV,
current pulses through the equivalent model of our 33 µF 60 dBµV = 1 mV, etc.). To obtain dBµV, Log compress the
capacitor and develops the unwanted noise signal. This Y axis and add 120. We purposely put the CISPR22 class
signal is confronted to the 50 Ω LISN network and a final quasi–peak limit to assess the needed amount of correction.
reading is made on one of the outputs. For simulation Please keep in mind that a quasi–peak detector will give a
reasons, we only use one input, the other one being loaded smaller level compared to a peak detector as we naturally
by a 50 Ω resistor. have with SPICE . . .

90.0
dBµV

70.0

50.0

30.0

10.00

200K 500K 1M 2M 5M 10M

Figure 4d. Further to the simulation, an FFT plot is drawn by the graphical interface.

From this graph, we can clearly identify the value of the range of 200–400 µH if you want to benefit from CM
highest harmonic: 90 dBµV @ 190 kHz (below 150 kHz is leakage inductances. If L is too big, select a bigger
out of the CISPR22 sweep range). To pass the limit, we shall capacitor 220 nF, 330 nF or 470 nF.
reduce its contribution by more than 35 dB, taking into
4. Check the DC input impedance presented by the
account a 10 dB safety margin:
SMPS at the lowest line condition (η = 75%): Pin =
1. Position the LC cutoff frequency fc at a given value to Pout/0.75 = 13.3 W. With a 120 VDC input,
obtain the above rejection at 190 kHz : –35  2
Rin  VinDC  1082 .
–40 . LOG (190 kfc) or fc  190 k  25.3 kHz. P
35
10 40 5. Evaluate the LC filter characteristic impedance by:
2. To avoid any resonance, the filter quality coefficient Q Zo   CL  56  and be sure to follow Zmax << Rin to
should be less than 1. By applying Q definition for a
series LC filter, we obtain the following equation: keep the stability. A plot example of the filter output
impedance will reveal Zmax (the output impedance
Q   · L  1 where Rs is the total series resistance peaking) and endure that the above stability criterion is
Rs
and    1 . The resistance Rs will normally met. It can easily be done by sweeping the LC filter
L·C output terminal through a 1A AC source. Observing the
include all ohmic losses (ESR, inductor series resistance, terminal voltage will display ohms. In our application,
load etc.) but since the 50 Ω load dominates, we will the peaking shows a value of Zmax =
make Rs = 50 for our calculation.
3. Fix C to an arbitrary 100 nF value (for the first step) and
Zo? 
Rs
  2
1
Rs or 38.5 dB with our application
Zo

calculate L by: Rs  315 H. L should be in the values.

2 ·  · fc

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 AND8032/D

40 k
L1
315 µH
Zout 20 k
1 2

dBΩ
0
Rlisn C4
100 nF I1
50 AC = 1
–20 k

–40 k

10 100 1k 10 k 100 k

Figure 4e. By fixing the AC current source to 1 A, Figure 4f. This voltage plot show an output impedance
the voltage probe Zout directly gives ohms affected by a low peaking

The exercise can be completed by sweeping the input and letting naturally circulate differential currents while
impedance of the supply through its average model and measuring the inductance . . . This is what is proposed by
pasting the results on figure 4e graph: there should be no Figure 5a.
overlap between the plots. Also the 50Ω impedance is a Figure 5b finally gives you the final impedance plot of the
simplistic mains impedance representation and might leakage inductor, showing again various stages: resistive in
obviously change depending on your local network the lower portion, inductive in the medium portion and
arrangement. Different sweeps shall be carried on the LC finally capacitive for higher frequencies. At 100 kHz, we
filter to ensure a final low peaking. If the peaking is really can read 48 dBΩ or a 250 Ω impedance. The final
strong, additional damping elements should be installed to calculation leads to an inductance of 398 µH or twice
decrease the filter Q. 199 µH when split into two components. Figure 5c gives its
equivalent SPICE model with ohmic losses measured with
The Final Filter Stage a 4–wire multimeter.
We now have the choice to combine a CM filter together Below stand measurement results comparing CM
with a single inductor for the DM currents. As described in inductors provided by two different manufacturers:
Figure 3d, we can also select a CM filter inductance knowing
its leakage inductance and take benefit from it for DM cure. Schaffner RN1140–08/2:
For a DM inductance below 500 µH, a 27 mH CM inductor Lopen = 23 mH, Lleak = 238 µH or 2 x 119 µH.
can be a good choice. However, we need to precisely Siemens B82723A2102–N1
evaluate the available leakage inductance. With a 1:1 ratio, Lopen = 31 mH, Lleak = 398 µH or 2 x
differential currents cancel the internal field. As a result, 200 µH.
why not connecting together the dotted ends of the choke

L1 MD

Lleak Short

L2

MC

Figure 5a. Shorting the dot–ended windings gives Figure 6a. A transformer to extract DM from CM.
you the value of the total leakage inductance.

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 AND8032/D

Mag (dB)

84.00
75.00
3
66.00
RS
57.00 1.5

48.00
1
39.00
L5 C7
30.00 398 u 20 pF

21.00

12.00 2

100 1k 10 k 100 k 1M 10 M

Figure 5b. A leakage inductance also welcomes parasitic elements. Figure 5c. These elements
can be modeled using SPICE.

As you can imagine, combining the 100 nF–X2 capacitor final attenuation from the input of the filter (where the diode
(who also has parasitic elements) together with a bridge connects) to the final output of the EMI receiver.
Figure 5d–like inductor will deliver a result different from SPICE does it in a snap–shot as shown by Figures 5d and 5e:
what we expect. Actually, the best would be to assess the

X3
LISN
RIf1 LDM1
CISPR16LISN 0.75 200 µH
Neutral Neutral
7 8 1
Source D.U.T
Live Live
C7
Sig. N Sig. L Resr 20 pF
90 m
+ V1
5 6 9 AC = 1
VN CX2
86 nF
R18 R14
50 50 LDM2
RIf2
0.75 200 µH
2
10

C10
20 pF

Figure 5d. This sketch lets you evaluate the filter attenuation once loaded by the LISN device.

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 AND8032/D

–30.0

dB
–50.0

–70.0

–90.0

–110

200K 500K 1M 2M 5M 10M 20M 50M

Figure 5e. The resulting final attenuation versus frequency.

As you can observe on Figure 5e, the rejection tends to Let’s now plug all these elements in Figure 4b test fixture
degrade at higher frequencies due to the presence of parasitic and run a new test. Figure 5f shows how to install these
components. But our attenuation at 190 kHz is 33 dB, elements before the LISN while Figure 5g plots the final
enough to theoretically pass the DM test. results:

F1
Vfilter –1
RIf1 LDM1 Controlling Vsource = Vinput
0.75 200 µH
To LISN
6 8 1
C8
34.4 µF
C7
20 pF
2
Resr
90 m R12 C9
674 m 640 nF
7
CX2
86 nF 3
96 mΩ
RIf2 LDM2 4
0.75 200 µH

10

C10
20 pF
Figure 5f. This sketch shows how the filter finally behaves once loaded by the LISN device.

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 AND8032/D

70.0

50.0
dBµV

30.0

10.00

–10.00

200K 500K 1M 2M 5M 10M

Figure 5g. The resulting spectrum confirming the filter action.

On the paper, we pass the test for DM measurements . . . N signals theoretically gives 0 while you obtain twice the
CM level. At the opposite, subtracting the signals cancels
Real Measurements Versus Simulated Ones CM and gives twice the DM. One limitation however
Using the aforementioned approach, we are able to exists: the impedance offered by both lines shall be
design a filter in a few iterations providing the computer perfectly equilibrated over the frequency range of
is fast enough when running SPICE. But this approach is interest, otherwise the rejection ratio will change . . . We
not worthwhile if true measurements on a board reveal have used an AEMC (Seyssins, France) DM/CM extractor
large discrepancies. First of all, we must be able to extract (reference [2]) to perform our tests (Figure 6a). Figure 6b
differential mode from common mode noise. plots the DM quasi–peak SMPS signature without any
Unfortunately, standards fix limits regarding the total EMI filter obtained with a Rhode & Schwarz ESPC EMI
noise level (CM + DM) available on either L1 (live) or N receiver. These results should be compared to Figure 4d
(neutral), a switch routing either line to the receiver. To drawing. The error on the main peak is only 8 dBs while
allow the study of both noise contents, we have modified the remaining peaks are not far away. Also quasi–peak
a Rhode & Schwarz LISN (ESH–3) to which we added a measurements deliver levels lower than with a peak
second separated output. A switch simply loading one of detector. Keep in mind that the DM/CM extractor ensures
the lines while running the final measurement on the other a good rejection up to 1 MHz (60 dB) while it tends to
one. We now have L1 and N separated. If DM currents degrade in the higher portion. But the overall result is
circulate 180° out of phase on the lines, summing L1 and encouraging.

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 AND8032/D

dBµV EN_V_QP EN_V_AV

90

80

70

60

50

40

30

20

10

0
0.15 1.0 10.0 30.0
MHz

Figure 6b. The DM–only SMPS signature when operated

without any EMI filter (quasi–peak detector).

Let’s now connect our 27 mH CM inductance with a constant less or equal to 1s). The final DM measurement is
100 nF–X2 capacitor over the line, as suggested by given by Figure 6c and confirms an attenuation of 35 dB at
Figure 3d. If this capacitor needs to be increased above 190 kHz, exactly what we were looking for. The margin we
100 nF, a discharge path has to be provided to avoid have here is better than what we obtained in simulation,
electrical shocks when touching the terminals immediately probably because of the quasi–peak internal time constants
after unplugging the supply (IEC–950 defines a time used during measurements.

dBµV EN_V_QP EN_V_AV

70

60

50

40

30

20

10

–10

–20
0.15 1.0 10.0 30.0
MHz

Figure 6c. The final quasi–peak DM–only measurement carried

with an EMI receiver.

Total Noise Measurement Figure 3d. For a two–wire applications, the IEC950 standard
We now know that DM levels are within the limits. To limits the maximum leaking current to less than 250 µA at
attenuate the CM noise, we can wire a Y–type capacitor 250 VAC power supply. The maximum capacitor value you
between the primary and the isolated ground as suggested by can use is thus: Zmin = 250 V/250 µA = 1 MΩ. With a

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 AND8032/D

50 Hz mains frequency, the Y capacitor cannot exceed would fail short. Figure 6d shows the final CM + DM plot
1  3 nF @ 50 Hz or 2.6 nF @ 60 Hz . Start in quasi–peak and clearly testifies for the CISPR22
2 ·  · 50 · 1E6 compliance. This measurement was also successfully
by wiring a 1 nF capacitor or two 2.2 nF in series if you want carried in average at worse operating conditions (100 VAC,
to reinforce the security in case one of the Y capacitors 10 W).

dBµV EN_V_QP
90

80

60

40

20

–20
0.15 1.0 10.0 30.0
MHz

Figure 6d. The final composite QP plot carried over one line while
the other is loaded (230 VAC, Pout = 10 W).

If the test would fail in common–mode, an option is to shows how you normally slow–down the MOSFET during
raise the CM inductor. Otherwise, you need to identify how turn–on and speed up its discharge for turn–off. Figure 7b
noisy nodes can induce disturbances in adjacent copper depicts how the NCP1200 output stage has been designed to
traces or through the air. Carefully look at the rising time on save these two extra components. The driver’s impedance at
the drain, how the output diode eventually rings, and various turn–on is about 40 Ω typically while it drops to 12 Ω for the
other unwanted ringing that could be snubbered by an RC turn–off phase. Figure 6d plot has been captured without any
network. As an advantage, the NCP1200 offers a controlled resistor in series with the MOSFET gate.
turn–on thanks to an asymmetrical output stage. Figure 7a

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 AND8032/D

VCC

Q
2
7
VCC 40

1
Q
2 12

1 5 5

Q\ Q\
3 3

Figure 7a. A standard driver configuration Figure 7b. The NCP1200 already
needs external components to slow down the integrates two resistors which avoid
MOSFET without degrading the turn–off. adding any other components.

Figure 8 portrays a complete working 10 W application example featuring an EMI filter.

D2 L2
C2 R4 22 µH
47 µF 22 k 1:0.1 MBRS360T3 12 V @ 0.85
400 V 2W + + C8 +
B1 C8 Lp C7
L1 SMD 10 nF 1.8 mH 470 nF 100 µF/16 V
Universal 2 x 27 mH NCP1200 400 V 16 V
Input Ground
CM T1 C6
1 Adj HV 8
470 nF
2 FB 7 D3 16 V
R2 MUR160
1 Meg 3 CS1 VCC 6
M1
4 Gnd Drv 5 MTP2N60E R3 R5
560 3.9 k
R1 C1
10 100 nF C4
X2 100 nF
R4
1.5 IC1
1W SFH6156–2
+ K2
C9 C3 TL431 R6
1 nF 22 µF 1k
16 V

C5
2.2 nF
Y Type

Figure 8. A complete 10 W AC/DC wall adapter featuring an EMI filter.

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 AND8032/D

References
1. C. BASSO, “Spice predicts differential conducted EMI
from switching power supplies”, EDN February 3, 1997.
2. AEMC, 86 rue de la Liberté 31180 SEYSSINS France.
Tel. 33 (0)4 76 49 76 76, Fax. 33 (0)4 76 21 23 90.
3. T. WILLIAMS, “EMC for product designers”,
Butterworth–Heineman, 1992, ISBN 0 7506 1264 9.

Line Impedance Stabilization Network SPICE Netlist:

.SUBCKT LISN mainsN mainsL1 measN measL1 L1 N
*
L4 measL1 1 100nH
R9 1 0 1k
C7 1 2 1uF
L5 2 3 1.75mH
R10 3 0 100m
C8 2 L1 1uF
L6 L1 6 50uH
R11 6 7 10m
R12 7 8 3.33
C9 8 0 8uF
C10 7 0 10n
L7 7 10 250uH
R13 10 mainsL1 10m
C11 mainsL1 0 2uF
R3 mainsL1 0 100m
C4 measN 0 10pF
L2 measN 11 100nH
R5 11 0 1k
C5 11 12 1uF
L3 12 13 1.75mH
R6 13 0 100m
C12 12 N 1uF
L8 N 16 50uH
R7 16 17 10m
R8 17 18 3.33
C13 18 0 8uF
C14 17 0 10n
L9 17 20 250uH
R14 20 mainsN 10m
C15 mainsN 0 2uF
R17 mainsN 0 100m
.ENDS
*********

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AND8038

Implementing the
NCP1200 in a 10 W AC/DC
Wall Adapter
Prepared by: Christophe Basso
ON Semiconductor http://onsemi.com

APPLICATION NOTE
INTRODUCTION rugged 10 W adapter. This adapter is designed to operate
from a universal mains (90–260 VAC) while providing a
The NCP1200 implements a standard current mode good standby power at no load.
architecture where the switch–off time is dictated by the
peak primary current setpoint. By combining fixed The Electrical Schematic
frequency and skip cycle operation in a single integrated Driving an external MOSFET, the NCP1200P60, only
circuit, ON Semiconductor NCP1200 represents an requires a sense element and a Vcc capacitor. Working
excellent solution where cost and ease of implementation together with an internal high–voltage current source, this
are premium: low–cost AC/DC adapters, auxiliary Vcc capacitor provides the NCP1200 with an average DC
supplies, etc. Furthermore, the device does not require any level of 11 V typically while it also controls the short–circuit
auxiliary winding to operate and thus offers a real time out. All these parameters are detailed in the application
breakthrough alternative to UC384X based supplies. This note AND8023 available to download at www.onsemi.com.
application note details how to build an efficient and The electrical schematic appears in Figure 1:

D2 L2
R7
22 k
MBR360T3 22
H
1:01
2W 12 V @ 0.85 A
C8 Lp + + C6b +
+
C2 10 nF 1.8 mH 470
F C7 100
F/16 V
47
F 400 V 16 V
Ground
400 V T1 C6a
470
F
D3 16 V
1 Adj HV 8 MUR160 R3 R5
B1
SMD 2 FB 7 560 3.9 k

Universal Input 3 CS VCC 6 M1

4 Gnd Drv 5 MTP2N60E

C1
R2 C4
1 Meg 100 nF 100 nF
X2
L1
R1 2 x 27 mH CM
Schaffner + R4
10 C5 IC2
RN1140–08/2 C3 1.8 TL431 R6
22
F 1W 2.2 nF
Y Type 1k
16 V

C9
1 nF

Figure 1. A 10 W AC/DC adapter built with the NCP1200

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

April, 2001 – Rev. 3 AND8038/D
 AND8038

As stated in AND8023, the Vcc capacitor needs to be protection activates again. If the short–circuit has gone, the
evaluated taking into account the startup sequence (actually IC resumes its operation and delivers its normal level. To
seen as a transient short–circuit by the controller). An check the correct value of the calculated Vcc capacitor, you
internal error flag is raised within the NCP1200 when an need to monitor both output voltage and Vcc level on an
output overload occurs. If this error flag is still asserted oscilloscope. A shot as proposed by Figure 2 confirms the
when the Vcc capacitor reaches UVLOLow (around 10 V validity of a 22 µF choice. We can see that the internal error
typical), then the IC goes into the latch–off phase: the output flag goes high first but as soon as Vout reaches its target
drive is locked and the internal consumption falls down to level, the flag goes back to zero, confirming the normal
350 µA typical. When another Vcc breakpoint is reached controller behavior at the UVLOLow checkpoint. This
(around 6.0 V), then the internal current source turns on experiment should be carried in the worse case conditions,
again and the IC tries to restart. If the error is still present, the e.g. low mains and maximum output load.

Error flag
Ok, flag = 0

Figure 2. The startup sequence shows a Vout establishment before UVLOLow is reached

Feedback Loop (R6) = 1.0 kΩ. This network ensures a bridge current flow
In this application, a precise output voltage is obtained of 2.0 mA which is good for the noise immunity. As any
through the use of a TL431. Since we target a 12 V output, closed loop systems, a compensation network needs to be
you calculate the upper and lower voltage sense elements by tailored to stabilize the loop. In this aspect, the NCP1200
applying the following formula: average SPICE model will save you a tremendous amount

Vout  
Rupper
Rlower

1· Vref
of time. The simulation template appears in Figure 3 on the
following page, showing how to wire the NCP1200 average
model with INTUSOFT’s IsSpice4.
Depending on the TL431 type, Vref can be 2.5 V or 1.25 V.
With a 2.5 V reference, Rupper (R5) = 3.9 kΩ and Rlower

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 AND8038

Iout
X1 out1 L1
NCP1200 Rs out2
XFMR
Averaged 127 22 µF 10 m 12.2
RATIO = 0.1 +
IN OUT
2 4 6
CTRL FB GND D1
LoL MBR140P
1 kH X1
2.38
1 NCP1200_Av R4 R5 R17
120 FS = 66 k 100 m 100 m 300 m
12
+ L = 1.8 m
Vin CoL RI = 1.5 12.2 12.2 12.2 Rload
126 1 kF 14
0 15 7 9
Vin
14
+ C1 C5 C2
Vstim 470 µF 470 µF 10 µF
AC = 1

out1 out2

R15
560
2.38
Vout 11.8
11
5

Rupp
Cf 3.9 k
11.1 100 nF
10

2.50
X3
TL431 13
Rlow
1k

Figure 3. The average model of the NCP1200 when used in AC analysis

The loop is kept opened in AC thanks to LoL which the AC stimuli to allow Bode plot generation. Figure 4
exhibits a fairly high value. However, during its bias point portrays the simulated results with a 100 nF feedback
calculation, SPICE opens all capacitors and shorts all capacitor, while Figure 5 offers the true measurement
inductors. Therefore, LoL closes the loop in DC but blocks curves.

Mag (dB) Phase (deg)

Phase
Gain 80.00 180.00
60.00 135.00
40.00 90.00
BW = 600 Hz
20.00 45.00
0
0.00 0.00
Y = 20 dB/div Y = 45°/div –20.00 –45.00
–40.00 –90.00
–60.00 –135.00
–80.00 –180.00

10 100 1k 10 k 100 k 10 100 1k 10 k 100 k

Figure 4. Bode plot obtained using SPICE
Figure 5.
confirmed by a network analyzer
measurement

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 AND8038

As you can see, curves are in good agreement, despite the switching cycles in standby operation. By default, skip cycle
small DC gain error which predicts a slightly lower takes place at 1/3rd of the maximum peak current: 200 mA
bandwidth in the case of SPICE. In both cases, the phase and in our case. Because skip cycle frequency will naturally
gain margins confirm the good stability of the design, but enter into the audible range, it is important that the skip
also the validity of the SPICE model (based on Ben–Gurion current value does not engender noise. Fortunately, if that
University GSIM approach). The NCP1200 FB pin being a would be the case, you could still wire a resistor bridge on
high impedance path, a 1.0 nF placed between this pin and pin 4 to fix a DC point different than the default one (1.4 V).
ground will prevent any noise picking during operation. As a result, you can force skip operation to happen at less
than 1/3rd of the maximum peak current. However, keep in
Transient Results mind that the highest peak currents in skip mode offer the
Using the NCP1200 design aid spreadsheet lead us to a best standby power. This is because of the switching cycles
transformer offering the following specs: Lprim = 1.8 mH, population within the bursts: less cycles mean less switching
Np:Ns = 1:0.1, RM8 or E25 core. For ease of losses and better efficiency at no load.
implementation, this transformer will be available from A quick method to assess the RMS current in the
Coilcraft, as referenced in the bill of material. The maximum MOSFET consists in simulating the whole AC adapter with
peak current has been fixed to 600 mA. This value SPICE. This has already been presented in AND8029 and
essentially defines the air gap requirement in the transformer the schematic will not be reproduced here. The simulated
but also the final potential transformer mechanical noise results are given below through Figure 6 and Figure 7 while
generated in standby. As explained, the NCP1200 skips the supply is delivering 10 W:

1.030 M 1.040 M 1.050 M 1.060 M 1.070 M

Figure 6. Transient results obtained with IsSpice4
Figure 7. Compared to true measurements

Worse case conditions (low mains, maximum output power in free–air conditions (without a heatsink) of:
current) gives an RMS drain current of 230 mA. Associated Tj  Tamb
Pmax   1.3 W. Further switching losses
with a 6.5 Ω Rds(ON) @ Tj = 100°C, the conduction losses Rj  a
grow up to 340 mW. Using a TO220 package for the measurements confirm the ability to use this MOSFET
MOSFET, offers the ability to dissipate a given amount of without any heatsink up to an ambient of 80°C.

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 AND8038

dBµV EN_V_QP
90
80

60

40

20

–20
0.15 1.0 10.0 30.0
MHz

Figure 8. The final composite QP plot carried over one line while
the other is loaded (230 VAC, Pout = 10 W)

Conducting EMI Filtering Final Performance

The 10 W NCP1200 demo board is equipped with a front We have carried some power tests on the 10 W adapters
stage filter who lets you pass the CISPR22 EMI tests in both and the below numbers will confirm the pertinence of
quasi–peak and average detector methods. The method we choosing ON Semiconductor’s NCP1200 for your next
used for calculating the filter is described in AND8032 designs:
“Conducted EMI Filter Design for the NCP1200’’. The front
stage is made of a single common mode (CM) choke whose VinDC Pout(W) Pin(W)
(%)
wiring method gives enough leakage inductance for 126 0 0.245 –
differential mode (DM) filtering. Figure 8 plots the final
126 10.5 12.6 83.3
CM+DM noise component confirming the test passing.
356 0 0.462
356 10.5 13.17 79.7

The standby power can be further reduced by

implementing one of the method proposed in AND8023
either through an additional diode or an auxiliary winding.
Thanks to its inherent protection circuitry, NCP1200
protects the power supply in presence of a permanent output
short circuit. When shorted, the average output current was
less than 500 mA.

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 AND8038

10 W Demoboard, Bill of Material C6a 470 µF/16 V, vertical

R1 10 Ω, 1 W through holes C6b 470 µF/16 V, vertical
R2a R2b 2 times 560 kΩ SMD in series C7 100 µF/16 V, vertical
R3 560 Ω SMD C8 10 nF/400 V
R4 1.8 Ω, 1W SMD or 1.8 Ω 1 W through holes D1 MUR160, ON Semiconductor
R5 3.9 kΩ SMD D2 MBRS360T3, ON Semiconductor
R6 1 kΩ, SMD B1 Bridge 1 A/600 V, mini DIP
R7 22 kΩ, 2 W through holes Transformer available from Coilcraft U.S, ref. : Y8848–A
L1 Schaffner RN114–08/2 Mains connector: Schurter GSF1.1202.31 with fuse
L2 22 µH, 1 A
M1 MTP2N60E, TO–220 through holes, Other Available Documents Related to NCP1200:
ON Semiconductor AND8023/D, “Implementing the NCP1200 in Low–Cost
IC1 SFH615A–2, SMD (optocoupler) AC/DC Adapters”
IC2 TL431BC (TO–92), ON Semiconductor AND8029/D, “Ramp Compensation for the NCP1200”
IC3 NCP1200P60, DIP8, ON Semiconductor AND8032/D, “Conducted EMI Filter Design for the
C1 100 nF X2/ 250 VAC NCP1200”
C2 47 µF/400 V, snap–in vertical PSpice, IsSpice4 and Micro–Cap Averaged and Transient
C3 22 µF/16 V, vertical models available in ready–to–use templates at
C4 100 nF, SMD www.onsemi.com
C5 1.5 nF Y1 type only NCP1200 Design aid spreadsheet with EBNCP1200/D

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 AND8038

Printed Circuit Board Details

Figure 9. Component Side, Silk Screen, Scale 1

Figure 10. Solder Side, Silk Screen, Scale 1

Figure 11. Copper Traces, Scale 1

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AND8042/D

Implementing Constant
Current Constant Voltage
AC Adapter by NCP1200
and NCP4300A
http://onsemi.com
Prepared by: Hector Ng
ON Semiconductor APPLICATION NOTE

Introduction Circuit Description

This paper describes a compact design of constant current Circuit and BOM of the AC adapter is shown in Figure 1
constant voltage (CCCV) AC adapter based on the current and Table 1. This design can accept universal AC input from
mode PWM controller NCP1200 and the secondary side 90 V to 264 VAC. Bulk capacitors C5 and C6 are split by
feedback IC NCP4300A. By these two ICs from ON inductor L1 and L2 to form the EMI filter as well as to
Semiconductor, circuit design is much simplified. These provide energy storage for the remaining DC to DC
devices enable users to meet ever increasing demand of converter circuit. Thanks to dynamic self supply of
smaller dimension and more sophisticated protection NCP1200 (please refer to NCP1200 data sheet), Vcc
feature of AC adapter. capacitor C7 is charged to startup voltage 11.4 V and the
On the primary side, NCP1200 is used as the PWM power MOSFET MTD1N60E starts switching. To reduce
controller. This current mode controller requires very few power consumption of NCP1200, HV pin (pin 8) is supplied
external components and no auxiliary winding is needed to by half wave rectification through a parallel combination of
supply this IC. In addition, NCP1200 can fulfill IEA diode D6 and resistor R13. A small signal diode 1N4148 is
recommendation easily because it features a pulse skipping enough for this function because diode D6 just has to
low power consumption mode. withstand one diode drop during negative half cycle. R13 is
NCP4300A is a general purpose device which consists of to equilibrate the voltages on the 1N4148 when both diodes
two operational amplifiers and a high precision voltage and high volt current source of NCP1200 are in the off state.
reference. One of the operational amplifiers is capable of rail R12 is to set the power level at which NCP1200 goes into
to rail operation. NCP4300A is employed to provide voltage pulse skipping, please refer to below section for more
as well as current feedback to NCP1200. details. RCD snubber R1, C1 and D3 provides the necessary
Output of the AC adapter is maintained at 5.2 V from no snubbing function to prevent drain voltage of MTD1N60E
load to 600 mA. Further increase in load enters constant to exceed 600 V. Choosing suitable value for the sensing
current output portion and output is kept at 600 mA down to resistor R7 is very important as it limits the primary peak
zero volt. This output characteristic assures a basic current during power up. If its value is too low, the system
protection against battery overcharge which is needed by a cannot deliver enough power during full load low AC input.
lot of applications, for instance cellular phone AC adapter. On the contrary, the transformer may go into saturation and
damages Q1 and NCP1200. Information on how to
determine value of R7 is elaborated in latter paragraph.

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

February, 2001 – Rev. 1 AND8042/D
 D1
L1 MUR120
470 µH
0.2 A 470p 250 V 100 k 1 W
L3
D2 4.7 µH
1N5819 1A 5.2 V, 600 mA
C1 R1
90–264 VAC + +
C5 C6
+ 4.7 µ 4.7 µ R2
DF06S U1 R4 R3
– 1 U2 400 V 400 V 1.5 k 3.3 k 10 k
V4 D3 + + 1% +
4 3 1 8 1N4937 C4
2 7 C2 C3 47 µ
3 6
Q1 10 µ 330 µF R5
4 5 10 k
2 1%
NCP1200
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MTD1N60E C10 U3 R6
1 nF

AND8042/D
NCP1200D60 Out1 VCC 0.15
250 VAC 1 8
D6 Y1 In1– Out2
1N4148 2 7
2

In1+ In2–
3 6
+ R7 R10 Ground In2+
C7 68 k 4 5 R8
3.3 2.7 k R9
47 µF 0.6 W 1% 470
NCP4300AD
SFH6156–3
R13 R11
220 k 4 1
C9 75 k
0.047 µF 1%
C8
2 0.1 µ
R12
L2 10 k D4
470 µH 3 U4
1N4148
0.2 A

D5
1N4148

Figure 1. Circuit Description

 AND8042/D

Table 1.
Reference Part Quantity Manufacturer
U1 NCP1200D60 1 ON Semiconductor
U2 DF06S 1 General Semi or IR
U3 NCP4300AD 1 ON Semiconductor
U4 SFH6156–3 1 Infineon
Q1 MTD1N60E 1 ON Semiconductor
C1 470 p, 250 V 1
C2, C7 10 F, 25 V 2
C3 330 F, 35 V 1 Panasonic FC Series or Rubycon JXA Series
C4 47 F, 16 V 1 Panasonic FC Series or Rubycon JXA Series
C5, C6 4.7 F, 400 V 2
C8 0.1 F 1
C9 0.047 F 1
R1 100 K , 1.0 W 1
R2 3.3 K 1
R3, R5 10 K, 1% 2
R4 1.5 K 1
R6 0.15 W, 0.1 W SMT 1
R7 3.3  , 0.6 W 1
R8 2.7 K , 1% 1
R9 470  1
R10 68 K 1
R11 75 K , 1% 1
R12 10 K 1
R13 220 K 1
D1 MUR120 1 ON Semiconductor
D4, D5, D6 1N4148 3
D2 1N5819 1 ON Semiconductor
D3 1N4937 1 ON Semiconductor
L1, L2 470 H, 0.2 A 2
L3 4.7 H, 1.0 A 1
T1 Transformer 1
C10 1.0 nF, 250 VAC, Y1 Cap 1

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 AND8042/D

The secondary side of the transformer consists of 2 OP2 is below ground. Once the output current reaches
windings, the output winding as well as a higher voltage 600 mA, feedback action is taken over by OP2 and one will
winding which is used to supply power to NCP4300A. As see a drop in output voltage if load is further increase but
the output may drop to 0 V during constant current output current remains constant. C9, R10 and C8, R9
operation, turn ratio of this higher voltage winding must be provide necessary feedback compensation for voltage and
able to sustain minimum Vcc as specify by NCP4300A. Or current loop respectively.
else, the system will be lost of feedback and the output is not
under control anymore. Figure 2 shows the internal block of Transformer Design
NCP4300A. A 2.6 V, 1.0% tolerance voltage reference is Transformer design involves very tedious calculation. An
connected to the non–inverting terminal of OP1. Thus, OP1 Excel spreadsheet has been specially designed for NCP1200
gives voltage feedback when its inverting terminal is to facilitate user with a quick determination of transformer
connected to the potential divider R3 and R5. Characteristic parameters. Table 2 and Table 3 display the results of the
of the voltage reference is similar to industry standard spreadsheet after keying in system parameters. Although
TL431 and a bias current supplied by R2 is needed to recommended transformer primary inductance is 4.6 mH,
guarantee proper operation. This 2.6 V is also divided down 3.2 mH is chosen instead. A lower primary inductance
by R11 and R8 to provide reference for output current enables us to have a lower flyback voltage added to the drain
sensing. Voltage developed at the non–inverting terminal of of the power MOSFET. This in turn allow us to use a less
OP2 is: heavy snubber which implies less power dissipated on the
snubber. Disadvantage of a lower primary inductance is the
VCC increase in MOSFET conduction loss because of higher
primary peak current. However, output of this AC adapter is
only 3.0 W and typical RDS(on) of MTD1N60E is merely 5.9
Out1 Out2  . Increment in conduction loss is not significant in this
OP1 OP2 case.
After the primary inductance is determined, we have to
- + + -
decide on the ferrite core. It can be seen from the Excel
In1– In2– spreadsheet that E16/8/5 core is big enough for this
transformer. Primary (N1) and secondary (N2) number of
turns needed are 166 and 12 respectively. However, one
more winding N3 is required to supply NCP4300A. It is
critical that voltage output of N3 must be higher than
minimum operating voltage of NCP4300A even when
GND In1+ In2+ output has dropped to 0 V. Under this condition, output
winding loop can be represented by Figure 3.
Figure 2.

Vcurrent  reference  2.7 K2.7K75 K· 2.6  0.09 V D2

L3
47 µH
1N5819
Since Out1 and Out2 are wired together by diodes D4 and 1A
D5, feedback current through the opto–coupler U4 is Short
VO(SC)
dominated by whichever op–amp output that has a lower Circuit
voltage. Thus feedback is dominated by OP1 until voltage R6
developed across R6 reaches 0.09 V and this is equivalent to 0.15
600 mA passing through R6. Thanks to the rail to rail
capability of OP2 in NCP4300A, current sensing function is
guaranteed although voltage of non–inverting terminal of Figure 3.

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 AND8042/D

Table 2.

NCP1200 DISCONTINUOUS MODE DESIGN WORKSHEET

System Parameters
Vmax 264 V Maximum AC Input Voltage User Input Cells
Vmin 90 V Minimum AC Input Voltage Results
Fline 50 Hz Line Frequency
Vmin(DC) 85.73 V Minimum DC Voltage
Fs(max) 69 KHz Maximum Switching Frequency
Fs(typ) 60 KHz Typical Switching Frequency
Fs(min) 51 KHz Minimum Switching Frequency
Vo 5.2 V Output Voltage Selected Device
Io 0.6 A Maximum Output Current 60 KHz
 75% Efficiency
Vbd 600 V Power MOSFET Breakdown Voltage
Vd 1V Output Diode Voltage Drop
PI 4.16 W Input Power
Iin(pk) 0.21 A Maximum Primary Peak Current
Vo′ 85.72 V Reflected Output Voltage
Vpwr_sw(max) 459.07 V Maximum Voltage across the Power Switch Circuit (Less Leakage Spike)
Dmax 0.50 Maximum Turn On Duty (Full Load, Low Line)
Iin(av) 0.05 A Maximum Input Average Current
Ratio N1/N2 13.83 Turn Ratio Between Primary and Secondary
Recommended Lp 4.650 mH Recommended Primary Inductance
Lp 3.200 mH Primary Inductance
RDS(ON) 16 ohm Maximum RDS(ON) of Power MOSFET
Pdls(pwr_sw) 0.12 W Maximum Conduction Loss of Power MOSFET
Input Filter Capacitor
Recommended Cin 14 F Recommended Input Filter Capacitance
Cin 9.4 F Input Filter Capacitance
Output Diode Selection
Io(pk) 2.40 A Output Peak Current
Vro 32.20 V Output Maximum Reverse Voltage

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 AND8042/D

Table 2. (continued)

NCP1200 DISCONTINUOUS MODE DESIGN WORKSHEET

Wire Selection
Iin(rms) 0.08 A Maximum Input RMS Current
Io(rms) 0.98 A Maximum Output RMS Current
Lay_p 1 Layer of Primary Winding
Lay_s 1 Layer of Secondary Winding
Primary Wire Size AWG 35 Maximum Wire Size
Secondary Wire Size AWG 24 AWG 24
RMS Current Density 4.9 (A/mm2)
Core Selection
Flux Density Safety Factor 0.4
Bobbin Usage Factor 0.4
Core Type Core Core Core Core Core
Type A Type B Type C Type D Type E

Core Name E 16/8/5 EI28–Z E25/13/7 E 30/15/7 E32/16/9

Ae 20.1 86 52.5 60 83 mm2 Effective Area
Bsat 0.5 0.5 0.5 0.5 0.5 T Saturation Magnetic Flux
Density

Aw 22.3 39.4 61 90 108 mm2 Bobbin Winding Window Area

Abob 8.92 15.76 24.4 36 43.2 mm2 Usable Area of Bobbin for
Winding

Gap Length d 0.22 0.05 0.08 0.07 0.05 mm

N1 166 39 63 56 40 Primary Number of Turns
N2 12 3 5 4 3 Secondary Number of Turns
Ap 0.02 0.02 0.02 0.02 0.02 mm2 Area of Single Turn of Primary
Wire

Lay_p 1 1 1 1 1 Layer of Primary Winding

Apri 3.98 0.93 1.52 1.33 0.96 mm2 Area of Primary Winding
As 0.26 0.26 0.26 0.26 0.26 mm2 Area of a Single Turn of
Secondary Wire

Lay_s 1 1 1 1 1 Layer of Secondary Winding

Asec 3.12 0.73 1.19 1.04 0.75 mm2 Area of Secondary Winding
Asum 7.09 1.66 2.72 2.38 1.72 mm2 Total Winding Area
Enough Space? OK OK OK OK OK
Maximum Peak Current (Sensing Resistor) Setting
DLp 10% Tolerance of Primary Inductance
Lp(min) 2.880 mH Lowest Primary Inductance
Lp(max) 3.520 mH Highest Primary Inductance
Ip(worst) 0.24 A Worst Case Maximum Primary Peak Current
(Lowest Switching Frequency and Lowest Primary Inductance

Rsense(max) 4.20 ohm Maximum Allowable Sensing Resistance

Rsense 3.30 ohm Sensing Resistance
Binit 0.32 T Magnetic Flux Density During Startup

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 AND8042/D

Table 3.
Transformer Specification
Primary Inductance Lp 3.200 mH
Core Type = E 16/8/5
Primary Wire Size = AWG 35
Layer of Primary Winding = 1 Select Core Type
Primary Number of Turns N1 166 Core Type A
Secondary Wire Size = AWG 24
Layer of Secondary Winding = 1
Secondary Number of Turns N2 12
Gap Length d 0.22 mm
Enough Space? = OK
Input Filter Capacitor
Input Filter Capacitance Cin 9.4 F
Output Diode
Maximum Reverse Voltage Vro 32.20 V
Sensing Resistor
Sensing Resistance Rsense 3.30 ohm

During flyback cycle, voltage across the output winding

Vo(sc) is: N3

Vo(sc) = V(D2) + V(L3) + V(R6) + V(PCB trace) N1

N2
V(D2) = forward voltage drop of 1N5819 ≈ 0.6 V
If resistance of L3 is 0.1  , V(L3) = 0.1  × 0.6 A = 0.06 V
V(R6) = 0.15  × 0.6 A = 0.09 V N1 = 166T, AWG # 34,  : 0.16 mm
If resistance of PCB trace is 0.15  , V(PCB trace) = N2 = 12T, AWG # 24,  : 0.51 mm
0.15 
× 0.6 A = 0.09 V N3 = 40T, AWG # 34,  : 0.16 mm

Core = E16/8/5
Therefore Vo(sc) is 0.84 V and volt/turn is 0.84/12 = 0.07. Magnetic Material = PC40 or N67
Minimum operating voltage of NCP4300A is 3.0 V. Its Air Gap = 0.22 mm (center limb)
Primary Inductance (Across N1) = 3.2 mH
supply winding voltage has to be 0.6 V higher if we assume
forward drop on MUR120 is 0.6 V. Minimum number of Figure 4.
turns required for this winding is 3.6/0.07 ≈ 52 turns. As can
be seen from the schematic, these 52 turns can be added on For discontinuous mode operation, maximum power that
top of the output winding. Therefore 40 turns is enough for can be delivered by the system is:
N3. When output is 5.2 V, supply winding voltage of
NCP4300A is approximately 24.5 V. Thanks to its wide P max  1 LpI2pk(max) f
2
operating voltage, 24.5 V is below maximum operating Where Lp is the primary inductance which we already
voltage of NC4300A (35 V). The final design of the decided and f is the switching frequency. In other words,
transformer is shown in Figure 4. Ipk(max) must be high enough to give full load power and this
Another important consideration is the value of sensing implies that R7 cannot be too high. The Excel spreadsheet
resistor R7. Value of R7 control maximum primary peak has calculated for us that R7 must be lower than 4.2  . 3.3
current by the following equation.  is chosen to give some headroom during transient
Ip(max)  1.0 V response. Before finalizing on this value, one must make
R7

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 AND8042/D

sure that transformer does not saturate at power up. During Vstby/4
power up when output voltage is much lower than rated
value, MTD1N60E is switched off not by PWM action. The VCS
power MOSFET is switched off because the primary peak
current has reached its maximum allowable value, Ip(max).
Ip(max) drives the transformer core up the B–H curve of the Figure 6.
magnetic material. B, magnetic flux density must be lower
than the saturation value Bsat. For most magnetic material, Therefore the input power level Pstby that enters standby
Bsat equals 0.5 T at room temperature. Nevertheless, Bsat mode is given by the following equation.

V4Rstby7 f
falls as temperature increases and at 120°C, Bsat becomes
0.35 T. Last row in Table 2 shows the magnetic flux density Pstby  1 Lp
2
during startup. The value is 0.32 T, thus 3.3  should give
us a safe startup.
 0.5
3.2 E  3
40.466

3.3
2
60000
Pulse Skipping Mode
NCP1200 has a pulse skipping standby mode feature and  0.12 W
the power level to enter standby mode is adjustable. Figure 5 At light load condition, efficiency should be lower than
shows the equivalent circuit of the Adj pin with a 10 K that of full load. Assume efficiency is 50% when input
resistor connecting Adj pin to ground. When the voltage at power is at 0.12 W, load current Io(stby) at that time is:
Io(stby)  0.12 W
50%  0.01 A
FB pin falls below Adj pin, NCP1200 starts to skip cycle.
This voltage Vstby is: 5.2 V
10 K29 K
Remember that Vo drops when Io attains 0.6 A. When Vo
Vstby  · 5.2 V  0.466 V drops below certain voltage, NCP1200 will also enters pulse
10 K29 K  75.5 K
skipping mode. Once again, assume efficiency is 50% when
input power is at 0.12 W, Vo(stby) at that time is:
Vo(stby)  0.12 W
50%  0.1 V
NCP1200
0.6 A
In summary, NCP1200 starts pulse skipping when Io is
75.5 k below 0.01 A or Vo is below 0.1 V.
+ Adj
10 k
5.2 Vdc Actual Performance
– Figure 7 and Table 4 shows the actual performance of the
circuit.
29 k

5
OUTPUT VOLTAGE

4
Figure 5.
3
Since NCP1200 is a current mode device, there is a direct
relationship between voltage at the FB pin and the voltage 2
developed by the peak current across the sensing resistor, ie.
voltage at CS pin, Vcs. As can be seen from the block 1
diagram of NCP1200 datasheet, Vcs is compared with one
fourth of FB pin voltage. Therefore at the verge of entering 0
into pulse skipping mode, we should see a relationship as 0 0.2 0.4 0.6 0.8
shown on Figure 6. OUTPUT CURRENT

Figure 7. Vo–Io Characteristic @ 110 VAC Input

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 AND8042/D

Table 4.
Test Conditions Results
Line Regulation Vin = 90 to 264 VAC, Io = 0.6 A  = 0.5 mV
Load Regulation Vin = 110 VAC, Io = 0 to 0.6 A  = 3.0 mV
Vin = 220 VAC, Io = 0 to 0.6 A  = 3.0 mV

Output Ripple Vin = 110 VAC, Io = 0.6 A 40 mVpp

Vin = 220 VAC, Io = 0.6 A 40 mVpp

Efficiency Vin = 110 VAC, Vo = 5.2 V, Io = 0.6 A 68%

Vin = 220 VAC, Vo = 5.2 V, Io = 0.6 A 61%

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 AND8069/D

AND8069/D

Tips and Tricks to Build

Efficient Circuits with
NCP1200
Prepared by: Christophe Basso http://onsemi.com
ON Semiconductor
14, rue Paul Mesplé – BP1112 – 31035 TOULOUSE Cedex 1, France
33 (0)5 34 61 11 54 APPLICATION NOTE
e–mail: christophe.basso@onsemi.com
Introduction winding, an efficient Over Voltage Protection (OVP) circuit
The NCP1200 easily lends itself to designing can be implemented. Figure 1 depicts the solution.
Switch–Mode Power Supplies (SMPS) in a snap–shot and At rest, when the SMPS is properly working, Q1 and Q2
its success speaks for itself. However, customers are transparent to the operations because the 10 kΩ resistors
applications (and problems) are unique and often necessitate block them. As soon as the auxiliary winding level exceeds
the addition of specific component arrangements around the the zener voltage and fires Q2, the whole SCR turns on and
IC. As usual, solving one particular design constraint brings via the 1N4148, pulls FB low. As a result, it immediately
another one with it, perhaps puzzling the designer even stops the 1200 driving pulses: the SMPS shuts off. However,
more. This application note answers typical questions that a the Dynamic Self–Supply (DSS) being still alive (Vcc
designer can raise when starting his own system analysis, ramps up and down between 10–12 V), the 47 kΩ resistor
but also tries to answer some problems common to keeps the SCR latched despite the disappearance of the
Switch–Mode Power Supply applications. default. Once the user cycles Vcc down and up again (e.g.
by unplugging the power supply from the mains outlet), the
Adding an External Latching Circuit for Over Voltage
SCR de–biases and allows the 1200 to restart. Q1/Q2 could
Protection or Over Temperature Shutdown
be ON Semiconductor dual combo bipolar MMBT3946DW.
When pulling NCP1200’s feedback pin below the skip
If for transformer noise reasons Vpin1 is much lower than
cycle level (pin1 voltage), output oscillations cease. If this
its default value (1.4 V), a BAT54 must be wired in place of
action is accomplished through a thyristor, permanent
the 1N4148 to ensure that FB passes well below Vpin1:
latch–off occurs until the user cycles the Vcc down and up
Q2_Vcesat + Vf < Vpin1. Increasing the value of the 47 k
again by unplugging the power supply. By firing the
will change the total latch–off behavior into auto–recovery
thyristor via a zener diode connected to an auxiliary
mode, as the default over current protection does.

HV Vout

Aux.
47 k

10 k 1 8
1N4148
Q1 2 7
NCP1200
3 6
18 V 4 5
bias
Q2

0.1 µF bias
10 k Rsense

Figure 1. A Dual–Transistor Arrangement Latches–Off the NCP1200 in Case of an OVP Event

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

August, 2001 – Rev. 0 AND8069/D
 AND8069/D

Vcc or aux. Vcc or aux. will quickly rise, lowering the DSS capability to its
minimum value stated in the data–sheet. This value being
R1
2.8 mA @ Tj = 125°C, care must be taken that Tj stays lower
than this number to ensure adequate safety margin. Needless
T
Q1 R1 to say that the DIP8 option offering much better thermal
specs compared to SO–8, it will be preferred in high Qg
T applications. A good news is that the internal NCP1200
consumption significantly reduces with temperature (see
characterization curves in the data sheet) and consequently
to SCR base to SCR base eases the DSS.
Now suppose that you would like to drive big MOSFETs,
Figure 2. A NTC and a Simple PNP Make an
featuring large Qg e.g. 60 nC or even 100 nC. It becomes
Easy–to–Build Thermal Sensor Which Fires the SCR
impossible to use the DSS. Should you try, you would
observe a Vcc that immediately collapses below 10 V after
A temperature shutdown can be realized on top of the turn–on: all the current the DSS delivers is eaten by the
above SCR by adding a PNP, as portrayed by Figure 2. The MOSFET driving. Even if this poor situation would work,
Negative Temperature Coefficient sensor (NTC) is selected you would not be able to sense a short–circuit anymore
to pull the PNP’s base toward ground at the wanted because the function is activated only if the Vcc goes up and
shutdown level. To obtain slightly more dynamic on the base down, e.g. between VccOFF and VccON. As a result, using
level, a simple diode is inserted in series with the emitter. A an auxiliary winding becomes the only solution. However,
more economic solution involves a single thermistor, also we will see below that the aux. winding can degrade the Over
shown on the same picture. Current Protection (OCP) trip point. Figure 3 offers an
Driving Big Gate–Charge MOSFETs interesting intermediate solution where the aux. winding
What actually limits the NCP1200 drive capability is the plays an important role but does not bother the DSS
DSS and not its driver stage. The driver output connects a operation, keeping the precise OCP trip point intact.
40 Ω resistor between Vcc and gate (see 1200 data sheet) In this example, Q1 buffers the drive output and the
during the ON state whereas a 12 Ω is connected in the energy necessary to drive the big MOSFET is derived from
discharge path (OFF time). If the MOSFET exhibits a large the auxiliary winding. At power–on, the DSS charges both
total gate charge Qg, turn–on and turn–off times will be capacitors, Caux and CVcc which are isolated by D1 as
longer but it will properly work, probably generating high soon as the auxiliary voltage has built up above the
switching losses. Problems usually arise because those big NCP1200 VccON level. The drive current passes through
MOSFETs heavily load the DSS and it is important to assess Q1 and the 1200 delivers a small current to bias its base. At
the total current consumption in worse conditions. This total the opposite, D3 routes the gate current inside the 1200 as
consumption can be evaluated through the following usual. A resistance can be inserted between the emitter and
formula: Itotal = Icc1 + Fswitchingmax x Qgmax. Suppose the gate to slow–down the turn–on transition. The no–load
that we use a 3 A MOSFET affected by a 25 nC Qg, then the standby performance is better than without auxiliary
total average current that the DSS must deliver is: 750 µA winding because the only current seen by the DSS is
+ 72 k x 25 n = 2.5 mA, if you would select a P60 version. roughly Icc1 which is low. Figure 3 clearly allows the
The DSS current is 4 mA @ Tj = 25°C. However, when NCP1200 to build SMPS of any output power levels,
supplied by the high–voltage rail, the junction temperature Flyback or Forward.
VBulk
8 HV
Vaux > Vcc, e.g. Vaux = 14 V
D2 D1
1N4148 Vaux 1N4148
6 Vcc

Caux Q1 CVcc
Aux. 22 µF 2N3904 22 µF

Rslow
down
5 Drv
D3
Rsense
1N4148

Figure 3. By Taking the Energy from the Auxiliary Winding Only at Turn–On, DSS Operation Is Not Bothered and
IC Consumption Is Kept Within Safe Limits

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 AND8069/D

Reducing the Standby Power with an Auxiliary 22

Winding that Disables the DSS Operation Aux.
In certain applications, a low standby power is mandatory.
10 nF 22 µF
This option clearly prevents from using the DSS because the
1200 supply would be the most consuming portion of the
SMPS in no–load conditions. To stop the DSS, an external
voltage must force the 1200 Vcc to be permanently above Figure 5. A Resistor and a Capacitor Can Integrate
VccON or 11 V as given in the data sheet. Failure to reach the Perfidious Leakage Inductance
that level would imply a DSS re–activation with all the
1N4148 BAT54 220
losses in standby. Wiring the auxiliary winding with Vcc,
skip–cycle components can be a little tricky, especially if pin6
you target an extremely low standby power. Why? Because 100 µF 100 µF 15 V
in standby, the pulses are not a continuous flow but a short
burst whose recurrence can be as low as several tens of
milli–seconds (skip cycle technique). Provided your
auxiliary circuit exhibits some losses, you will not be able to Figure 6. This Configuration Ensures Self–Supply in
maintain a self–supply above 11 V, re–activating the DSS Standby and Prevents Vcc from Exceeding the 16 V
again. Another problem takes place: the primary to Maximum Rating
secondary leakage inductance. This inductance generates a
spike detected by the auxiliary diode which artificially raises Using an auxiliary winding as wired according to Figure
the auxiliary voltage (Figure 4 with arbitrary levels). This 6 offers true short–circuit protection but the precise over
effect can accidentally destroy the 1200 but also deteriorate load mode detection brought by the DSS is lost. This is
the OCP detection point. imputed to the primary leakage inductance, which in some
cases is so energetic, that a short on the secondary power
winding cannot drop the auxiliary winding, preventing
25.0 Leakage effect: Vpeak = 24.2 V short–circuit detection. Reducing the primary clamp level
(via the RCD network) represents a good solution, but to the
15.0 “clean” plateau, V = 13.4 V detriment of the efficiency. If this is a problem in your
0V application, below are other solutions keeping all the 1200
5.0 goodies with an auxiliary winding.
A 70 W demo board was built using an auxiliary supply
and revealed less than 100 mW standby power at 350 VDC
–5.0
–
input level.

–15.0
– Using Auxiliary Winding Without Affecting the OCP
Trip Point, but Disabling the DSS
236U 240U 244U 248U 252U One great aspect of the DSS, is the fact that the OCP
circuitry is activated whatever the auxiliary voltage is,
Figure 4. The Leakage Effect Seen on the
Auxiliary Side Pulls–Up the Final Level
because it does not use any! In low standby power
Peak–Rectified by the Diode applications, you will need to wire an auxiliary winding to
permanently disconnect the DSS. Unfortunately, the 1200
As the NCP1200 Vcc cannot exceed 16 V, care must be internal OCP circuitry activates when Vcc crosses VccON
taken at the design stage to limit the voltage excursion while (≈ 10 V) while going down. This action naturally takes place
running nominal load. A good solution would be to first with the DSS, but if you wire an auxiliary winding, it just
integrate the leakage spike and then rectify the wave with a disappears because you managed to keep Vaux above 10 V
diode as Figure 5 suggests. Unfortunately, in standby, the to invalidate the DSS. As a result, if you overload the output,
auxiliary level would collapse because the burst energy is so NCP1200 will activate its burst only when the auxiliary Vcc
low that the 22 Ω would dramatically limit the 22 µF collapses below 10 V. And what happens if you have a poor
re–fuelling current. We will exploit this feature in a later coupling between the windings and a large primary leakage
application. inductance (see Figure 4)? You never detect the OCP.
The solution consists in splitting the rectifying section in We have seen that the leakage inductance generates an
two blocks, the second one clamping Vcc below 16 V. This energetic spike that couples to the auxiliary winding. Why
solution is depicted by Figure 6. The BAT54 is only here to not sampling the auxiliary voltage on the plateau, a short
avoid hampering the startup time by charging two capacitors time further to the leakage appearance? This is exactly what
together. If this is not a problem, you can simply omit it. The Figure 7 circuit does for you.
zener voltage can be lowered but the maximum VccOFF
(12.5 V) must be reached otherwise the 1200 won’t startup.

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 AND8069/D

D2 When the main power switch is ON, capacitor C13 is

Q3
1N4148 discharged through R22 and D7 whereas D1 avoids a deep
2N3906 Vcc
reverse bias of Q4 base–emitter junction. When the main
R22 R21 R20 switch opens, the secondary voltage sharply rises and node
10 k 10 k 100 k 1 becomes positive. However, C13 being discharged, Q3
stays open and Vcc does not grow up. After a short period
Laux R1 CVcc
of time (adjustable through R21 or C13), Q4 closes and
D7
10 k 22 µF brings Q3’s base closer to ground. Vcc now goes up and
1N4148
catches up node 2 level, minus Q3’s Vce sat. If the time delay
Q4 is correctly selected, Vcc is absolutely clean from any
2N3904
D1 C13 voltage spike because you have sampled the plateau.
1N4148 2.2 nF Figure 8 details the scope shot obtained using this circuit.
As you can see, the sampling time occurs right after the
leakage and the auxiliary level extracted from this plateau is
clean. This solution can also be very useful in application
Figure 7. The Delay Introduced by Q4 Samples Right
After the Leakage and You Obtain a Nice DC Voltage
where precise primary regulation is needed.
With this solution, the off–time is truncated to avoid the
leakage effect. In standby, when skip cycle takes over, this
off–time is considerably reduced and our delay circuit loses
quite a bit of precious energy: the auxiliary winding collapses
Q4 Collector and cannot self–supply anymore the 1200. To combine the
advantages of a clean self–supply (remember, to get a precise
overcurrent trip point or a good primary regulation level if
any) together with excellent standby power performance,
Figure 9 offers an interesting solution. The schematic
becomes more complicated but has been tested fine.
Q1 and Q2 perform their duty as described above but
when voltage is present over C2, Q3 is biased and keeps D8’s
Sampling Here anode low enough to block it. When the supply enters
standby, C2’s level goes low and unleashes Q3 which can
now let the current flow through D8, keeping 1200
self–supplied in standby. As soon as the load comes back,
Q3 closes again and C2 recovers its role.
Figure 8. By Delaying the Sampling Time,You Obtain
a Clean Auxiliary Level Without Any Leakage Effect
D8 R5 D6
BAT54 470 1N4148

R6 C3
330 R8 100 µF
6.8 k
Q3
1 8
2N2222
D1 D2
2 7
R7
NCP1200 1N4148 1N4148
10 k
3 6

4 5 R3 Q1 R1
100 k 2N2907 12 k
D3 R2
1N4148 12 k
C4 R4
100 µF C2
12 k
100 nF
Q2 Laux
2N2222 C1
2.2 nF

Figure 9. A Shunt Prevents the Auxiliary Level to Supply the 1200 in Normal Operation But Becomes Active in Standby

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 AND8069/D

Using Auxiliary Winding Without Affecting the OCP longer pulls R5 to the ground and D5 can pass all the
Trip Point and Keeping the DSS Working auxiliary level developed across C2 to block the DSS. R5
The DSS offers a very interesting feature which is the value can be adjusted to avoid too much of wasted power as
ability to implement true overload detection. Standard long as D5 stays blocked in nominal load operations. The
UC384X–based systems are usually built with an auxiliary standby power becomes as good as stated before: less than
winding but because of the poor cross–regulation between 100mW at high line. Thanks to this latest solution, you can:
the windings, it is almost impossible to implement a precise • Drive the MOSFET of your choice: all the ON current
over load protection. However, these systems can usually is drawn from the auxiliary winding.
cope with short–circuit constraints because the auxiliary
• Benefit from the DSS activity to build a precise over
winding finally collapses when Vout equals zero. (See
current detection and use its ripple for EMI jittering.
Figure 4 to see who is guilty.) As such, the DSS is a very
desirable choice when true over load protection is required • Disable the DSS in no–load conditions and obtain one
by the customer. Unfortunately, in no–load conditions, the of the best standby power on the market.
DSS being connected to the high–voltage rail, you directly
Inserting a Resistor with Pin8 to Avoid
measure this power consumption on the input, despite the Over–Dissipation of the Package
low current consumption of the 1200. In some very stringent Some users like to use the SO–8 package mainly because
standby power requirements, you simply cannot accept of its small size. Unfortunately, the thermal resistance
these losses. Figure 10 presents a solution built on top of that junction–to–ambient makes the exercise difficult because
presented in Figure 3. the DSS naturally dissipates heat (except if use some
alternative solution as depicted below). The auxiliary
R5
820 D5
winding option is still possible, but the best Over Current
Node 8 voltage Protection (OCP) trip point is obtained with the DSS. The
collapses in standby DSS being active, there is no other alternative than
and releases Q3 dissipating this heat through copper, or, move it to another
D2 D1
6 Vcc component, e.g. a series resistor. By inserting a resistive
element in series with pin8, every time the DSS turns on, you
C2 C1 drop some voltage across the resistor (Figure 11) . You thus
D4
Aux. 100 µF 47 µF
spread the total power between two components instead of
R2 one, lowering NCP1200 Tj inside the SO–8 package. The
100 calculation is easy. You know by the data sheet that every
Q3 time the DSS turns on, 4 mA flow inside pin8 at
R3 steady–state. If one keeps about 50 V minimum on pin8 to
C3 10 k R6 properly operate the DSS, the resistor value can be
47 µF 1.0 k calculated through:
Rdrop  Vbulk min
50
Q1 4m
D3
Gate 5 Drv
DSS is off

Figure 10. This Solution Upgrades Figure 3 Option DSS is on Vcc

by Disabling the DSS in Standby

The trick used to detect the standby or no–load condition,

is to take benefit from the the weak energetic content of the
P=0 HV
burst pulses when the supply operates in standby. That is to
say, if the refueling current circulating through D4 is
diminished by a resistor (R2), then C3 will never be able to
maintain a normal operating voltage (e.g. as the one at
nominal load) and it we be severely reduced. In the example, Vdrop > 50 V
Vpin8
P = Vdrop × 4 mA
we measured 15 V in normal load, and less than 3 V in
standby. In normal operation, C3’s voltage is high enough to 180M 220M 260M 300M 340M
forward bias Q3 via R3/R6. His collector pulling R5
terminal to ground, D5 is naturally blocked and the DSS Figure 11. By Inserting a Resistor with Pin8, You Can
plays its role: precise over load mode detection, and EMI Split the Power Between an Active and a Passive
jittering through its ripple. When the SMPS goes to standby, Component in Order to Keep Tj Lower
C3’s level decreases until Q3 gets un–biased. Its collector no

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 AND8069/D

Below are two examples showing the benefits of inserting 250 ns

the resistor. 16.0

Case 1: 12.0 Drive

Single mains, 230 VAC ± 15%, NCP1200 average
consumption is around 2.5 mA. DSS duty–cycle is 62%. Gate
8.0
Vbulk max = 374 VDC and Vbulk min = 276 VDC.
Rseries = (276 – 50)/4 m = 56 kΩ.
4.0
1. Without the resistor, NCP1200 would dissipate
(worse case): 374 x 2.5 m = 935 mW,
incompatible with the SO–8. With an RtetaJA of 0
100°C/W, the maximum power the NCP1200D
48.6U 49.0U 49.4U 49.8U 50.2U
version can handle at an ambient of 40°C is:
125°C – 40°C/100 = 850 mW Figure 12. When the Gate Follows the Drive, the LEB
2. By inserting the 56 kΩ resistor, we drop 56 k x Works Fine
4 m = 224 V during the DSS activation. The power
dissipated by the NCP1200 is therefore: Pinstant x 250 ns
DSS duty–cycle = (374 – 224) x 4 m x 0.62 = 16.0
372 mW. We can pass the limit and the resistor
Drive
will dissipate 935 – 372 = 563 mW. 12.0

Case 2:
8.0
Universal mains, 90 – 27 5VAC, NCP1200 average
consumption is around 2.5 mA. DSS duty–cycle is 62%. Gate
Vbulk max = 388 VDC and Vbulk min = 127 VDC. Rseries 4.0
= (127 – 50)/4m = 19 kΩ.
1. Without the resistor, NCP1200 would dissipate 0
(worse case): 388 x 2.5 m = 970 mW,
incompatible with the SO–8. 48.0U 49.0U 50.0U 51.0U 52.0U
2. By inserting the 19 kΩ resistor, we drop 19 k x Figure 13. Delaying the Gate–Source Signal
4 m = 76 V during the DSS activation. The power Produces the Effect of Truncating the LEB
dissipated by the NCP1200 is therefore: Pinstant x
DSS duty–cycle = (388 – 76) x 4 m x 0.62 = HV
773 mW. We can pass the limit and the resistor
will dissipate 970 – 773 = 197 mW.
1 8
“When I Insert a Resistor in the Gate of My MOSFET,
2 7
the Supply Becomes Instable” NCP1200 Rg
The Leading Edge Blanking (LEB) circuitry has the role 3 6

to clean the voltage appearing across the sense resistor. By 4 5

discharging all the parasitic capacitors at turn–on, you create
a current spike that can engender false tripping of the current
comparator. To avoid this problem, NCP1200 includes a C1 R3
Rsense
LEB calibrated at 250 ns. The LEB starts to blank the current 220 pF 470
sense information as soon as the driver goes high. Figure 12
displays the drive and gate signals when a resistor inserted
between gate and driver is small. This represents a normal
Figure 14. This Network Re–Enforces the LEB Action
operating conditions where the gate follows the driver. by Integrating the Sense Signal Whatever the Gate
However, inserting a larger resistor in series with the gate is Delay
a common practice when one wants to slow down the main
switch, e.g. for EMI reasons. Unfortunately, the resistor “What MOSFET’s Size Can I Drive in Half–Wave
delays the turn–on of the MOSFET and truncates the Configuration?”
Leading Edge Blanking (LEB) which no longer plays its role In some of the available application notes, we propose to
(Figure 13). In that case, false triggers occur and instabilities wire pin8 not to the bulk capacitor but to the rectifying
takes place. The cure consists in adding an RC network half–wave. This solution is acceptable for low gate–charge
between Rsense and the current sense pin (Figure 14). MOSFETs only, because the DSS current capability is

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 AND8069/D

divided by two in average (half–wave duty–cycle is around Vf vs Temperature

50%). As a result, the DSS can only deliver 2 mA DC which 750
divides between the controller (Icc1) and the driver

Forward Voltage (mV)

consumption, utilized to charge up the MOSFET’s Qg. If we 700
take the very worse case that appears at high temperature, the
DSS minimum current is 2.8 mA which divided by two
makes 1.4 mA. Removing Icc1 (≈750 µA, this number goes 650

down when Tj goes up), we have 650 µA with 100 µA left

to charge the Vcc capacitor. As a result, with a 60 kHz 600
version, the maximum Qg would be: 550 µA/60 k = 9 nC.
This corresponds to a 1 A MOSFET or a 2 A MOSFET 550
featuring low gate charge only. If you wire a bigger 25 45 65 85 105 125
MOSFET, Vcc will collapse without the classical ripple 2 V Temperature (°C)
due to the DSS operation. No ripple means no OCP because
Figure 15. Collecting Data Points and Feeding a
the 10 V error flag test has gone. (See application note
Spreadsheet Unveils the ESD Junction Temperature
AND8023/D for more detailed explanation.) In summary, Behavior
we recommend half–wave operation only in configurations
that guarantee proper DSS operation at any temperature. IIN

“I Have Routed My 1200 with a Large Copper Area

Around the Package. What Power Can I Dissipate?”
The maximum power accepted by the NCP1200 is given by: –
1 8
to Vf–meter

+
Tj max
Tamb max
+
2 7
Pmax  NCP1200 +
R
J
A 3 6
Vcc
VIN
As you can see, you could define yourself two parameters in 4 5
the formula: Tjmax given by the data sheet, or the maximum
operating temperature your Quality Department fixes, and
finally Tambmax, given by your application. Unfortunately,
you cannot determine RθJ–A because the copper area you
Figure 16. Next Step Is to Inject Power Into the Chip
added has actually changed it from the original data sheet
specification. The best is to measure it with a simple method
With that graph on hand, we can now start measuring our
that has proven to be accurate enough for our purposes. First,
RθJ–A. On the same PCB board, make a short between Vcc
you need a bare PCB featuring the copper area you have
and ground, leave all the other pin open but keep the
routed. It can be your final board without anything soldered
Vf–meter connected. Do not bring too much of solder on the
on it. Then, you solder the NCP1200 (DIP8 or SO,
joints to be in same final industrial conditions (for instance
depending on your selection) directly on the copper (please,
wave soldering). Now, bring a DC source to pin8, normal
without a socket). Once this is done, we need to find a
polarity, that is to say, pin8 positive by respect to ground.
Temperature Sensitive Parameter (TSP) to evaluate the
Figure 16 shows the wiring diagram for best understanding
junction temperature inside the package. One of the internal
where an ampere–meter has been inserted. Immerse all the
ESD zener diode represents a good choice. Before using it,
1200 PCB test fixture into an hermetic oven and select the
we must calibrate it. Several solutions exist but the easiest
ambient temperature at let’s say 40°C. Turn the DC power
one is to take a multi–meter in diode position offering
supply on and start to increase the voltage. At a certain
sufficient resolution (3 or 4 digits are ok) and current
moment, the DSS turns on and the ampere–meter indicates
stability during the measurement. The Agilent HP34401A
a current. Increase the voltage until you reach a power value
can be a possible selection. The ESD diode connected to
of 300 mW roughly (V_in x I_in). Leave everything cooking
pin1 can be used but another one could also be wired, e.g. the
for a while, until the Vf reading stabilizes. You will note that
current sense pin. Now, bias it in forward mode by
the current goes down a bit because of the DSS thermal
connecting probe + to the ground and probe – to pin 1. At an
effect (actually self–protective). After time has elapsed,
ambient of 25°C, you should read something like Vf ≈ 720 mV.
suppose that you read Vf = 652 mV and Ptotal = 280 mW.
The rest of the operation requires a precisely controlled
From Figure 15, we extract the corresponding junction
heater to calibrate our junction. Put the NCP1200 under the
temperature given by our calibrated TSP: 652 mV → Tj ≈
heater’s bell and measure the Vf at different points, e.g.
75°C. From these numbers, we are able to calculate our
every 10°C. At every step, wait at least a few minutes that
thermal resistance junction–to–ambient resistor by:
the reading stabilizes before recording the point. If
everything goes well, you should obtain a linear graph as Tj
Tamb
R
J
A 
Figure 15 shows. Ptotal

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 AND8069/D

which turns to be 125°C/W. A few remarks concerning the ranging from a few hundred of mW up to 100 W or more!
measure: The above design ideas will let you implement the solution
• Use a well temperature–controlled oven. Failure to best adapted to your application. The limiting factor is
stabilize the temperature in a quiet environment will actually the power switch and the 1200 driving capability. In
engender large errors. the simplest application schematic (no aux. winding) with
• Wait that the part has stopped its temperature excursion the DSS working and a 3 A MOSFET featuring low gate
before taking the Vf point. DIP8 packages require charge, we have successfully built a 70 W universal mains
longer time than SO–8. application board exhibiting 81% efficiency at low line and
87% at high line. Associating an auxiliary winding and a
“What Power Level Can I Expect from the NCP1200?” single or dual bipolar stage (as described in the data sheet)
The NCP1200 being a general purpose current–mode will let you drive the MOSFET of your choice, e.g. a 10 A
controller, you can virtually use it in any applications device, reducing the conduction losses and the heatsink size.

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EBNCP1200/D

How to Use the Spreadsheet

NCP1200 Discont.xls"
By Hector NG
ON Semiconductor Singapore
Application Engineer
Email: hector.ng@onsemi.com http://onsemi.com

ENGINEERING BULLETIN

This short note describes the necessary steps to efficiently use the NCP1200 design aid file: “NCP1200 Discont.xls”.

Symbol Cell in Spreadsheet Explanation Remarks

Vmax B4 Maximum AC Input Voltage in volt
Vmin B5 Minimum AC Input Voltage in volt
Fline B6 AC Line Frequency in Hz
Vo B11 Output Voltage in volt
Io B12 Maximum Output Current in ampere
h B13 Efficiency in % Assume 80% if unknown
Vbd B14 Power MOSFET breakdown voltage in volt
Vd B16 Diode voltage drop in volt Assume 1.0 V if an ultra–fast diode is used
or 0.8 V if a Schottky diode is used

Step 1: Input System Parameters Step 4: Enter Current Density Allowed for the
The first step in power supply design is to understand the Transformer
system requirements. The following parameters have to be The wire size of a transformer has to be chosen suitably
entered into the spreadsheet. to avoid excessive copper loss and heat dissipation. The
current density of the wire selected should be in the range
Step 2: Enter Capacitance of Input Filter Capacitor Cin of 3 ~ 5 A/mm2 for natural cooling system and current
Enter the capacitance value of the input filter capacitor density can be increased to 4 ~ 7 A/mm2 for fan cooled
into cell B39 in mF. A recommended capacitance value is system. This value should be entered into cell B55.
shown in cell B38.
Step 5: Determine Maximum Wire Size
Step 3: Determine Primary Inductance Select the maximum wire size for the transformer in the
A list box is shown in the spreadsheet which labelled as list box in cell G53. The program will limit itself in
“Selected Device” – Cell G12. Choose a device which you choosing which wire size for primary and secondary
plan to use from the list. NCP1200 is offered in 40 KHz, winding with this information.
60 KHz and 100 KHz versions. Then the user can set the
primary inductance by inputting a value in cell B32. A Step 6: Enter Flux Density Safety Factor
recommended Lp is shown in cell B31 for the user Flux density safety factor determines the magnetizing
reference. Depending on the application, the choice of Lp level of the transformer core, it should in the range from 0.3
can have a significant noise impact during NCP1200 skip to 0.5 Tesla. Enter this value in cell B58.
cycle operation. Low Lp implies high peak currents (with
possible noise problems in standby) while a high Lp Step 7: Enter Bobbin Usage Factor
implies low peak current (less noise problems) but possibly In a transformer bobbin, not all cross sectional area is
a higher leakage inductance. A trade–off has thus to be available to accommodate the windings. A bobbin usage
found between all the design requirements. factor is introduced to account for area occupied by margin,
insulation tape and waste space between wires. It should be
in the range from 0.3 to 0.5. Enter this value in cell B59.

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

January, 2001 – Rev. 0 EBNCP1200/D
 EBNCP1200/D

Step 8: Enter Magnetic Core and Bobbin Data without excessive hysteresis loss, e.g. N67 from Epcos
Before we can proceed further, we must have the (Siemens) and PC40 from TDK. The worksheet allows user
information of different magnetic cores and bobbins ready. to input properties of 5 material simultaneously. From the
Recommended core types are EE, EI, EF and ETD made of data book of the magnetics, locate the following date and
material that can work in the selected switching frequency enter into cell B61 to F64.

Symbol Cell in Spreadsheet Explanation Remarks

Core B61–F61 Name of the magnetic core Optional data, not for calculation
Name For identification purpose only
Ae B62–F62 Effective area of the magnetic core in mm2 Property of the magnetic core
Bsat B63–F63 Saturation magnetic flux density at 25oC in Tesla Property of the magnetic material
Aw B64–F64 Bobbin window area in mm2 Property of the bobbin, some vendors provide
several bobbins for one magnetic core

Step 9: Enter RDS(on) of the Power MOSFET room for transient response. Ideally Dmax should be kept
The spreadsheet provides additional information on at 40% to 60% so that there is reasonable balance on
maximum conduction loss of the power MOSFET. Enter primary and secondary ripple current. Decrease Lp if
maximum RDS(on) (usually @Tj = 100°C) of the selected Dmax is too high.
power MOSFET in cell B34, maximum conduction loss is b. Maximum voltage across power switch circuit,
shown in cell B35. Vpwr_sw(max):
Make sure that this value (cell B23) does not exceed
Step 10: Determine the Sensing Resistor power MOSFET breakdown voltage. Decrease Lp if
It is normal for a transformer to have 10% tolerance in its Vpwr_sw(max) is too high. In fact, we must have
primary inductance. Enter the percentage tolerance in cell headroom to cater for voltage spike generated by the
B82. The spreadsheet uses the lowest primary inductance leakage inductance of the transformer.
and lowest switching frequency to compute worst case c. Magnetic flux density during start–up, Binit:
primary peak current. Maximum allowable sensing To avoid magnetic saturation during start–up, Binit (cell
resistance is calculated based on this information and it is B88) should be kept below 70% of Bsat. If Binit is too
shown in cell B86. Select a sensing resistor with value high, first attempt to reduce Binit should be by increasing
lower than B86 and enter into B87. Please pick a value the value of the sensing resistor Rsense. If Rsense is
within the E24 series for easier selection: 0.56 Ω, 0.68 Ω, already very close to its allowable maximum value, try
0.82 Ω, 1.0 Ω, 1.2 Ω, 1.5 Ω, 1.8 Ω, 2.2 Ω, 2.7 Ω, 3.3 Ω, 3.9 Ω, lowering the value of flux density safety factor (cell
4.7 Ω. B58). This may force you to change to a bigger magnetic
core.
Step 11: Final Review
Before finalizing on the design, one has to review the Step 12: Reading Results
calculation results. Results are summarized in the Results page. Select
a. Maximum turn on duty, Dmax: magnetic core/bobbin set to use by list box in cell G6. User
Dmax (cell B25) should be kept below the maximum turn should take note whether cell C11 is showing “OK” or “not
on duty of NCP1200. Referring to NCP1200 data sheet, OK”. Cell showing “OK” implies that the corresponding
typical D(max) is at 80%. However, it is not realistic to magnetic core/bobbin set is big enough to accommodate all
push Dmax to the limit of the control IC because the windings. The information is for reference only, consult
secondary peak current will be very high and there is no your transformer vendor for a conclusive answer.

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 NCP1200 versus UC384X
Feature NCP1200 UC384X

Thanks to the Dynamic Self Supply

feature (DSS):

• No need of power resistors at startup • Need of Power resistors at startup.

IC supply • In operating mode: No need of auxiliary • In operating mode: need of auxiliary

winding + rectifying diode winding + rectifying diode + capacitor

⇒ Cost effective ⇒ Additional cost

⇒ PCB space saving ⇒ PCB space consuming
⇒ Increase of Efficiency ⇒ Useless power dissipation
⇒ Reliability issues

Internally Fixed at 40 kHz, 60 kHz and Externally fixed by a resistor and a

100 kHz capacitor
Switching
⇒ Cost effective ⇒ Additional cost
frequency ⇒ PCB space saving ⇒ PCB space consuming
⇒ Reliability issues

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 NCP1200 versus UC384X
Feature NCP1200 UC384X
Built–in Frequency Jittering for Lower External components (resistor + capacitor)
EMI. needed to slow down MOSFET switching-on
in order to lower EMI.
EMI
behavior ⇒ Cost effective ⇒ Additional cost
⇒ PCB space saving ⇒ PCB room consuming
⇒ Increase of Efficiency ⇒ Lower efficiency
Internal Output Short–Circuit Cycle-by-cycle current limiting:
Protection:
Dedicated overload detection circuitry. With low voltage outputs, IC may not s ee the
Once activated, this circuitry imposes to overload ⇒ ext ra components are needed:
deliver pulses in a burst manner with a fuse or transistors to monitor feedback level.
low duty–cycle.
Safety,
Fault ⇒ Cost effective ⇒ Additional cost
conditions ⇒ PCB space saving ⇒ PCB space consuming
⇒ Auto-recovery ⇒ No auto-recovery
⇒ Predictable behavior

Internal Temperature Shutdown No Internal Temperature Shutdown

Fault condition will not destroy the IC Fault condition can destroy the IC

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 NCP1200 versus UC384X

Feature NCP1200 UC384X

Skipping Cycle Mode No Skipping Cycle Mode
(Automatic Standby Mode): (NO Standby Mode):
NCP1200 automatically skips switching IC is not designed to work in Burst
cycles when output power demand mode. Extra components are needed
drops below a given level. to achieve it.
No load,
⇒ Energy Saving ⇒ Energy waste
Standby Mode ⇒ Cost effective ⇒ Additional cost
behavior ⇒ PCB space saving ⇒ PCB space consuming
⇒ High efficiency ⇒ Low efficiency (start-up resistors will
⇒ Adjustable level always dissipate and waste power)
⇒ No acoustic noise (low peak current) ⇒ Possible acoustic noise
⇒ Predictable behavior ⇒ Reliability issues

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NCP1200PAK/D