M Tech ECE (VLSI)

UNIT-1

ANALOG IC DESIGN
ECVM 503

Prof. Manoj Kumar

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 Device Structure and Operation
• Figure shows general structure of the n-
channel enhancement-type MOSFET

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view,
(b) cross-section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the
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thickness of the oxide layer (tox) is in the range of 1 to 10nm.
 two n-type doped
regions (drain, source)
Device Structure and Operation
layer of SiO2 separates
source and drain

metal, placed on top of

SiO2, forms gate
electrode

one p-type doped region

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view,
(b) cross-section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the
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thickness of the oxide layer (tox) is in the range of 1 to 10nm.
 Device Structure and Operation
• The name MOSFET is derived • The device is composed of
from its physical structure. two pn-junctions, however
• However, many MOSFET’s do they maintain reverse
not actually use any “metal”, biasing at all times.
polysilicon is used instead.
– Drain will always be at
– “This” has no effect on positive voltage with
modeling / operation as
respect to source.
described here.
• We will not consider
• Another name for MOSFET is
insulated gate FET, or IGFET. conduction of current in this
manner.

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 Operation with Zero Gate Voltage
• With zero voltage applied to
gate, two back-to-back
diodes exist in series
between drain and source.
• “They” prevent current
conduction from drain to
source when a voltage vDS is
applied.
– yielding very high
resistance (1012ohms)

Figure : Physical structure…

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 Creating a Channel for
Current Flow
• Q: What happens if (1) source
and drain are grounded and (2)
positive voltage is applied to
gate? Refer to figure to right.
– step #1: vGS is applied to the
gate terminal, causing a
positive build up of positive
charge along metal electrode.
– step #2: This “build up”
causes free holes to be
repelled from region of p-
type substrate under gate.
Figure : The enhancement-type NMOS
transistor with a positive voltage applied to
the gate. An n channel is induced at the top of
the substrate beneath the gate 28
Q: What happens if (1) source and drain are grounded and (2) positive voltage
is applied to gate? Refer to figure to right.

• step #3: This “migration”

results in the uncovering of
negative bound charges,
originally neutralized by the
free holes
• step #4: The positive gate
voltage also attracts
electrons from the n+
source and drain regions
into the channel.
Figure : The enhancement-type NMOS
transistor with a positive voltage applied to
the gate. An n channel is induced at the top of
the substrate beneath the gate 29
Q: What happens if (1) source and drain are grounded and (2) positive voltage
is applied to gate? Refer to figure to right.
this induced channel is
also known as an
• step #5: Once a sufficient inversion layer
number of “these”
electrons accumulate, an n-
region is created…
– …connecting the source
and drain regions
• step #6: This provides path
for current flow between D
and S.

Figure : The enhancement-type NMOS

transistor with a positive voltage applied to
the gate. An n channel is induced at the top of
the substrate beneath the gate 30
 Vtn is used for n-type
Creating a Channel for MOSFET, Vtp is used for
p-channel
Current Flow
• threshold voltage (Vt) – is the • effective / overdrive voltage – is
minimum value of vGS required to the difference between vGS
form a conducting channel applied and Vt.
between drain and source
• field-effect – when positive vGS is
applied, an electric field develops (eq5.1) vOV  vGS  Vt
• oxide capacitance (Cox) – is the
between the gate electrode and capacitance of the parallel plate
induced n-channel – the capacitor per unit gate area
conductivity of this channel is (F/m2)
affected by the strength of field
– SiO2 layer acts as dielectric
 ox is permittivity of SiO2 3.45E11 F / m 
tox is thickness of SiO2 layer

 ox
(eq5.3) C ox  in F / m2
tox
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 Creating a Channel for
Current Flow
• Q: What is main requirement for
n-channel to form?
• Q: How can one express the
– A: The voltage across the magnitude of electron charge
“oxide” layer must exceed Vt. contained in the channel?
• For example, when vDS = 0… – A: See below…
– the voltage at every point
W and L represent width and length of channel respectively
along channel is zero
(eq5.2) Q  C ox WL  vOV in C
– the voltage across the oxide
layer is uniform and equal to
vGS • Q: What is effect of vOV on n-
channel?
– A: As vOV grows, so does the
depth of the n-channel as well
as its conductivity.

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equation (5.14) as vGS increases, so do the (1) saturation current
and (2) beginning of the saturation region

Figure 5.13: The iD – vDS characteristics for an enhancement-type NMOS transistor

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 kn is known as NMOS-FET
transconductance parameter
and is defined as mnCoxW/L

1/rDS

low resistance, high vOV

high resistance, low vOV

Figure 5.4: The iD-vDS characteristics of the MOSFET in Figure 5.3.
when the voltage applied between drain and source VDS is kept small.
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 saturation occurs
once vDS > vOV

 W
 triode:  m n C ox   v OV  2 vDS  vDS
1
if vDS  vOV
(eq5.14) iD   L in A
 saturation: 1  mnC ox  W vO2 V otherwise
 2 L 46
 The p-Channel MOSFET

• PMOS technology originally dominated the MOS field

(over NMOS). However, as manufacturing difficulties
associated with NMOS were solved, “they” took over
• Q: Why is NMOS advantageous over PMOS?
– A: Because electron mobility mn is 2 – 4 times greater
than hole mobility mp.
• complementary MOS (CMOS) technology – is
technology which allows fabrication of both N and PMOS
transistors on a single chip.
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 Finite Output Resistance in Saturation
• In previous section, we assume (in saturation) iD is
independent of vDS.
• Therefore, a change DvDS causes no change in iD.
– This implies that the incremental resistance RS is
infinite.
– It is based on the idealization that, once the n-channel
is pinched off, changes in vDS will have no effect on iD.
– The problem is that, in practice, this is not completely
true.

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 Finite Output Resistance in Saturation

• Q: What effect will increased vDS have on n-channel

once pinch-off has occurred?
– A: It will cause the pinch-off point to move slightly
away from the drain & create new depletion region.
– A: Voltage across the (now shorter) channel will
remain at (vOV).
– A: However, the additional voltage applied at vDS will
be seen across the “new” depletion region.

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 this is the most important
Finite Output Resistance in Saturation
point here

• Q: What effect will increased vDS have on n-channel

once pinch-off has occurred?
– A: This voltage accelerates electrons as they reach
the drain end, and sweep them across the “new”
depletion region.
– A: However, at the same time, the length of the n-
channel will decrease.
• Known as channel length modulation.

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 Finite Output Resistance in Saturation

• Q: How do we account for “this

effect” in iD? Figure 5.16: Increasing vDS beyond vDSsat causes the
– A: Refer to (5.23). channel pinch-off point to move slightly away from
the drain, thus reducing the effective channel
length by DL
valid when vDS vOV

1 W 2
(eq5.17) iD   mnCox  vOV in A
2 L
1 W 2
(eq5.23) iD   mnC ox  vOV 1  vDS  in A
2 L
valid when vDS vOV
– A: Addition of finite output
resistance (ro).
Figure 5.18: Large-Signal Equivalent Model of the
n-channel MOSFET in saturation, incorporating the
output resistance ro. The output resistance
models the linear dependence of iD on vDS and is
given by (5.23) 51
 Finite Output Resistance in Saturation

• Q: What is ? .
– A: A device parameter with
the units of V -1, the value of
which depends on
manufacturer’s design and
manufacturing process.
• much larger for newer tech’s
• Figure 5.17 demonstrates the
effect of channel length
modulation on vDS-iD curves Figure 5.17: Effect of vDS on iD in the
– In short, we can draw a saturation region. The MOSFET
straight line between VA and parameter VA depends on the process
saturation. technology and, for a given process, is
proportional to the channel length L.

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 SPICE
• SPICE is a powerful general purpose analog circuit
simulator that is used to verify circuit designs and
to predict the circuit behavior.
• This is of particular importance for integrated
circuits. It was for this reason that SPICE was
originally developed at the Electronics Research
Laboratory of the University of California,
Berkeley (1975), as its name implies:
• Simulation Program for Integrated Circuits
Emphasis.
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SPICE can do several types of circuit analyses. Here are the
most important ones:

• Non-linear DC analysis: calculates the DC transfer curve.

• Non-linear transient analysis: calculates the voltage and current as
a function of time when a large signal is applied.
• Linear AC Analysis: calculates the output as a function of
frequency.
• Noise analysis
• Sensitivity analysis
• Distortion analysis
• Fourier analysis: calculates and plots the frequency spectrum.
• Monte Carlo Analysis

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SPICE

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The circuit can contain the following components:

• Independent and dependent voltage and current sources

• Resistors
• Capacitors
• Inductors
• Mutual inductors
• Transmission lines
• Operational amplifiers
• Switches
• Diodes
• Bipolar transistors
• MOS transistors
• JFET
• MESFET
• Digital gates

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A SPICE input file, called source file, consists of
three parts.
• Data statements: description of the
components and the interconnections.
• Control statements: tells SPICE what type of
analysis to perform on the circuit.
• Output statements: specifies what outputs are
to be printed or plotted.

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One can also use the following scale factors:

T(= 1E12 or 10+12); G(= E9); MEG(= E6); K(=

E3); M(= E-3); U(= E-6); N(= E-9); P(= E-12),
and F(= E-15)
Both upper and lower case letters are allowed in
PSpice and Hspice (SPICE uses only uppercase
characters)

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Independent DC Sources
• Voltage source:
Vname N1 N2 Type Value Current source: Iname N1
N2 Type Value

• N1 is the positive terminal nodeN2 is the negative

terminal node Type can be DC, AC or TRAN,
depending on the type of analysis (see Control
Statements)Value gives the value of the source
The name of a voltage and current source must
start with V and I, respectively.
• Examples: Vin 2 0 DC 10 Is 3 4 DC 1.5

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• Resistors
Rname N1 N2 Value

• Capacitors (C) and Inductors (L)

Cname N1 N2 Value <IC>
Lname N1 N2 Value <IC>
N1 is the positive node
N2 is the negative node.
IC is the initial condition (DC voltage or current).
The symbol < > means that the field is optional. If
not specified, it is assumed to be zero. In case of
an inductor, the current flows from N1 to N2.

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Pulse
• Vname N1 N2 PULSE(V1 V2 TD Tr Tf PW Period)
• V1 - initial voltage; V2 - peak voltage; TD - initial delay
time; Tr - rise time; Tf - fall time; pwf - pulse-wise; and
Period - period.
MOSFETS
Mname ND NG NS NB ModName &ltL=VAL> &ltW=VAL>
&ltAD=VAL> &ltAS=VAL> &ltPD=VAL> &ltPS=VAL>
&ltNRD=VAL> &ltOFF> &ltIC=VDS.VGS.VBS>

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Level 1 model

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Short Channel effects

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• Surface scattering occurs when electrons are
accelerated toward the surface by the vertical
component of the electric field and due to its
reduction in mobility. The electrons are attracted
by the positive Gate field; They keep bouncing
and crashing against the oxide surface.

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 Velocity Saturation
• Velocity saturation is a phenomenon that occurs
in short-channel MOS transistors, significantly
deviating from the behavior predicted by
traditional transistor models. In MOS transistors,
carrier velocity is typically assumed to be
proportional to the electrical field, independent
of the field’s magnitude.
• However, at high field strengths, such as those
found in short-channel devices, carriers no
longer adhere to this linear model due to
scattering effects during their movement.

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In short-channel MOS transistors, the carriers
reach a critical velocity, or saturation velocity,
beyond which they cannot accelerate further
due to collisions.
This saturation velocity is approximately 105 m/s
for electrons in p-type silicon. Consequently,
short-channel MOS transistors can easily reach
this saturation point with only a few volts
between the drain and source.

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 Impact of Velocity Saturation on
Transistor Behavior
It leads to the following effects:
• Reduced Saturation Voltage: In short-channel devices, the
transistor can enter saturation before the drain-source
voltage (VDS) reaches the value of VGS – VT (threshold
voltage). This extends the saturation region, and these
devices tend to operate more frequently in saturation
conditions.
• Linear Dependence on VGS: Unlike long-channel devices,
where drain current (ID) has a squared dependence on VGS,
short-channel devices show a linear dependence. This
means that for a given control voltage, short-channel
transistors deliver less current than their long-channel
counterparts. 139
• Channel Shortening Effect: As VDS increases, a
larger portion of the channel becomes velocity-
saturated, effectively shortening the channel.
• Additionally, mobility degradation is another
effect in short-channel MOS transistors. It
reduces surface carrier mobility compared to
bulk mobility due to the vertical electric field
from the gate voltage. This effect further inhibits
channel carrier mobility.

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 Hot Carrier Effects and Impact
Ionization
• As channel lengths reduce, the lateral electric field
increases, if applied voltages remain the same. This causes
carriers flowing along the channel to gain energy and
become “hot”.
• The hot carriers can cause impact ionization, which
produces extra hole electron pairs. This produces extra
drain current, and also a substrate current consisting of
the ionization-generated holes which flow towards the
substrate, the most negative point in the transistor.
• The hot carriers may also gain sufficient energy to
surmount the potential barrier at the silicon-insulator
interface, and get injected into the insulator. These effects
are shown schematically in Fig

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 Hot Carrier Effects
• Due to the high electric field in the channel,
electrons, which constitute the drain current in
nchannel transistors, can get hot.
• If some of these electrons get sufficiently heated
up – more than the 3.1 eV barrier Фox between
silicon and silicon dioxide conduction bands –
and also have their momentum directed
towards the interface, then these electrons can
get injected into the insulator.

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• Furthermore, some of the holes created by
impact ionization may also get heated up and be
injected into insulator (though this process is
more difficult for holes than for electrons, given
the larger 4.9 eV barrier for holes at the Si/SiO2
interface).
• The holes and electrons flowing into the
insulator cause several problems, including
electron and hole trapping, interface state
generation, and generation of bulk and “border”
traps in the insulator. These phenomena,
collectively called “hot carrier effects”, and pose
an important reliability issue for MOSFETs.

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• Some of the deleterious effects caused by hot
carrier effects on MOSFET performance
include: threshold voltage shift, decrease in
transconductance, excess leakage currents,
instabilities and excess noise.

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