Course Roadmap

High-Level Language (SYSC 2006)

Towards the Software 2

Towards the Hardware SYSC 3006 Assembly Language

Computer Instruction Set Architecture 3
Organization Micro-architecture
Assumes prerequisite knowledge from
Towards the Hardware 1 We are here!
ELEC 2607 and SYSC 2006
Logic Circuits (ELEC 2607)

Fall 2105 SYSC 2006

Computer System

Sept. 23, 2015 ELEC 2607 2

Goal: Computer System Towards the Hardware

Want to understand how a computer works at the Build up some circuits to explain how a computer
hardware/software interface works at the hardware/software interface
Hardware components: Processor, Main Memory, Major attractions along the road (~200 slides!):
Input / Output (I/O), Interconnection Bus Recall ELEC 2607 material: gates, state machines
• Especially the Adder/Subtracter lab!! ALU
Memory: read and write binary values
Main Input/Output
Processor
Memory I/O External Processor Datapath: execute an instruction
Devices
Microarchitecture: fetch instruction from
memory and execute using datapath SYSC 2006
Interconnection Bus
Computer System

ELEC 2607
Sept. 23, 2015 3 Sept. 23, 2015 4

About the Circuits in this Course Upwards!

This course uses simple circuits to introduce how a Basic Circuits (mostly review of 2607)
computer operates at the hardware/software interface Logic gates, interconnect gates using bus
The simple circuits show “operational concepts” Tri-State Buffer NEW
Real implementations probably use different circuits Flip Flops + Tristate Output Main
Processor I/O
The circuits are abstractions that ignore many realistic Memory

Finite State Machines Interconnection Bus

practical electrical issues (e.g. voltages and currents)
You may study more realistic (practical) circuits in Memory: read and write binary values Worry about I/O later!
other courses (like ELEC 3500) worry about Processor Datapath: execute an instruction
practical electrical issues there
Microarchitecture: fetch instruction from memory
Here, we want to understand how a computer works and execute using datapath SYSC 2006
logically at the hardware/software interface ☺
Computer System

Sept. 23, 2015 5 Sept. 23, 2015 ELEC 2607 6

 Recall from ELEC 2607 How Are Logic Gates Built?
(see 2607 course notes on 3006 website) (see 2607 course notes on 3006 website) NOT Gate
Digital circuits are based on logic levels: 0 and 1, Lo and Hi (Inverter)
A few transistors driven in saturation
Abstract: actual voltage level is “not important” +V
Act like switches (either open or closed)
Logic gates: AND, OR, XOR, NOT (inverter) Out R2

AND
Symbols, functionality truth tables Assume: 0 V = Lo, +V = Hi A T
R1

Combinational Circuits: If A is at 0 V (Lo) “switch” T is open

OR
Multiplexer, Demultiplexer, Decoder Out is at +V (Hi)
+V

Describe using truth tables A

Out R2

D Flip-flops: clocked Memory! XOR If A is at +V (Hi) “switch” T is closed T

Finite state machines: clocked, asynchronous Out is at 0 V (Lo) A Out

Moore: outputs based on state (only) NOT Logically: Out = NOT(A) A Out
Mealy: outputs based on state & inputs
Describe using state tables
Binary values 0 and 1 can be used Lo (0) Hi (1)

instead of Lo and Hi Hi (1) Lo (0)

Sept. 23, 2015 7 Sept. 23, 2015 8

AND Gate AND Gate

+V
Logic Gates Are Abstract
What are the transistors made of, and how big are
Assume: 0 V = Lo, +V = Hi A T1
R1
they? What value is +V? How much current flows?
If B is at 0 V (Lo) “switch” T2 is open
B T2 Do electrical characteristics matter so much when the
Out is at 0 V (Lo) R1

Out abstraction is focused on logical behaviour?

If A is at +V (Hi) “switch” T1 is closed R2

Out depends on state of T2 A Abstraction is essential without it we couldn’t

Out
If both A and B at +V (Hi) B
engineer anything! (too many details)
A B Out
Both “switches” closed Out at +V (Hi) The circuits we will consider often have 10’s of
0 0 0
If either A or B at 0 V (Lo) 0 1 0
1000’s of transistors
No connection to +V Out at 0 V (Lo) 1 0 0 • Will gate-level representations be feasible? [NO!]
1 1 1 – MUST work at more abstract (block) level
Logically: Out = A AND B
Sept. 23, 2015 9 Sept. 23, 2015 10
other gates are just as simple!

Decoder: Combinatorial Circuit Connecting Gates

Example of a combinatorial circuit Connect the terminals on gates using wires
Current outputs depend only on current inputs Sometimes use a BUS when connecting sets of
A decoder activates a unique output selected by a terminals
combination of inputs Simple Form: A bus is an abstraction of a set wires
Truth Table for a simple 2-to-4 binary decoder: that are used to transmit related signals
IN1 IN0 OUT3 OUT2 OUT1 OUT0 n = number of wires in the bus
n also defines the bus width
0 0 0 0 0 1 Decoder
0 1 0 0 1 0 OUT3 0
1 IN1 OUT2 1
1 0 0 1 0 0 0 IN0 OUT1 0 wires
OUT0 0
1 1 1 0 0 0
If n == 1 single wire “bus”??
number of wires in this “bus” is usually omitted
Block-level abstraction
Sept. 23, 2015 11 Sept. 23, 2015 12
 Tri-State Hi-Z
NEW! Not introduced in 2607
Tri-State Buffer
Two electrical states (0 and 1, Hi and Lo) are needed for Three terminal device: inputs A and E, output B
logic circuits that always assert their outputs
Always force each output to either 0 or 1
E Switch is open Switch is closed
ELEC 2607 considered this type of circuit when E = 0 when E = 1
A 3rd electrical state is useful for saving power and E E
simplifying the use of a bus to integrate circuits A B A B A B
High impedance state: Hi-Z
When a device holds a pin in Hi-Z state: A (input) E (enable) B (output)
• Pin is passive 0 0 Hi-Z (floating)
• Pin is (logically) disconnected from device circuit 1 0 Hi-Z (floating)
• Pin is “floating” … Does not assert any signal 0 1 0
• Pin does not influence anything connected externally 1 1 1
to the pin
Sept. 23, 2015 13 Sept. 23, 2015 14

Bus-Wide Tri-State Buffer Tristate Connections to a Bus

Assert all n outputs through a single n-bit buffer A B C
Single control input (E) for all n outputs n n n

E EA EB EC
E
n n A0 B0
Bus
...

inputs outputs n
E
An-1 Bn-1 ED EE
n n
E = 1: n outputs = n inputs D E
E = 0: n outputs = Hi-Z (floating) How to get values at A to E? from C to D and E? can A go to D while B go to E?

Use a 5-bit value to control all enable signals at once

E.G. If EA EB EC ED EE = 0 1 0 1 0 net result?
Sept. 23, 2015 15 Sept. 23, 2015 16

Circuits that Remember 1-bit Data Latch

(as in 2607, but will add tri-state outputs)
Sequential circuits (e.g. state machines) relied on some
D flip flop: “remember” last input
way to store information about the past for use in the
Trailing (falling) edge triggered
future
On falling clock edge, value at D input is stored in latch
Introduced flip flops:
Put flip flop in a “known state” store 0 or 1 D flip flop with Clock Enable
Stays stable over time remembers Only sense clock when CE = 1 CE

Non-persistent: remembering requires power to Ignore clock when CE = 0

stay applied can’t remember if power is removed
D flip flop with Clock Enable and Output Enable (NEW)
• “power on” state may be unknown OE = 0: Q floating (Hi-Z) OE

… could be 0 or 1 OE = 1: Q asserted = stored value (0 or 1)

Sept. 23, 2015 17 Sept. 23, 2015 18
 Finite State Machine (FSM) What?
(as in 2607)
Sequential circuits: sequence of states Ever seen this before?
Change state during operation over time clock Outputs
Current Comb.
Inputs Next Logic
Need to remember “current state” Comb. Logic
State
State
(flip flops)
Use flip flops to “remember” current state
Feedback !!
Use combinatorial logic to decide next state based
on inputs and current state YES!!!
Outputs
clock Comb.
Inputs Current Logic From 2607
Next
Comb. Logic State Course Notes
State (flip flops)
Feedback !!

Sept. 23, 2015 19 Sept. 23, 2015 20

Moore vs. Mealy FSM: State Table

Moore: outputs based on state (only) Specify the FSM behaviour in a State Table
Comb. Outputs
Inputs Current Logic
Use the current inputs and current state to specify
Next
Comb. Logic
State
State the next state and the current outputs
(flip flops)
Feedback !!
E.G.: Up/Down Counter (2607 Course Notes)
Inputs = Up/Down selector and count trigger (clock)
Mealy: outputs based on state and inputs
Comb. Outputs
Moore or
Inputs Current Logic
Next Mealy state
Comb. Logic State
State (flip flops) machine?

Feedback !!

Later … will build a Mealy Control FSM! …

Sept. 23, 2015 21 Sept. 23, 2015 22

Implementation from State Table Onwards and Upwards!

State Table has the essential information Basic Circuits (mostly review of 2607)
Abstract: many possible implementations! Processor
Main
I/O
Goal: Memory Worry about I/O later!
In 2607: elaborate procedure going Interconnection Bus

to K-Maps and then circuits of gates Memory: read and write binary values
to generate next state inputs to flip n-bit word
flops and outputs Bank of addressable n-bit words
In 3006: Processor Datapath: execute an instruction
Will use State Tables to specify FSM behaviour Microarchitecture: fetch instruction from memory
Will use a different implementation approach and execute using datapath SYSC 2006

• Simpler(?) ROM-based implementation (Lab1!) ☺ Computer System

Sept. 23, 2015 23 Sept. 23, 2015 ELEC 2607 24

 Why Start with Memory? Memory
Memory is “simple” compared to Processor Important features of RAM (Random Access Memory):
Computer systems need several forms of memory A collection of “words” fixed size memory elements
A word can store (remember) a digital value
“Main” Memory: holds Instructions and Data
• e.g. program variable’s data value
Need to Read Instructions and Read and Write Data! Can Write (store) value into a memory word
Processor has some built-in memory registers (later!) • Writing a value overwrites previously stored value
Can Read currently stored value from a memory word
SYSC 2006
• Reading does not change the stored value
Main
Goal: Processor
Memory
I/O Computer System For now: Notes will use memory to imply RAM memory
Interconnection Bus
ELEC 2607 Later: will deal with Read-Only Memory (ROM) too
• Especially in Lab 1 and Control FSM design later!

Sept. 23, 2015 25 Sept. 23, 2015 26

n-bit Data Latch: Circuit 1 Want to build up to:

Clock Enable
Output Enable
(with Clock Enable and Output Enable) A Memory Bank of n-bit Words
(CE)
Clock (OE) Bank: A set of n-bit data latches + some circuitry
Read?
OE
Each individual word in bank supports data operations:
D0 OE
Q0 Write: loads (stores) an n-bit value into a word
n-bit Data
Read: outputs the n-bit value stored in a word
Latch
n
...

n n-bit Word
D Q

Bank of n-bit
OE words
Dn – 1 Qn – 1
n-bit Word

CE
Sept. 23, 2015 27 Sept. 23, 2015 28
Write?

Want to Get to This Abstraction:

Access to Words in Memory Bank
Bank of 8 x n-bit Words
Want to access each word individually
Operation Read Clock
Need to access only one word at a time
to perform Write
Will use a unique binary value as an identifier to select
the word in the bank to be involved in an operation W R CLK
The address of the word m
Bank of n-bit
Address Bus

Selects word m Am-1

Need: Words
…

used in
Address bus to the bank to identify specific word in operation
A0
Data
operation Dn-1 … D0
n-bit Data bus to move data to/from the bank
some control signals for data operations n
Read, Write, Clock n
Data Bus
Recall: a bus is just a bundle of wires
Data used in operation
Sept. 23, 2015 29 Sept. 23, 2015 Build up circuits to realize the bank … 30
 Addressing Sub-Circuit for Read Sub-Circuit for
A Bank of 8 x n-bit Words A Bank of 8 x n-bit Words
Need 8 unique addresses (each word has unique address)
Use Word Select signal (from decoder) AND Read
Each digital signal has 2 possible values: 0 or 1 control signal to enable the outputs
recall: 8 = 23 (000, 001, 010, 011 … , 111)
Read Control Signal n-bit data
Need 3 digital signals to encode 8 unique addresses latch
A word’s address is its unique binary name! 7
Word Address
Each address must select a unique word (n-bit data latch) Word Select Signal
e.g. input = 1012 5
OE
1
Recall a simple Decoder: 0 Decoder
Word Select (outputs): 1 Word “at”
7 0 Address
Address signals (input): 0 Unique output selected n
n
select unique output 5 1 by encoded input is set 0 D 1012 Q
1 0
e.g. input = 1012 0 Decoder to 1
1 0
activates output 5 0 (all other outputs = 0) NOTE: the address is not “saved” anywhere … it selects
Recall: 1012 = 510 0 the decoder output that is wired to a particular word! CE
0 0
Sept. 23, 2015 31 Sept. 23, 2015 32

Write Sub-Circuit for Circuit 2:

A Bank of 8 x n-bit Words n-bit Word = latch + Read/Write Logic
Read Control Signal R n-bit Word
Use Word Select Signal (from decoder) AND Write
Control Signal to enable clock sensing
Word Select Signal WS
Latch data on falling clock edge OE (from address decoder) OE
Word at n-bit Data
7 n Address Latch
Word Address n
e.g. input = 0012 D 0012 Q D Q
0 NOTE:
0 Decoder
1 Clock Clock CLK Can’t Read
1 CE CE and Write to
0 Word Select Signal Write Control Signal W word at the
Write Control Signal same time!
n-bit data n
n-bit Data Bus Data
latch Why?
Sept. 23, 2015 33 Sept. 23, 2015 34

Circuit 3: Circuit 3 Block-Level Abstraction:

Bank of 8 x n-bit Words Bank of 8 x n-bit Words
Clock Read Clock
Write
Write
CLK W

WS n-bit Word 7 W R CLK … as an abstract

3 7
3
Address Bus

R Data representation, how is

Address Bus

3 A2
A1 8 x n-bit Words this different from the
Decoder
A0 previous slide?
CLK W
Data
WS n-bit Word 0 Dn-1 … D0
0
R Data
n
n n
Read
n
n Data Data Bus
Data Bus

Sept. 23, 2015 Abstract representation … next … 35 Sept. 23, 2015 36

 Abstraction Abstraction and Engineering
An abstraction (intentionally) ignores some details in Could a complex system be built if all of the details must be
order to focus on others addressed before anything can be understood?
Engineers routinely use abstractions to communicate
Example: the previous slide shows an abstraction of the
8 x n-bit Words circuit • Ignore details that are not relevant and focus on
aspects that are relevant (in the communication)
Ignores the low-level details of how the circuit is
Pearce’s Observation: People usually feel comfortable
implemented
working with an abstraction when they understand at least
Focuses on higher-level details needed to understand one way that the abstraction might be implemented
behaviour in terms of the signals at the boundary of no magic!
the circuit
Are you comfortable working with the abstraction of a bank
These types of abstractions are used routinely! of words or do you need to see the implementation details?

Sept. 23, 2015 37 Sept. 23, 2015 38

Students and Abstraction Larger Bank of n-bit Words?

Students typically “learn” in a bottom-up style that builds What would have to change? (logically)
abstractions on top of lower–level details, and then omits Size of address bus
the lower-level details
As was done in developing the bank of words abstraction • m-bit address bus address (max.) 2m words
Engineering design often requires a top-down approach Size of decoder
where abstractions are designed and used before • m inputs 2m outputs
implementations are designed
Number of word circuits
An abstraction is often the starting place for a design
This is a skill that comes through practice and experience • 2m word circuits
with knowing what a reasonable abstraction might be Example: 1024 x n-bit words m = ? 1 Kibi Ki !!
A 4-year Eng. education provides some initial practice Example: 4 Ki x n-bit words m = ?
and experience … which will continue in your career
Example: 1 Mi x n-bit words m = ?
Sept. 23, 2015 39 Sept. 23, 2015 Memorize powers of 2 up to 210 ! 40

Kibi ?? Circuit 4: 2m x n-bit Words

103 and 210 are often called “1K” (or 1k) Read Clock

But 1000 ≠ 1024 (close, but not the same) Write

W R CLK
Sometimes it is obvious which interpretation is m
2m x n-bit Can this abstraction
Address Bus

implied (e.g. salary, resistance, memory size) m Am-1

be understood
Words
…

A
When necessary to be exact: A0 without revisiting
Dn-1 … D0 the internal details?
Use 1K for 103 (1000) D

Use 1 Kibi (Kilo binary) for 210 (1024)

Similarly: Mebi, Gibi, Tebi, Pebi, Exbi, Yobi n
n
Data Bus

Sept. 23, 2015 41 Sept. 23, 2015 42

 Recap on Words Onwards and Upwards!
Basic Circuits (mostly review of 2607)
Each word has a unique address associated with it
Main
No two words have the same address Goal: Processor
Memory
I/O
Worry about I/O later!
Interconnection Bus

A word’s address is determined by how the circuit Memory: read and write binary values
decodes an address value to select a particular word
Processor Datapath: execute an instruction
There is a data value stored in a word
ALU
Called the contents of the word
Processor & Datapath
A word contains the last value written into the word
Put the Pieces Together! Execute an instruction!
Reading a word obtains the contents of the word
Microarchitecture: fetch instruction from memory
Multiple words may have the same contents (value) and execute using datapath SYSC 2006
Size of contents is not related to size of address
Computer System

Sept. 23, 2015 43 Sept. 23, 2015 ELEC 2607 44

Processor 1 ALU
(introduced in 2607)
A computing engine that manipulates binary values A computer uses an Arithmetic and Logic Unit (ALU)
The binary values represent (encoded) information to manipulate (binary) data values
Processor E.G. ADD, SUB, OR, AND, NOT
Registers Recall that ELEC 2607 included a lab that involved
2
Control FSM
2607 and Lab 1 ?

(memory words)3006
designing a simple ALU: 3-bit Adder/Subtracter
Internal Buses 3006 X (3 bits)
1
1 = subtract Sum (4 bits) switch = 0 Y+X
ALU Adder/Subtracter
2607 ?
0 = add switch = 1 Y–X
1 0

Interconnection Bus … later! Y (3 bits)

X, Y & Sum 2’s complement binary numbers!
Sept. 23, 2015 45 Sept. 23, 2015 46

Recall Some Features of Using Binary Values to Represent

Adder/Subtracter Information
Binary vs. decimal values Logic gates in the ALU manipulate binary signals
2’s complement values Want ALU to manipulate information relevant to our
program
Calculating 2’s complement of a value
Therefore, program must represent (encode)
Addition and subtraction
information using binary values
Sign extension
In 2607: used binary values to represent signed and
Result (Sum) has more bits than inputs (X, Y) unsigned integer values
Carry (off-end) vs. Overflow In 2006: needed to represent other kinds of info too
Half adder, Full adder, Multi-bit (carry ripple) adder E.G. floating point (ECOR 2606?), boolean, char
Operation Selector: Add or Subtract
Sept. 23, 2015 47 Sept. 23, 2015 48
 Represent Information Binary Values are Awkward
using Binary Values People working with binary values prone to errors!
Too many digits … too easy to make mistakes
Use hexadecimal representation when convenient
Inside a computer system: ALL information must be Use hexadecimal as a shorthand for binary
represented using binary values Hex digits (base 16) =
Because it is a digital system! { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F }
In the shorthand: 1 hex digit represents 4 binary digits
When discussing the binary values that represent 016 00002 416 01002 816 10002 C16 11002
information, must be aware of the information that is 116 00012 516 01012 916 10012 D16 11012 Memorize
being represented 216 00102 616 01102 A16 10102 E16 11102 these!
E.G. unsigned integer, signed integer, char, … etc. 316 00112 716 01112 B16 10112 F16 11112

Sept. 23, 2015 49 Sept. 23, 2015 50

Larger Values Identifying the Base

Sequence of binary digits multiple hex digits What is the value of the number 10 ?
10000011011101111000110101001000111 Hex digits?
Depends what base the digits have been written in!
102 = two10 1010 = ten10 1016 = sixteen10 = 100002
Partition binary value into 4-bit groups start at least
Could use subscripts to clarify base, but awkward to type
significant bit (rightmost bit)
Will use prefix to clarify:
10 0001 1011 1001 1100 0110 1010 0100 0111
0b binary 0x hexadecimal
May add leading zeros to complete leftmost bit-group 0b10 vs. 0x10 decimal values?
0010 0001 1011 1001 1100 0110 1010 0100 0111 From previous slide:
Map to appropriate hex digits 0b10000011011101111000110101001000111
0010 0001 1011 1001 1100 0110 1010 0100 0111 0x21B9C6A47 or 0x 2 1B 9C 6A 47 to be more readable
2 1 B 9 C 6 A 4 7 Will assume that no prefix implies decimal
Use reverse approach for hex to binary! E.G. 2015 and 10
Sept. 23, 2015 51 Sept. 23, 2015 52

Some Common Information Common Sizes of Binary Values

Encodings Used in Computers Used in (Modern) Computer Systems
(Raw) Binary values 4 bits: nybble
Signed & Unsigned Integers A hex digit encodes a nybble
BCD: Binary Coded Decimal 8 bits: byte
ASCII: characters 2 nybbles Hi nybble and Lo nybble
IEEE Floating Point (IEEE 754)
Includes a standard mapping between floating
point and binary values
Single & double precision
Beyond this course (ECOR 2606 ?)

Sept. 23, 2015 53 Sept. 23, 2015 54

 Binary vs. Decimal Values Max / Min Values
Represent n-digit (unsigned) integer value: dn-1dn-2 … d2d1d0
Once the size of a binary value (number of bits) is fixed
Decimal digit di contributes to represented value based on power there are limits to the set of values that can be
of 10 it represents (10i) times its value (d)
represented
E.G. d2d1d0 21610 = 2 x 102 + 1 x 101 + 6 x 100
If n bits: n-bit binary values can be used to represent (at
Can generalize: n-1
most) 2n possible values
represented value10 = Σ
di x 10i
If n-bit binary value represents unsigned integer value:
i=0
n-bit binary value: bn-1bn-2bn-3 … b2b1b0 bit = binary digit Minimum value = 0
If represents unsigned integer value, bit bi contributes to the Maximum value = 2n – 1
value based on power of 2 it represents (2i) times its value (0 or 1) • Used one value to represent 0, so only 2n – 1 left
n-1 E.G. if n = 8, max value = 28 – 1 = 25510 (1111 11112)
represented value10 = Σ
i=0
bi x 2i 1101 10002?
Why are the number of bits “fixed” in an ALU?
Sept. 23, 2015 55 Sept. 23, 2015 56

3-bit Carry Ripple Adder

(Raw) Binary Addition
(from ELEC 2607)
Carried out in same general way as decimal addition
Carry In A B Carry Out A+B
A B Carry A B
0 0 0 0 0 A B Carry A B Carry Carry
In In
0 0 1 0 1 In In
0 1 0 0 1
0 1 1 1 0 (1-bit)
(1-bit) (1-bit) (1-bit)
Full Adder
1 0 0 0 1 Full Adder Full Adder Full Adder
1 0 1 1 0
1 1 0 1 0 Carry Carry
A+B Carry Carry A+B
1 1 1 1 1 Out A+B A+B
Out Out Out

2607: built Ripple-Carry adder circuit

Raw? Based on binary number system …
Not concerned about what the binary value might represent
Sept. 23, 2015 57 Sept. 23, 2015 58

Carry vs. Overflow Signed Integer Values

When performing a raw binary addition, a “carry” value Signed integer values include: positive, negative and 0
is always generated could be 0 or 1 0 is neither positive or negative!
Regardless of what the binary value represents! Represent non-negative values same way as unsigned
When the n-bit values being added represent unsigned values (“non-negative” = 0 and positive values)
integers, a carry out of the most significant bit (2607: Need some way to represent negative values
off-end carry) means the result is too big to represent Use 2’s complement encoding
using an n-bit value Non-negative values are encoded as before
Result is bigger than 2n – 1 Negative values are encoded differently!
Overflow! Result cannot be represented using the Negation operation (negate: taking 2’s comp. of a value)
encoding scheme and size of the inputs must be consistent across the encoding
In this case, overflows the n-bit representation of I.E. Taking the 2’s comp. of the representation for +1
unsigned integer values should give the representation for – 1
Why are the number of bits “fixed” in an ALU add operation?? • And vice versa!
Sept. 23, 2015 59 Sept. 23, 2015 60
 Taking 2’s Complement of a Value Taking 2’s Complement of a Value
1. Invert all of the bits 1. Invert all of the bits
2. Add 1 2. Add 1
E.G. 8-bit value + 1 = 0000 0001 Consistent? Negate(– 1)? i.e. – (– 1)
Negate (+1) E.G. 8-bit value – 1 = 1111 1111 Negate(– 1)
invert all bits 1111 1110
add 1 + 1 invert all bits 0000 0000
1111 1111  –1 add 1 + 1
0000 0001  + 1

Sept. 23, 2015 61 Sept. 23, 2015 62

Max / Min Values Sign and Sign Extension

If n bits: n-bit binary values can be used to represent The most significant bit (msb) indicates the sign of a 2’s
(at most) 2n possible values complement encoded signed integer value
If n-bit binary value represents signed integer value: msb = 0: non-negative (could be 0!! Is 0 positive?)
Use one value to represent 0, so 2n – 1 left msb = 1: negative
• Can’t split these equally between positive and Adding more leading (significant) bits = sign bit
negative use sign bit to differentiate! (extending the sign) does not change the value
Maximum (positive) value = 2n – 1 – 1 How many
positive values? E.G. 5 vs. 00000005 … same for 2’s comp. negative
Minimum (negative) value = – 2n – 1 Negative values?
Can form larger binary representations from smaller
E.G. if n = 8, 8 – 1
max value = 2 – 1 = 12710 when needed by sign extension
max value = – 28 – 1 = – 12810

Sept. 23, 2015 63 Sept. 23, 2015 64

Addition Subtraction Trick from

Subtraction: X – Y = X + (– Y) ELEC 2607!
Performed as raw binary addition
Works for both unsigned and (2’s comp) signed Negate Y and add ! (no need to “subtract”! ☺)
representation E.G. 2 – 1 = 2 + (– 1) [see previous slide!] ☺
E.G. Signed values: (+ 2) + (– 1) Works for signed integers
+2 0000 0010 Careful with this approach for unsigned integers!
+ –1 1111 1111 E.G. 1 – 2 … cannot represent result as
= + 1 1 0000 0001 1 (carry 1) unsigned integer!
Is there overflow in this example? 1 – 2 = 1 + (– 2) 0000 0001 1
For signed integers, carry ≠ overflow !!!! unsigned?
+ 1111 1110 – 2
0 1111 1111 255 (– 1) ?
Sept. 23, 2015 65 Sept. 23, 2015 66
 An n-bit ALU with 2m Operations 2m Operations? (this is the OPR Slide)
n n Suppose m = 4, 24 = 16 operations … the first 8 might be:
X Y
2 n-bit data inputs: X and Y m ALU Operation Effect Opr
OP
1 n-bit data output: R (Result) NOP Do nothing 0000
VC R
n ADD R=X+Y 0001
1-bit Carry indicator: C SUB R=X–Y 0010 More
1-bit Overflow indicator: V RY R=Y 0011 operations
bitwise AND R = X AND Y 0100 will be
m-bit operation selector: OP added
bitwise OR R = X OR Y 0101
later!
In ELEC 2607 lab: n = 3, m = 1 (21 = 2 operations) bitwise XOR R=X⊕Y 0110
No signed overflow indicator! bitwise NOTY R = invert(Y) 0111

Later (Lab 2): add more flag outputs from ALU Could you build circuits for each of the operations? Then could you
Carry, oVerflow, Zero, Negative design an ALU circuit that uses Opr signals to select which
operation circuit to use (hints: decoder, tri-state buffers)? Lab 2 ☺
Sept. 23, 2015 67 Sept. 23, 2015 68

2
Putting the Pieces Together A Simple Processing System
Processor

ELEC SYSC Registers

2607 3006 Control FSM (memory words)

X Y

Let’s go! ALU

R = X Opr Y

Sept. 23, 2015 69 Sept. 23, 2015 70

Simple Processing System Clock

A Simple Processing System CLK
Registers (bank of memory words) 16 x 32-bit words Addr 4
Use ALU to perform operations on values stored in registers Address Bus A 16 x 32-bit Words
(memory words in Processor) WordR R
WordW CLK
Ignore C and V output of ALU for now ! W
Store operation results in registers Data
Complete operation involves multiple values from registers 32
Control FSM

• e.g. R = X + Y 3 data values! (X, Y, R) 32-bit Data Bus

T1
Can only access one memory word at a time need 3 steps! T1CE
CE D T = Temporary (T1 and T2)
T1OE 32-bit Latch
Need extra Data Latches (T1 & T2) to hold values temporarily OE Q 32
Use a Finite State Machine (FSM) to sequence the steps and to 32
generate control signals for: X
ALU
Y
Use OP values
Transfer data to/from register bank OP 32 from OPR slide
Opr 4
Manage use of temporary registers (T1 & T2) VC R

Perform ALU operations T2CE

CE D
Use system-wide Clock to synchronize and advance the FSM state T2OE 32-bit Latch
OE Q
Sept. 23, 2015 71 Sept. 23, 2015 T2 72
 Control FSM Control FSM
Controls the system Sequence of 3 execution states Will describe FSM using a table, with columns for:
Clock used to change states (on rising edge ) (Current) State, Outputs, Next State
• Write into registers on falling edge! Outputs: Addr: 4 bits: select a memory word
FSM outputs are held constant while in a state WordR, WordW: read/write word
Change only when new state is entered T1OE, T1CE: control T1 data latch
T2OE, T2CE: control T2 data latch
Execution Execution Execution
State E0 State E1 State E2 Opr: 4 bits: ALU operation

14 output bits!
Outputs Outputs Outputs
while in E0 while in E1 while in E2
Sept. 23, 2015 73 Sept. 23, 2015 74
Recall Clock-driven FSM’s from ELEC 2607!

W4  W1 + W7 state E0 Clock
Example: W4  W1 + W7 CLK

Add the values stored in word 1 and word 7, and store Addr 4
Address Bus A 16 x 32-bit Words
the result in word 4 WordR R
WordW word 1 CLK
Involves 3 data values each must go on the Data W
Data
Bus separately! 32
Control FSM

Recall: (OPR slide) ADD = 0001 Data Bus

T1
Must sequence the steps in the operation: T1CE
CE D
word 1
T = Temporary (T1 and T2)
T1OE OE Q 32
E0: Read W1 onto Data Bus and Write value into T1 32
X Y
E1: Read W7 onto Data Bus, perform addition, Write ALU 32
NOP
OP
result into T2 (since W7 value is on Data Bus) Opr 4
VC R

E2: Read T2 onto Data Bus and Write value into W4 T2CE
CE D
T2OE 32-bit Latch
OE Q
Sept. 23, 2015 75 Sept. 23, 2015 T2 76

W4  W1 + W7 state E1 Clock W4  W1 + W7 state E2 Clock

CLK CLK

Addr 4 Addr 4
Address Bus A 16 x 32-bit Words Address Bus A 16 x 32-bit Words
WordR R WordR R
WordW word 7 CLK WordW word 4 CLK
W W
Data Data
32 32
Control FSM

Control FSM

Data Bus Data Bus

T1 T1
T1CE D T = Temporary (T1 and T2) T1CE D T = Temporary (T1 and T2)
CE CE
T1OE word 1 T1OE word 1
OE Q 32 OE Q 32
32 32
X Y X Y
ALU 32 ALU 32
ADD NOP
OP OP
Opr 4 Opr 4
VC R VC R
T2CE T2CE
CE D CE D
T2OE w1 + w7 T2OE w1 + w7
OE Q OE Q
Sept. 23, 2015 T2 77 Sept. 23, 2015 T2 78
 State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next
Control FSM Transitions & Outputs E0 State
E0 0001 1 0 1 0 0 0 NOP E1
W4  W1 + W7 Recall: (OPR slide) ADD = 0001
E0: Read W1 onto Data Bus and Write value into T1 Read W1 onto Data Bus and Write value into T1
E1: Read W7 onto Data Bus, perform addition, Write Clock
State E0 S1 S2
result into T2 (since W7 value is on Data Bus)
Addr 0001 111 100
E2: Read T2 onto Data Bus and Write value into W4 Data Bus contents of word 1 word 7 word 1 + word 7

State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next WordR
(4) (4) State WordW into W4
E0 0001 1 0 1 0 0 0 NOP E1
T1CE into T1
E1 0111 1 0 0 1 1 0 ADD E2
T1OE
E2 0100 0 1 0 0 0 1 NOP –
T2CE into R2
Could you design an FSM to implement this?
T2OE
Consider activity in each state …
Opr NOP 0000
Sept. 23, 2015 79 Sept. 23, 2015 ADD x 80

State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next
State Clock E1 State
E0
CLK
E0 0001 1 0 1 0 0 0 NOP E1 E1 0111 1 0 0 1 1 0 ADD E2
CLK
Addr 4
Address Bus 0001 A
Read W7 onto Data Bus, perform addition, Write
16 x 32-bit Words
WordR R result into T2 (since W7 value is on Data Bus)
WordW word 1 CLK
W
Clock
Data State E0 E1 S2
32 Enter E0 on rising edge Addr 0001 0111 100
Control FSM

Data Bus word 1 of clock Data Bus contents of word 1 contents of word 7 word 1 + word 7
T1
T1CE D WordR
CE
T1OE word 1
OE Q 32 WordW into W4
32
X Y
Contents of word 1 is put T1CE into T1
ALU on Data Bus “immediately”
NOP 32 T1OE
Opr
OP so it can be latched in T1
(0000) 4 VCR on falling clock edge T2CE into T2
T2CE T2OE
CE D
T2OE 32-bit Latch
OE Q
Stay in E0 until next rising Opr NOP ADD 0001
Sept. 23, 2015 T2 81 Sept. 23, 2015 x 82
clock edge then go to E1

State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next
State Clock State
E1 E2
CLK
E1 0111 1 0 0 1 1 0 ADD E2 E2 0100 0 1 0 0 0 1 NOP –
CLK Addr
4
Address Bus 0111 A 16 x 32-bit Words Read T2 onto Data Bus and Write value into W4
WordR R
WordW word 7 CLK
W
Clock
Data State E0 E1 E2
32 Contents of word 7 is put on Addr 0001 0111 0100
Control FSM

Data Bus word 7 Data Bus “immediately” &

T1 Data Bus contents of word 1 contents of word 7 word 1 + word 7
word 1 is output from T1
T1CE D WordR
CE “immediately” so they both
T1OE word 1
OE Q can be used in ADD
32 WordW into W4
32
X Y T1CE into T1
ALU Addition is performed in
OP 32 first half of clock cycle so T1OE
Opr = ADD (0001) 4 result can be latched in
VCR T2CE into T2
T2CE T2 on falling clock edge
CE D T2OE
T2OE w1 + w7 Opr
OE Q NOP ADD NOP
T2 Stay in E1 until next
Sept. 23, 2015 83 Sept. 23, 2015 84
rising clock edge
 State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next
State Clock
E2
CLK
E2 0100 0 1 0 0 0 1 NOP –
Whhaaaattt? Do it again
“Putting the Pieces
CLK Addr Together”
4
Address Bus 0100 A 16 x 32-bit Words
WordR R
WordW word 4 CLK
W
Data
32
Control FSM

Data Bus w1 + w7
T1
T1CE D
CE
T1OE word 1
OE Q 32
32
The result from T2 is put on
Data Bus “immediately” so
X Y
ALU it can be latched into word 4
NOP 32 on falling clock edge
OP
Opr (0000) 4 VCR
T2CE
CE D
T2OE w1 + w7
OE Q
Sept. 23, 2015 T2 85 Sept. 23, 2015 86

Recap: FSM for an Operation

<image removed> E0: copy 1st source word from register to T1
E1: (i) present 1st source word (T1) and 2nd source word
(from register) to ALU,
(ii) perform ALU operation
(iii) store result in T2
E2: copy result to destination word

Execution Execution Execution

State E0 State E1 State E2

Outputs Outputs Outputs

Sept. 23, 2015 87 Sept. 23, 2015 while in E0 while in E1 while in E2 88

Other Word Operations W3  W0 + W5 W4  W1+W7

Most of the ALU operations involve 3 data values What would change in the FSM table from before?
2 source values (operands)
E0: Read W1 W0 onto Data Bus and Write value into T1
1 destination value (result)
NOTY and RY only involve 2 data values (1 source, 1 E1: Read W7 W5 onto Data Bus, perform addition,
destination) Write result into T2
What use is RY ???? E2: Read T2 onto Data Bus and Write value into W4 W3
Does no manipulation of any data?
Could use to copy a value from one register to another! State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next
State
Copy source word to T2 first (using RY), then copy to
E0 0001 1 0 1 0 0 0 NOP E1
destination word 0000
• Still uses the Data Bus twice! discussed more later! E1 0111 1 0 0 1 1 0 ADD E2
Exercise: develop FSM tables for the other operations 0101
E2 0100 0 1 0 0 0 1 NOP –
Sept. 23, 2015 89
0011
Sept. 23, 2015 90
 W3  W0 – W5 W3  W0 + W5
W3  W5
W3  W0 – W 5
What would change in the FSM table on previous slide? Copy word 5 to word 3
E0: Read W0 onto Data Bus and Write value into T1 What would change in the FSM table on previous slide?
E1: Read W5 onto Data Bus, perform addition E0: Read W0 onto Data Bus and Write value into T1
subtraction (OPR = 0010), Write result into T2 E1: Read W5 onto Data Bus, perform subtraction RY
E2: Read T2 onto Data Bus and Write value into W3 (OPR = 0011), Write result into T2
E2: Read T2 onto Data Bus and Write value into W3
State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next
State State Addr WordR WordW T1CE T1OE T2CE T2OE Opr Next
State
E0 0000 1 0 1 0 0 0 NOP E1
E0 0000 1 0 1 0 0 0 NOP E1
E1 0101 1 0 0 1 1 0 ADD E2
SUB E1 0101 1 0 0 1 1 0 SUB E2
RY
E2 0011 0 1 0 0 0 1 NOP –
E2 0011 0 1 0 0 0 1 NOP –
Sept. 23, 2015 91 Sept. 23, 2015 92

What Are the Differences Among

An Abstraction Problem?
Operations?
Problem: A unique FSM is required for each operation!
Could the operations be generalized so that a single FSM W4  W1 + W7 Registers: Source and Destination
could drive all of them? W3  W0 + W5
Would require encoding the differences between the Operation
W3  W0 – W5
operations in a way that can be used by the FSM # of registers & Operation &
W3  W5 # of states needed
Give encoding of operation as an FSM input
Solution: store the operation-specific information in a
data latch and have a single FSM that uses the stored
information as an input (to create the right outputs)
A Problem for Later: How can the operation-specific
information be loaded into the data latch?
Sept. 23, 2015 93 Sept. 23, 2015 94

Generalizing Word Operations 16 – bit Operation Encoding

FSM tables for the operations share many similarities Operations differ in (a) the ALU operation and (b)
Each has an ALU operation to perform the specific source & destination words involved
Each has at least one source word [E1 (SY), E2 (D)] Each ALU operation can be encoded in 4 bits
• Most have 2 source words [E0 (SX), E1 (SY), E2 (D)] Each word address can be encoded in 4 bits
Each has a destination word
Identifying ALU opr & 3 (max) words involves:
Only differences are:
Whether E0 is needed (only needed if 2 source words) 4 + 4 + 4 + 4 bits = 16 bits (max)
The actual operation performed Use 16 D flip-flop latch (with CE and OE) to encode
The actual source & destination words involved operations encoding has 4 fields Least
Most 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Significant
The timing and the control of the Registers, the temporary Significant Bit (LSB)
Opcode DWord SXWord SYWord
Data Latches (T1 & T2) and ALU don’t change! Bit (MSB)
4 bits 4 bits 4 bits 4 bits Names of
opr dest. word source 1 source 2 fields
Sept. 23, 2015 95 Sept. 23, 2015
goes to T1, then ALU input X 96
 Operation Encoding Example
More Examples
W3 = W1 AND W6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode DWord SXWord SYWord
Recall field formats
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode DWord SXWord SYWord
W4  W1 + W7 ADD (0001)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1
W3 = W1 AND W6
From OPR Slide: ADD W4 W1 W7
AND = 0100
W3  W0 – W5 SUB (0010)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 0
SUB W3 W0 W5

Sept. 23, 2015 97 Sept. 23, 2015 98

What Operation is This? Software-Related Terminology

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 1 0 0 1 0 0 1 1 1 0 1 A value that is known to be the address of a word is
said to index or point to or reference that word.
If value is in a register, then the register is said to
If you can decide … then so can the processor!!
index (or point to or reference) the word.

Dword, SXWord and SYWord point to (index) the

registers used in the operation

Sept. 23, 2015 99 Sept. 23, 2015 100

Only 1 Source Word? Solved Abstraction Problem!

NOTY and RY operations have only 1 source word Problem: Previously, each operation needed a
unique Control FSM to encode each operation’s
Ignore SXWord field in encoding details
Use 16-bit words to encode operations: don’t Only some details change between operations
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 care
Opcode DWord x x x x SYWord Other details say the same for all operations!
4 bits 4 bits 4 bits 4 bits Want to encode instructions in a way that captures
To identify operations with 1 source word : the differences between instructions
Operation Opcode OneSourceOp
Encoded in a 16-bit “encoded instruction” value
o15 Output = 1 iff
(o15 o14 o13 o12)
o13 Opr has only Use encoded instruction as input to a single FSM!
RY 0 0 1 1 o12 one source FSM uses encoded input to generate correct
NOTY 0 1 1 1 word
output details for each instruction
• Mealy machine!
Sept. 23, 2015 101 Sept. 23, 2015 102
 Encoded Operation Input to FSM Extensions to FSM
Control FSM Other signals Control FSM Other signals
4 NOP encoding 4
Address Bus 0000 Address Bus
4
Select ANOP
register (assert in E0 and E2)
4
4 Opr
Opr
Select AOP (assert in E1)
operation SYW (assert in E1)
SXW (assert in E0)
OneSourceOp
DW (assert in E2)
Q15-12 4 Q11-8 4 Q7-4 4 Q3-0 4

Opcode DWord SXWord SYWord Opcode DWord SXWord SYWord

16-bit latch contains Encoded Operation 16-bit latch contains Encoded Operation
Sept. 23, 2015 103 Sept. 23, 2015 104

W3 = W1 AND W6
Encoded Operation Input to FSM NOTE ON PREVIOUS SLIDE
Control FSM Other signals
NOP encoding 4
In the Simple Processing System the registers and
0000
4
Address Bus operations involved were encoded as outputs for
ANOP
(assert in E0 and E2)
specific states
4 Each operation needed its own unique FSM!
Opr
Now: registers and operation involved are input to FSM
AOP (assert in E1)
SYW (assert in E1) and the FSM can output them
0 SXW (assert in E0)
OneSourceOp
DW (assert in E2)
They are not encoded in the FSM!
Q15-12 4 Q11-8 4 Q7-4 4 Q3-0 4
• One FSM can do many operations!

0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 0
16-bit latch contains Encoded Operation
Sept. 23, 2015 105 Sept. 23, 2015 106

Encoded Ops and Control FSM Revised FSM

FSM must now control fields of encoded info Decode state precedes the execution states
OpCode field: out to ALU via Opr during E1 OneSourceOp
• Opr = NOP in E0 and E2
Decode Execution Execution Execution
Word selection: via Address Bus during E0, E1, E2 State State E0 State E1 State E2
• But no E0 if operation has only 1 source word! OneSourceOp
Introduce new Decode state to determine if E0 is New state and signals to drive encoded fields
included in the execution of the encoded operation State SXW SYW DW AOP ANOP Other signals Next State

Use OneSourceOp circuit to decide Decode 0 0 0 0 1 no active outputs

OneSourceOp E0
OneSourceOp E1
• Feedback into FSM! Lab 3! ☺ E0 1 0 0 0 1 as before E1
E1 0 1 0 1 0 as before E2
E2 0 0 1 0 1 as before –
Sept. 23, 2015 107 Sept. 23, 2015 108
 Recall Earlier Problem Onwards and Upwards!
Basic Circuits (mostly review of 2607)
Problem: How can the operation-specific information be
loaded into the data latch? Goal: Processor
Main
Memory
I/O
Worry about I/O later!
Interconnection Bus
Solution: Load the encoded operations from main memory
locations ☺  goal of the step to microarchitecture Memory: read and write binary values
A Problem for Later: How do the encoded operations get Processor Datapath: execute an instruction
into main memory words?
The circuits introduced so far will be grouped into the Microarchitecture: fetch instruction from memory
Processor component and execute using datapath
small memory (and data latches) in the Processor SYSC 2006
component will be called registers
Computer System
Will introduce a large Main Memory component that can
hold encoded operations ELEC 2607

Sept. 23, 2015 109 Sept. 23, 2015 110

Processor + Main Memory System Interconnection Bus

Will look at the Interconnect Bus first, then Main Memory,
then the Processor
3 2

1
Interconnection Bus
Clock
IBWrite Used later Main
Processor
IBRead Used now! Memory
Processor Main Memory
32
Interconnection Address Bus
32
Interconnection Data Bus

Interconnection Bus
Sept. 23, 2015 111 Sept. 23, 2015 112

1 1

Memory Speed Interconnection Bus Protocol

Main Memory circuits are often slower than
Terminology:
Processor circuits … for a variety of reasons
Clock cycle: starts on the rising edge of the Clock signal
Creates more complex behaviour on
Interconnect Bus Continues until next rising clock edge
• Often involves handshaking signals A signal is stable while it is being asserted (held) to a
particular value
discussed in other courses (e.g. SYSC 4507)
A signal is stable in a clock cycle if it is stable during the
In this course we will assume that the memory can
entire clock cycle
respond in the same (clock) cycle that an access
request is made

Sept. 23, 2015 113 Sept. 23, 2015 114

1 1
Protocol: Memory Write Clock Cycle Protocol: Memory Read Clock Cycle
The Processor must keep the IBWrite, Address and The Processor must keep the IBRead signal stable for
Data signals stable for one clock cycle, and Main one clock cycle while keeping the Address signals stable
Memory must store the Data value on the falling for one clock cycle
edge of that cycle Main Memory must ensure that the Data value read
Memory Write Clock Cycle
from Main Memory is on the bus during the falling clock
Clock edge of that cycle Memory Read Clock Cycle
Asserted by
Processor Addr Memory Address Clock
Asserted by Asserted by
Data Data to Memory
Processor Addr Memory Address Memory
IBWrite
Data Data from Memory
Write into Main
Memory on IBRead
falling edge
Sept. 23, 2015 115 Sept. 23, 2015
? Copy into
Processor 116

2
Circuit 7: 2
Address Size?
Main Memory Component Main Memory size = 1 M words
Just a bigger memory … for now, let’s assume: Need 20 address bits!
32-bit words Interconnection Address Bus = 32 bits
1M words [1MB = 220] Use the 20 least signif. bits for the address
What about the most signif. (high) 12 bits?
1M x 32-bit Words
Will assume that IF most signif. 12 bits = 0x000
Main THEN accessing Main Memory!
Clock CLK
Memory Will assume most signif. 12 bits ≠ 0x000
IBWrite W
Address Data
IBRead R
A19…A0 D31…D0
then accessing some other component on bus I/O!
Interconnection Later: Will use most signif. 12 bits ≠ 0x000 to select I/O!
Bus ? 20 32
32 Introduce Selection signal SEL to Memory Component
Interconnection Address Bus
32 component participates in bus cycle iff SEL = 1
Interconnection Data Bus
Sept. 23, 2015 117 Sept. 23, 2015 118

2 2
Memory Mapped Access Main Memory Component with SEL
Using Memory address ranges to select components to SEL = 0 ignore Interconnect Bus Cycle
be accessed is called Memory Mapped Access
SEL = 1 participate in Interconnection Bus Cycle
Common in computer systems!
1M x 32-bit Words
In this case addresses with the most signif bits = 0x000
Main
are used to access Main Memory Clock CLK
Memory
1M words of Main Memory address range: IBWrite W
Address Data
IBRead R
SEL A19…A0 D31…D0
• 0x000 00000 Interconnection
20 32
to Bus = 0x000?

• 0x000 FFFFF 12
32 32
Interconnection Address Bus
32
Sept. 23, 2015 119 Sept. 23, 2015 Interconnection Data Bus 120
3 3
Here we go again! A Few Changes in the Design
Remember: memory words and latches in the processor
Extend Processor’s capability: are called registers distinguish from Main Memory
Read instruction from Main
words
Memory and copy into the
Instruction Register (IR) In the Processor, the WordR and WordW control
signals renamed: RegR and RegW
Some new hardware To set up for more instructions (later), will expand
circuits inside Processor. encoded operations input to FSM from 16 bits to 32 bits
Let’s go!
3 2 The encoded operations will be called instructions
1
Expand Control FSM: 32 D flip flop latch used to hold instructions
Main more states & more
Processor
Memory outputs
referred to as the Instruction Register (IR)

Interconnection Bus
Sept. 23, 2015 121 Sept. 23, 2015 122

32 – bit Instruction Encoding Example

Encode instruction operation in 8 bits W4  W1 + W7 ADD (0000 0001)
Up from 4 bits previously
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
bit 9 8 7 6 5 4 3 2 1 0
Pad previous “ALU operations” with leading 0’s 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

use Op Rd Rsx Rsy Not used (always 0) for now!

• E.G. ADD: 0000 0001
bin 00000001 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 00 0 0 0
Still allows some bits to identify operation at ALU
hex 0 1 4 1 7 0 0 0
Still use 4-bits each for register identification
Ignore any remaining bits (for now) Encoded Instruction = 0x01417000
Revised 32-bit instruction encoding:
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0

use Op Rd Rsx Rsy Not used (always 0) for now!

Sept. 23, 2015 123 Sept. 23, 2015 124

Simple Processing System: Revised and Redrawn

32-bit IR Input to FSM Control FSM Register Address Bus (4 bits)
CLK
Control FSM Other signals CLK
Address A3…A0
NOP encoding 4 16 x 32-bit Registers
0000 Address Bus RegR
4 R Data
ANOP RegW
W D31…D0
(assert in E0 and E2) 32-bit latch
4
Opr Internal Data Bus (32 bits)

AOP (assert in E1)

SYW (assert in E1) T1CE D
CE
T1OE OE T1
0 SXW (assert in E0) Q
OneSourceOp
DW (assert in E2)
X Y
Q27-24 4 Q23-20 4 Q19-16 4 Q15-12 4 ALU
OP
Opr 4
VCR
0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1 unused (all 0) T2CE D
CE
32-bit latch contains Encoded Operation T2OE T2
OE Q
Sept. 23, 2015 125 Sept. 23, 2015 126
 Processor
Towards Microarchitecture Control FSM
CLK
Register Address Bus (4 bits)

Recall goal of microarchitecture: PCOE Address A3…A0 CLK

16 x 32-bit Registers
Want to load instructions read from memory 1111 RegR
R Data
PC Addrs RegW
W D31…D0
Need to load IR from Internal Data Bus IR Q
D
CE
Will introduce IRCE signal to IR IRCE Internal Data Bus (32 bits)

Will give R15 Special Purpose: Program Counter (PC)

T1CE D
CE
Introduce new constant to encode the PC’s register T1OE OE T1
Q
address address of R15 = 11112
X Y
ALU
Introduce PCOE signal from FSM to select the constant OP
Opr 4
VCR
T2CE D
CE
T2OE T2
OE Q
Sept. 23, 2015 127 Sept. 23, 2015 128

Roles of PC and IR Instruction Load

Key roles of PC and IR in microarchitecture: The address in PC will be used in a Main Memory read
Program Counter (PC) Register contains the Main operation to obtain the instruction stored there
Memory address of the word containing the next The instruction will be copied from the Interconnection
instruction to be loaded into the Instruction Bus onto the Internal Data Bus and then written into
the IR
Register (IR)
The FSM can then execute the instruction (as done
PC points to the Main Memory word containing before!)
the next instruction The FSM must be expanded to include states to load
the instruction from Main Memory into the IR
Remember:
PC = register 15 (F) Called “fetching” the instruction
IR = encoded instruction register

Sept. 23, 2015 129 Sept. 23, 2015 130

Processor
Also Need to Adjust PC Control FSM Register Address Bus (4 bits)
CLK
To execute multiple instructions (program): After PCOE
Const1
0000000000000000 Address A3…A0 CLK
0000000000000001
loading an instruction, PC must be incremented to point C1OE
16 x 32-bit Registers
1111 RegR
to the “next” instruction R Data
PC Addrs RegW
W D31…D0
Fundamental Microarchitecture Assumption: IR Q D
CE

“next” instruction is stored in “next” sequential IRCE Internal Data Bus (32 bits)
(ascending) Main Memory word
T1CE D
Adjusting the PC is part of fetching an instruction CE
T1OE OE T1
Q
Must expand FSM to do this too!
X Y
For incrementing PC: New 32-bit constant called Const1 ALU
OP
Holds constant value 1 Opr 4
VCR
Used to adjust (increment) the PC using ALU T2CE
CE D
T2OE T2
Will select using C1OE signal from FSM OE Q
Sept. 23, 2015 131 Sept. 23, 2015 132
 Interconnection Bus Interface Interconnection Bus Interface
Some interface circuity is needed to allow the 2 new 32-bit registers (latches) added to interface with the
Processor to read an instruction from Main Memory Interconnection Data and Interconnect Address Buses
and copy the retrieved instruction onto the Internal MAR: Memory Address Register
Data Bus MDR: Memory Data Register
Need some buffering (temporary) registers for MAR: holds the address to be accessed output onto the
the instruction address and the instruction data Interconnection Address Bus
Need some control signals to request a read (and MDR: holds data exchanged on the Interconnection Data
Bus (read from Main Memory, or written to Main Memory)
later a write) operation on Main Memory
FSM will be augmented to control the new registers and
generate the IBRead and IBWrite signals on the
Interconnection Bus (in addition to RegR and RegW)

Sept. 23, 2015 133 Sept. 23, 2015 134

Processor
Control FSM Register Address Bus (4 bits) Interconnection Bus Interface Details
CLK
Const1 CLK
PCOE 0000000000000000 Address A3…A0 MAR: “easy” need to read address from Internal
0000000000000001
16 x 32-bit Registers
1111
C1OE RegR R Data Bus and output address to Interconnection Bus
PC Addrs RegW
W D31…D0
IR Q D MDR: has two sources/destinations for data
CE
IRCE Internal Data Bus (32 bits)
Details 1. Internal Data Bus
coming!
2. Interconnection Data Bus
T1CE D Interconnection
CE
T1OE OE T1
Q
Bus
MAR
Must be able to Read and Write to either bus
Interface
Must accomplish this using single MDR
X Y MDR
ALU
OP
Opr 4
C R
Interconnection Address Bus
T2CE D
CE Interconnection Data Bus
T2OE T2
OE Q
IBRead
Sept. 23, 2015 IBWrite 135 Sept. 23, 2015 136

MAR: Only need read

MDR: Must be able to
read/write from/to both buses
internal bus and output
to Interconnection Bus
Clock Cycles at External I/F
Internal Data Bus (32 bits) Both MAR and MDR share the Internal Data Bus
Must use the bus sequentially
Interconnection MDRget MARCE
MDRput CE D
Bus MAROE MAR Cycle Write (to Memory) Read (from Memory)
OE Q
Interface
1 Load MAR from Reg Load MAR from Reg
MDRCE D
CE
MDROE MDR
OE Q 2 Load MDR from Reg Memory Read Clock Cycle
IBRead
3 Memory Write Clock Cycle Save MDR to Reg
IBWrite

Interconnection Address Bus

Interconnection Data Bus

Sept. 23, 2015 137 Sept. 23, 2015 138

 1
RECALL MDR: Must be able to
MAR: Only need read
internal bus and output
read/write from/to both buses
Protocol: Memory Write Clock Cycle to Interconnection Bus
Internal Data Bus (32 bits)
The Processor must keep the IBWrite, Address and
Data signals stable for one clock cycle, and Main
Memory must store the Data value on the falling Interconnection
MDRput
MDRget MARCE
CE D
Bus MAROE MAR
edge of that cycle Interface
OE Q
Memory Write Clock Cycle
MDRCE D
CE
Clock MDROE MDR
OE Q
Asserted by IBRead
Processor Addr Memory Address Cycle Write (to Memory) IBWrite
Data Data to Memory 1 Load MAR from Reg
IBWrite 2 Load MDR from Reg Interconnection Address Bus
Write into Main
3 Memory Write Clock Interconnection Data Bus
Memory on
falling edge Cycle
Sept. 23, 2015 139 Sept. 23, 2015 140

MAR: Only need read MAR: Only need read

MDR: Must be able to MDR: Must be able to
internal bus and output internal bus and output
read/write from/to both buses read/write from/to both buses
to Interconnection Bus to Interconnection Bus
Internal Data Bus (32 bits) Internal Data Bus (32 bits)

Interconnection MDRget MARCE Interconnection MDRget MARCE

MDRput CE D MDRput CE D
Bus MAROE MAR Bus MAROE MAR
OE Q OE Q
Interface Interface
MDRCE D MDRCE D
CE CE
MDROE MDR MDROE MDR
OE Q OE Q
IBRead IBRead

Cycle Write (to Memory) IBWrite Cycle Write (to Memory) IBWrite
1 Load MAR from Reg 1 Load MAR from Reg
2 Load MDR from Reg Interconnection Address Bus 2 Load MDR from Reg Interconnection Address Bus
3 Memory Write Clock Interconnection Data Bus 3 Memory Write Clock Interconnection Data Bus
Cycle Cycle
Sept. 23, 2015 141 Sept. 23, 2015 142

1
RECALL MDR: Must be able to
MAR: Only need read
internal bus and output
read/write from/to both buses
Protocol: Memory Read Clock Cycle to Interconnection Bus
The Processor must keep the IBRead signal stable for Internal Data Bus (32 bits)

one clock cycle while keeping the Address signals stable

for one clock cycle Interconnection MDRget MARCE
MDRput CE D
Bus MAROE OE MAR
Main Memory must ensure that the Data value read Interface
Q

from Main Memory is on the bus during the falling clock

MDRCE D
edge of that cycle Memory Read Clock Cycle MDROE
CE
OE
MDR
Q
IBRead
Clock Cycle Read (from
Asserted by Asserted by IBWrite
Memory)
Processor Addr Memory Address Memory
1 Load MAR from Reg
Data Data from Memory Interconnection Address Bus
2 Memory Read
IBRead Interconnection Data Bus
Clock Cycle
Sept. 23, 2015 ? Copy into
Processor
143 3Sept. 23, 2015
Save MDR to Reg 144
 MAR: Only need read MAR: Only need read
MDR: Must be able to MDR: Must be able to
internal bus and output internal bus and output
read/write from/to both buses read/write from/to both buses
to Interconnection Bus to Interconnection Bus
Internal Data Bus (32 bits) Internal Data Bus (32 bits)

Interconnection MDRget MARCE Interconnection MDRget MARCE

MDRput CE D MDRput CE D
Bus MAROE OE MAR Bus MAROE OE MAR
Q Q
Interface Interface
MDRCE D MDRCE D
CE CE
MDROE MDR MDROE MDR
OE Q OE Q
IBRead IBRead
Cycle Read (from Cycle Read (from
IBWrite IBWrite
Memory) Memory)
1 Load MAR from Reg 1 Load MAR from Reg
Interconnection Address Bus Interconnection Address Bus
2 Memory Read 2 Memory Read
Clock Cycle Interconnection Data Bus Clock Cycle Interconnection Data Bus

3Sept. 23, 2015

Save MDR to Reg 145 3Sept. 23, 2015
Save MDR to Reg 146

Fetching an Instruction Incrementing the PC

Recall: Purpose of expanding to microarchitecture was to Programs have many instructions
allow instructions to be fetched from Main Memory and Computer must be able to fetch the instructions
stored into the Instruction Register
States in reading instruction from Main Memory: Fetch & execute them one at a time
1. F0: copy PC to MAR: MAR  PC Recall Microarchitecture Assumption: next
2. F1: Interconnection Bus Protocol: Read Clock Cycle instruction is in word at next (ascending) address
Output IBRead and MAR After reading an instruction, increment PC to point
Read Instruction into MDR to the next instruction to be fetched.
MDR  MMem( MAR ) i.e. perform the operation: PC  PC + 1
3. F2: copy MDR to IR: IR  MDR Uses ALU to increment value

Implement using FSM states!

Sept. 23, 2015 147 Sept. 23, 2015 148

Use ALU to Increment PC Value States to Increment the PC

Not part of “operation execution” states! Can’t use
Just another ALU operation … requires 3 states to
the Opcode field of the IR to generate the ADD
use the data bus 3 times:
operation code
1. PC0: copy PC to T1: T1  PC
Introduce the constant ADD operation code (0001)
into the FSM circuit 2. PC1: add PC value (from T1) with the new
constant 1 and store Result in T2: T2  T1 + 1
FSM just needs to activate the AADD signal to put
ADD operation onto the Opr signals 3. PC2: copy T2 to PC PC  T2
ADD operation code
0001
4
AADD
4
Opr

Similar to how FSM outputs NOP operation

Sept. 23, 2015 149 Sept. 23, 2015 150
 Instruction Fetch States During “Instruction Fetch”?
The microarchitecture must accomplish two things Must get instruction from memory AND increment PC
during an instruction fetch: Extend the Control FSM Number of states depends
1. Read the memory location indexed by the PC and on how much can be accomplished in each state
load the value into the IR Can the activity of reading the instruction (F0, F1, F2)
AND be overlapped with the activity of incrementing the
PC (PC0, PC1, PC2)?
2. Increment the PC to point to the next instruction
Depends on how/when the components in the
datapath are used to accomplish the fetch!
“Parallelize” activities: a major conceptual
theme in hardware and software design!!!
Sept. 23, 2015 151 Sept. 23, 2015
Parallel: Overlapping in time 152

Parallelize Adjusting PC While

What about PC2?
Reading from Memory?
F0: MAR  PC PC0: T1  PC F2: IR  MDR PC2: PC  T2
F0: Drive PC contents onto Internal Data Bus and Both use Internal Data Bus
latch into MAR can’t parallelize do F2 Fetch State 2
While PC contents on bus, could also latch into T1 Need extra Fetch State 3 for PC2? PC  T2
Parallelize PC0 and F0! Fetch State 0 No!
F1: read memory into MDR: MDR  MMem( MAR )
Parallelize PC2 with the Decode state! ☺
Does not use any other internal registers or buses
Could also perform PC + 1 addition T2  PC + 1
Why do F2 before PC2? ☺
• Drive Const1 onto Internal Data Bus, output T1,
ALU Opr = ADD, latch Result into T2
Parallelize PC1 and F1! Fetch State 1
Sept. 23, 2015 153 Sept. 23, 2015 154

Parallelized Result PC, IR and Main Memory

BEFORE Instruction Fetch Main Memory
State Instruction from Adjust PC
Memory PC
Encoded Instruction
F0 MAR  PC T1  PC IR
F1 MDR  MMem( MAR ) T2  PC + 1
F2 IR  MDR -----
AFTER Instruction Fetch Main Memory
Decode ------ PC  T2
PC
Encoded Instruction

IR Encoded Instruction

Sept. 23, 2015 155 Sept. 23, 2015 156

 Expanded FSM F0
Add the instruction Fetch States PC onto Internal Data Bus (PCOE & RegR)
Save PC in T1 (T1CE)
Fetch Fetch Fetch Load PC in MAR (MARCE)
State F0 State F1 State F2
ANOP = 1 since ALU is not involved
I
M M I
Decode MMM M B
R R A T T T T A C P D D B I
State A A D D W
e e N 1 1 2 2 A 1 C R R R R Next
(and State R R R R r Other
g g O C O C O D O O p g e C State
PC2) C O C O i
R W P E E E E D E E u e a E
OneSourceOp E E E E t
OneSourceOp t t d
E
F0 1 1 1 1 1 0 F1
Execution Execution Execution
State E0 State E1 State E2
Sept. 23, 2015 157 Sept. 23, 2015 158

Processor
Control FSM Register Address Bus (4 bits)
F0 F1 (very busy!)
CLK
MAR onto Interconnect Address Bus (MAROE)
PCOE 0000000000000000 Address A3…A0 CLK IBRead (to Main Memory, and to Interconnect Bus Interface)
0000000000000001
C1OE
16 x 32-bit Registers Read instruction into MDR (MDRCE, IBRead, falling clock)
1111 RegR R Data
PC Addrs RegW PC (R15)
Q W D31…D0 T1 (PC value) to X (T1OE) & constant 1 to Y (C1OE)
IR D
CE PC ALU: R = PC + 1 (AADD)
IRCE Internal Data Bus (32 bits) IBRead Save PC + 1 in T2 (T2CE)
IBWrite
T1CE Interconnection MARCE I
CE D M M I
T1OE OE PC Bus MAR MAROE MMM M B
Q R R A T T T T A C P D D B I
Interface = PC MDRCE A A D D W
e e N 1 1 2 2 A 1 C R R R R Next
MDROE State R R R R r Other
X Y g g O C O C O D O O p g e C State
ALU MDR MDRget C O C O i
NOP R W P E E E E D E E u e a E
MDRput E E E E t
Opr 4 OP t t d
VCR e
Interconnection Address Bus
T2CE F1 1 1 1 1 1 1 1 0 F2
CE D
T2OE T2 Interconnection Data Bus
OE Q
IBRead
Sept. 23, 2015 IBWrite 159 Sept. 23, 2015 160

Processor
Control FSM Register Address Bus (4 bits)
F1 F2
CLK
PCOE CLK
0000000000000000
0000000000000001
Address A3…A0 MDR contains instruction drive MDR onto the
16 x 32-bit Registers
1111
C1OE RegR R Data Internal Data Bus (MDROE, MDRget)
PC Addrs RegW
W D31…D0
IR Q D Load instruction into IR (IRCE)
CE
IRCE Internal Data Bus (32 bits) IBRead
ANOP = 1 since ALU is not involved
IBWrite I
MARCE M M I
T1CE D Interconnection MMM M B
CE 1 R R A T T T T A C P D D B I
T1OE OE PC Bus MAR MAROE A A D D W
Q MDRCE e e N 1 1 2 2 A 1 C R R R R Next
Interface = PC State R R R R r Other
MDROE g g O C O C O D O O p g e C State
MDR C O C O i
X Y MDRget R W P E E E E D E E u e a E
ALU = MMem( PC ) E E E E t
ADD MDRput t t d
OP e
Opr 4
VCR F2 1 1 1 1 0 Decode
Interconnection Address Bus
T2CE D
CE Interconnection Data Bus
T2OE PC + 1
OE Q
IBRead
Sept. 23, 2015 IBWrite 161 Sept. 23, 2015 162
Processor
Control FSM Register Address Bus (4 bits)
F2 Decode
CLK
PCOE CLK
0000000000000000
0000000000000001
Address A3…A0 Drive T2 (adjusted PC value) onto Internal Data Bus
16 x 32-bit Registers
1111
C1OE RegR R Data (T2OE)
PC Addrs RegW
W D31…D0
Q
MMem(PC) D
Load into PC (RegW, PCOE)
CE
IRCE Internal Data Bus (32 bits) IBRead
ANOP = 1 since ALU is not involved
IBWrite
I
T1CE Interconnection MARCE M M I
CE D MMM M B
T1OE OE T1 Bus MAROE R R A T T T T A C P D D B I
Q MAR A A D D W
Interface MDRCE e e N 1 1 2 2 A 1 C R R R R
State R R R R r Other Next State
MDROE g g O C O C O D O O p g e C
X Y MDR C O C O i
ALU MDRget R W P E E E E D E E u e a E
NOP = MMem( PC ) E E E E t
MDRput t t d
Opr 4 OP e
VCR
Interconnection Address Bus
T2CE Decode 1 1 1 1 0 ???
CE D
T2OE PC + 1 Interconnection Data Bus
OE Q
IBRead
Sept. 23, 2015 IBWrite 163 Sept. 23, 2015 164

Processor Decode
Control FSM Register Address Bus (4 bits) Repeating Mechanism
CLK
PCOE 0000000000000000 Address A3…A0 CLK Loop to get next instruction execute a program
0000000000000001
C1OE
16 x 32-bit Registers
1111 RegR R Data
PC Addrs RegW PC (R15)
Q W D31…D0
IR D Fetch Fetch Fetch
CE
State F0 State F1 State F2
IRCE Internal Data Bus (32 bits) IBRead
IBWrite
T1CE Interconnection MARCE
CE D
T1OE OE T1 Bus MAROE
Q MAR Decode
Interface MDRCE
State
MDROE
X Y (and F3)
ALU MDR MDRget
NOP MDRput OneSourceOp
OP OneSourceOp
Opr 4
VCR
Interconnection Address Bus
T2CE D Execution Execution Execution
CE Interconnection Data Bus
T2OE PC + 1 State E0 State E1 State E2
OE Q
IBRead
Sept. 23, 2015 IBWrite 165 Sept. 23, 2015 166

Resulting State Table Instruction Cycle

I
The resulting Control FSM is fundamental to
M M I
R R A T T T T A C P
M M M M
D D B
B
I
microarchitecture (and the computer system’s) operation
A A D D W
State
e e N 1 1 2 2 A 1 C
R R R R
R R R
r
R
Other
Next Called the Instruction Cycle
g g O C O C O D O O p g e C State
C O C O i Often represented as 3 stages:
R W P E E E E D E E u e a E
E E E E t
t t d
e Fetch, Decode, Execute (repeat)
F0 1 1 1 1 1 Always 0 F1
F1 1 1 1 1 1 1 1 Not F2
involved in
F2 1 1 1 1 fetching Decode
Fetch Decode Execute
Decode 1 1 1 1 Stage Stage Stage
E0 Always 0 As before
E1 As before Not involved in previous execution Later, will add some extra behaviour interrupts!
E2 states F0

Sept. 23, 2015 167 Sept. 23, 2015 168

 Example R4 = R0 AND R12 ( 0x0440C000 )
Decode
Typical midterm/final question Registers F0 F1 F2
F4
E0 E1 E2
Given initial register and memory contents, show how the R0 01
registers change value due to an instruction cycle R4 03
Often asked at two different levels: Assume all values are hexadecimal
R12 FF
1. Microarchitecture: includes all of the temporary R15 0600
registers, IR and the MDR & MAR T1
• Identify changes in every state in instruction cycle T2
2. Instruction Set Architecture: the aspects visible to MAR
programmers (no temporary registers, IR or MDR & MAR MDR
… not visible to programmers!) IR
• Just give register/memory values after instruction cycle Memory
Addrs Value
0600 0440C00
Sept. 23, 2015 169 Sept. 23, 2015 170

R4 = R0 AND R12 ( 0x0440C000 ) R4 = R0 AND R12 ( 0x0440C000 )

Decode Decode
Registers F0 F1 F2 E0 E1 E2 Registers F0 F1 F2 E0 E1 E2
F4 F4
R0 01 R0 01
R4 03 R4 03
R12 FF R12 FF
R15 0600 R15 0600
T1 0600 T1 0600
T2 T2 0601
MAR 0600 MAR 0600
MDR MDR 0440C000
IR IR
Memory Memory
Addrs Value Addrs Value
0600 0440C000 0600 0440C000
Sept. 23, 2015 171 Sept. 23, 2015 172

R4 = R0 AND R12 ( 0x0440C000 ) R4 = R0 AND R12 ( 0x0440C000 )

Decode Decode
Registers F0 F1 F2 E0 E1 E2 Registers F0 F1 F2 E0 E1 E2
F4 F4
R0 01 R0 01
R4 03 R4 03
R12 FF R12 FF
R15 0600 R15 0600 0601
T1 0600 T1 0600
T2 0601 T2 0601
MAR 0600 MAR 0600
MDR 0440C000 MDR 0440C000
IR 0440C000 IR 0440C000
Memory Memory
Addrs Value Addrs Value
0600 0440C000 0600 0440C000
Sept. 23, 2015 173 Sept. 23, 2015 174
 R4 = R0 AND R12 ( 0x0440C000 ) R4 = R0 AND R12 ( 0x0440C000 )
Decode Decode
Registers F0 F1 F2 E0 E1 E2 Registers F0 F1 F2 E0 E1 E2
F4 F4
R0 01 R0 01
R4 03 R4 03
R12 FF R12 FF
R15 0600 0601 R15 0600 0601
T1 0600 01 T1 0600 01
T2 0601 From R0 T2 0601 From R0 01
MAR 0600 MAR 0600 R0 AND R12
MDR 0440C000 MDR 0440C000
IR 0440C000 IR 0440C000
Memory Memory
Addrs Value Addrs Value
0600 0440C000 0600 0440C000
Sept. 23, 2015 175 Sept. 23, 2015 176

R4 = R0 AND R12 ( 0x0440C000 ) R4 = R0 AND R12 ( 0x0440C000 )

Decode Decode
Registers F0 F1 F2 E0 E1 E2 Registers F0 F1 F2 E0 E1 E2
F4 F4
R0 01 R0 01
R4 03 01 R4 03
What about just registers after instruction cycle? 01
R12 FF R12 FF
R15 0600 0601 R15 0600 0601
T1 0600 01 T1 0600 01
T2 0601 From R0 01 T2 0601 01
MAR 0600 R0 AND R12 MAR 0600
MDR 0440C000 MDR 0440C000
IR 0440C000 IR 0440C000
Memory Memory
Addrs Value Addrs Value
0600 0440C000 0600 0440C000
Sept. 23, 2015 177 Sept. 23, 2015 178

R4 = R0 AND R12 ( 0x0440C000 ) R4 = R0 AND R12 ( 0x0440C000 )

Just registers after instruction cycle: Just registers after instruction cycle:

Registers After Registers After

R0 01 R0 01
R4 03 R4 03 01 Obvious (?)
R12 FF R12 FF
given the
instruction
R15 0600 R15 0600 0601
Memory Memory Most likely to
be missed on
Addrs Value Addrs Value
midterm or
0600 0440C000 0600 0440C000 final

Sept. 23, 2015 179 Sept. 23, 2015 180

 Wow! Learned So Far (1)
We have arrived at the Hardware/Software interface The circuits to build computer systems are all very
Still some Hardware coming … but …. Finished simple at their lowest levels: logic gates & flip flops
what we start 175 slides ago ☺ (and tri-state buffers)
As they become larger, the logic gates “disappear”
as high-level functionality becomes more complex
Microarchitecture !!! SYSC 2006 E.G. Microarchitecture
A description at the logic gate-level would be
Computer System
incomprehensible
Must use abstractions to hide low-level details!
ELEC 2607

Sept. 23, 2015 181 Sept. 23, 2015 182

Learned So Far (2) Learned So Far (3)

Major components in a computer system: Interconnection Bus:
Processor, Main Memory, I/O and Interconnection IBRead, IBWrite, System Clock, Address and Data Buses,
Bus Read and Write Protocols
Processor: fetches & executes instructions, processes data
Registers, ALU, Data Bus, Interconnection Bus Interface,
Program Counter
Main
Processor I/O External
Memory Control FSM !!! Instruction Register (input), Mealy
Devices
Instruction Cycle (Fetch Decode Execute … repeat)
Interconnection Bus Main Memory: stores information (instructions and data)
Capacity, Addresses, Contents, Read, Write

Microarchitecture … WOW!
Sept. 23, 2015 183 Sept. 23, 2015 184