BENR 1123

LOGIC CIRCUIT (BENR 1123)

TUTORIAL 4
1. The full-adder in Figure 4.1 is tested under all input conditions with the input waveforms
shown. From your observation of the  and C out waveforms, is it operating properly,
and if not, what is the most likely fault?

Figure 4.1

2. BCD numbers are applied sequentially to the BCD-to-decimal decoder in Figure 4.2.
Draw a timing diagram, showing each output in the proper relationship with the others
and with the inputs.

Figure 4.2

3. Referring to Figure 4.3, show the input and output bits for the following 4-bit input
numbers if C0 will be connected to ground.
i) 1100 + 0101 (ii) 0001 - 0011

MSB A3 A2 A1 A0

4-bit parallel adder

C4 7483 C0

MSB B3 B2 B1 B0 S3 S2 S1 S0
Figure 4.3

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4. Use the diagram in Figure 4.4 to form an addition of the decimal number by using binary
addition. Show the input and output bits for the following 4-bit input numbers if C0 will be
connected to +5V.
i) (+5)-(+7) (ii) 1001-0101

MSB A3 A2 A1 A0

4-bit parallel adder

C4 7483 C0

S3 S2 S1 S0

MSB B3 B2 B1 B0
Figure 4.4

5. Show how three 74LS283 adders can be connected to form a 12-bit parallel adder.

6. Referring to Figure 4.5, the following are the specifications of the required decoder:
- if the input (pqr) = 000, nothing is displayed (all segments off)
- if the input = 001, the letter A is displayed
- if the input = 010, the letter B is displayed
- if the input = 011, the letter C is displayed
- if the input = 100, the letter D is displayed
- if the input = 101, the letter E is displayed
- if the input = 110, the letter F is displayed
- input = 111 is considered an invalid situation
The 7-segment display unit used is of the common-anode type (logic '0' is used to
activate a segment).
i) Build a truth table of the required decoder.
ii) Use Karnaugh maps to get the Boolean equations of segments a, b, d, e, f and g.
iii) Draw the circuit for each of the segment.

Figure 4.5

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7. Design of a decoder. The specification of the required decoder is given below:

- if the input (AB) = 00, the number 0 is displayed
- if the input = 01, the number 1 is displayed
- if the input = 10, the number 2 is displayed
- if the input = 11, the number 3 is displayed
The 7-segment display unit used is of the common-cathode type (logic '1' is used to
activate a segment).
i) Build a truth table of the required decoder.
ii) Use Karnaugh maps to get the Boolean equations of segments a, b, d, e, f and g.
iii) Draw the circuit for each of the segment.

8. Design of a Binary Encoder (with Priority). The description of the required encoder is
given below (A is MSB):

Figure 4.7
 Normal cases (if only one input is activated):
- if only A is activated (A =1), XY = 00
- if only B is activated (B =1), XY = 01
- if only C is activated (C =1), XY = 10
- if only D is activated (D =1), XY = 11
 Abnormal cases (if more than one input is activated):
- A has more priority than B, C and D
- B has more priority than C and D
- C has more priority than D
(for example, if both B and D are activated, XY = 01)
 Other (if no input is activated, XY=00)
i) Build a truth table of the required encoder.
ii) Use Karnaugh maps to get the Boolean equations.
iii) Then, implementation in all-NOR form and all-NAND form.

9. Show how the Boolean function S = B  AC may be implemented using a single 8-to-1
multiplexer. Sketch the final circuit.
10. Implement the same function as in Problem 9 using a 4-to-1 multiplexer. Sketch the final
circuit. (Assume A and B as selectors).

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11. Implement the logic function specified in Table 4.1 by using an 8 to 1 multiplexer. Draw
the final circuit.
Table 4.1
A B C Y
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

(i) Then Implement the circuit using a 4-to-1 multiplexer. Draw the final circuit.
(Assume A and B as selectors).
(ii) Referring to SOP expression for Y, implement the circuit using a 3 to 8 decoder
with one OR gate.

12. Implement the logic function specified in Table 4.2 by using an 8 to 1 multiplexer and
several basic gates. Draw the final circuit. (Assume A, B and C as selectors)
Table 4.2
A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 I
1 0 0 1 I
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

(i) Then implement the circuit using a 4-to-1 multiplexer. Draw the final circuit.
(Assume A and B as selectors).
(ii) Referring to SOP expression for X, implement the circuit using a 4 to 16 decoder
with one OR gate.

13. With refer to Figure 4.8:

(i) Write Boolean expression for X and Y as a function of the inputs A, B, C and D in
standard sum-of-product (SOP) form.
(ii) Obtain the simplified SOP expressions for X and Y using K-Map.

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Figure 4.8

14. A comparator is a digital circuit that examines the binary data on two sets of inputs.
By using a combinational logic gates, design a 2-bit comparator, which can compare
between 2 numbers as shown in Figure 4.9.

A1 F2 (A > B)
A0 combinational
F1 (A < B)
B1 logic
B0 F0 (A = B)
Figure 4.9

15. Arrange several 2-to-1 Mux to built 4-to-1 multiplexer and 8-to-1 multiplexer. Then,
design 8-to-1 multiplexer by using 2-to-1 multiplexer and 4-to-1 multiplexer.

16. Figure 4.10 shows a 2-to-1 multiplexer. Determine the Boolean expression and
analyze the output.

Figure 4.10