Experiment No.

Aim: To study and verify the Truth Tables of AND, OR, NOT, NAND, NOR, EXOR logic gates

Components: IC 7400, 7402, 7404,7408,7432,7486

Apparatus: Prototyping board (breadboard), DC Power Supply, Connecting Wires

Theory:

AND, AND, OR and NOT gates are basic gates. XOR and XNOR are universal gates.
Basically logic gates are electronic circuits because they are made up of number of electronic
devices and components. Inputs and outputs of logic gates can occur only in two levels. These
two levels are term HIGH and LOW, or TRUE and FALSE, or ON AND off, OR SIMPLY 1
AND 0. A table which lists all possible combinations of input variables and the corresponding
outputs is called a „truth table‟. It shows how the logic circuit‟s output responds to various
combinations of logic levels at the inputs.

AND GATE:-

An AND gate has two or more inputs but only one output. The output assumes the logic 1
state only when each one of its inputs is at logic 1 state. The output assumes logic 0 state even if
one of its input is at logic 0 state. AND gate is also called an „all or nothing‟ gate.

The logic symbol & truth table of two input AND gate are shown in figure 1.a & 1.b
respectively. The symbol for AND operation is „.‟.

With input variables A & B the Boolean expression for output can be written as;

X = A.B

Logic symbol: Truth table:

Input Output
1
A 3 A B X
2
X
B 0 0 0
X = AB
0 1 0

1 0 0

1 1 1

Fig.1.a Fig.1.b
 Pin diagram of IC74LS08:

OR GATE

Like an AND gate, an OR gate may have two or more inputs but only one output. The
output assumes the logic 1 state, even if one of its inputs is in logic 1 state. Its output assumes
logic 0 state, only when each one of its inputs is in logic 0 state. OR gate is also called an „any or
all‟ gate. It can also be called an inclusive OR gate because it includes the condition „both the
input can be present‟.

The logic symbol & truth table of two input OR gate are shown in figure 1.c & 1.d
respectively. The symbol for OR operation is „+‟.

With input variables A & B the Boolean expression for output can be written as;

X=A+B

Logic symbol: Truth table:

Input Output
1
A 3
2
X A B X
B
X= A+ B 0 0 0

0 1 1

1 0 1

1 1 1

Fig.1.c Fig.1.d

Pin diagram of IC74LS32:

NOT GATE

A NOT gate is also known an inverter, has only one input and only one output. It is a
device whose output is always the complement of its input. That is the output of a not gate
assumes the logic 1 state when its input is in logic 0 state and assumes the logic 0 state when its
input is in logic 1 state.

The logic symbol & truth table of NOT gate are shown in figure 1.e & 1.f respectively.
The symbol for NOT operation is „-„-‟(bar).

With input variable A the Boolean expression for output can be written as;

This is read as “X is equal to a bar”.

Logic symbol: Truth table:

Input Output

A X

0 1

1 0

Fig.1.e Fig.1.f
 Pin diagram for IC74LS04:

NAND GATE

NAND gate is universal gate. It can perform all the basic logic function. NAND means
NOT AND that is, AND output is NOTed.so NAND gate is combination of an AND gate and a
NOT gate. The output is logic 0 level, only when each of its inputs assumes a logic 1 level. For
any other combination of inputs, the output is logic 1 level. NAND gate is equivalent to a
bubbled OR gate.

The logic symbol & truth table of two input NAND gate are shown in figure 1.g & 1.h
respectively.

With input variables A & B the Boolean expression for

output can be written as;

̅̅̅̅̅

Logic symbol: Truth table:

Input Output

A 1 A B X
3
2
X
B 0 0 1

X = AB 0 1 1

1 0 1

1 1 0

Fig.1.g Fig.1.h
 Pin diagram for IC74LS00:

NOR GATE

NOR gate is universal gate. It can perform all the basic logic function. NOR means NOT
OR that is, OR output is NOTed.so NOR gate is combination of an OR gate and a NOT gate. The
output is logic 1 level, only when each of its inputs assumes a logic 0 level. For any other
combination of inputs, the output is logic 0 level. NOR gate is equivalent to a bubbled AND
gate. The logic symbol & truth table of two inputs NOR gate are shown in figure 1.i& 1.j
respectively. With input variables A & B the Boolean expression for output can be written as;

̅̅̅̅̅̅̅̅

Logic symbol: Truth table:

Input Output

A B X
A 2
1
X 0 0 1
3
B
0 1 0
X= A+ B
1 0 0

1 1 0

Fig.1.i Fig.1.j
 Pin diagram for IC74LS02:

EXCLUSIVE-OR (X-OR) GATE

An X-OR gate is a two input, one output logic circuit, whose output assumes a logic 1 state
when one and only one of its two inputs assumes a logic 1 state. Under the condition when both
the inputs are same either 0 or 1, the output assumes a logic 0 state. Since an X-OR gate
produces an output 1 only when the inputs are not equal, it is called as an anti-coincidence gate
or inequality detector. The output of an X-OR gate is the modulo sum of its two inputs. The logic
symbol & truth table of two input X-OR gate are shown in figure 1.k & 1.l respectively. The
symbol for X-OR operation is „⊕‟. With input variables A & B the Boolean expression for
output can be written as;

X= A ⊕

Logic symbol: Truth table:

Input Output

A B X
1
A 3
2
X
B 0 0 0

0 1 1
X= A ⊕
1 0 1

1 1 0

Fig.1.k Fig.1.l
 Pin diagram for IC74LS86:

Procedure:-

 Set up the breadboard.

 Test all required ICs.
 Give various combinations of inputs and check the output.
 Repeat the procedure for each IC.

Observation Table: LED ON (RED light): Logic 1

LED OFF (Green Light): Logic 0
Input variables: A, B
Output variable: Y

Sr. Input(A) Input(B) Output Output Output Output Output Output

No LED LED (OR) (AND) (OR) (NAND) (NOR) (XOR)
___ Y=AB Y=A+B ____ ______ Y=A B
Y=A Y = AB Y= A+B
1
2
3
4

Results and Analysis:

NOT Gate: When logic 1 is applied to one of NOT gate of 7404 IC, then output becomes zero.
When input LED is ON (RED), the output LED become OFF (Green) vice versa.
OR Gate: The output of an OR gate is a 1 if one or the other or both of the inputs are 1, but a 0 if
both inputs are 0. When One or the other or Both of the input LEDS are ON (RED Light), then
output LED is ON(RED) otherwise Output LED is OFF(Green Light)

AND Gate: The output of an AND gate is only 1 if both its inputs are 1. For all other possible
inputs the output is 0.When both the LEDS are On, then output LED is ON (RED Light)
otherwise Output LED is OFF.

NOR Gate: The output of the NOR gate is a 1 if both inputs are 0 but a 0 if one or the other or
both the inputs are 1.
NAND Gate: The output of the NAND gate is a 0 if both inputs are 1 but a 1 if one or the other
or both the inputs are 0.

EXOR gate: The output of the XOR gate is a 1 if either but not both inputs are 1 and a 0 if the
inputs are both 0 and both 1.

Conclusion: Any Boolean expression can be realized using NOT, AND, OR, NAND,NOR,
EXOR gates.
 Experiment No.2

Aim: - realization of logic gates using NAND and NOR gates.

Components: - IC 7400, 7402

Apparatus: - Digital trainer kit, wires, probes, etc.

Theory:-

Universal gates: -

The Nand and Nor gates are called as universal gates, because it is possible to implement any
Boolean expression with the help of only Nand or only Nor gates.

Hence a user can build any combinational circuit with the help of only Nand gates or only Nor
gates.

The NAND & NOR gates are called as „Universal gates‟. Because it is possible to
implement any Boolean expression with the help of only NAND or only NOR gate. We can
construct AND, OR, NOT, X-OR & X-NOR gates.

The Boolean expression for NAND gate is,

The Boolean expression for NOR gate is,

This is a great advantage because a user will have to make a stock of only Nand or Nor gates.

All gates using Nand Gate:-

1) Not using Nand:-

The Boolean expression for NOT gate is Fig. shows the realization of a NOT gate
using a two i/p NAND gate. As both i/p‟s are connected together we can write i/p
A=B=A
So o/p is given as
 But A.A=A by AND law

A
𝐴

2) AND using NAND:-

The Boolean expression for an AND gate is Y=A.B
Taking double inversion,
̿̿̿̿̿

But ̿
Y=A.B
This equation can be realized using only NAND gate as shown in fig.

A
A.B
B

3) OR using NAND:-
The Boolean expression for an OR gate is Y=A + B
Taking double inversion,
̿̿̿̿̿̿̿
But by DE-Morgan‟s theorem
̅̅̅̅̅̅̅ ̅ ̅
̅̅̅̅̅
̅ ̅
This is required expression for OR gate

A+B

B
4) NOR using NAND:-
The Boolean expression for an NOR gate is ̅̅̅̅̅̅̅̅̅

But by DE-Morgan‟s theorem

̅̅̅̅̅̅̅ ̅ ̅
̅ ̅
Taking double inversion,
̿̿̿̿̿
̅ ̅
This is required expression for NOR gate
A

̅̅̅̅̅̅

B
5) Ex-OR using NAND:-
The expression for Ex- OR gate is
⊕
̅ ̅
Taking double inversion
̿̿̿̿̿̿̿̿̿̿̿̿̿̿
̅ ̅
Let ̅ =X and ̅ =Z

=̿̿̿̿̿̿̿
i g e g he e
̅̅̅̅̅̅̅ ̅ ̅
̅̅̅̅̅
̅ ̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅
̅ ̅̅̅̅̅̅̅̅
̅̅̅
 This is required expression for Ex-OR gate using NAND gate.

̅ ̅

All gates using NOR Gate:-

1) Not using NOR:-

The Boolean expression for NOT gate is Fig. shows the realization of a NOT gate
using a two i/p NOR gate. As both i/p‟s are connected together we can write i/p A=B=A
So o/p is given as

But A+A=A by OR law

A ̅

2) OR using NOR:-
The Boolean expression for an OR gate is Y=A+B
Taking double inversion,
̿̿̿̿̿̿̿

But ̿
Y=A+B
 This equation can be realized using only NAND gate as shown in fig.

A A+B

3) AND using NOR:-

The Boolean expression for an AND gate is Y=A.B
Taking double inversion,
̿̿̿̿̿
But by DE-Morgan‟s theorem
̅̅̅̅̅ ̅ ̅
̅̅̅̅̅̅̅
̅ ̅
This is required expression for AND gate

A.B

4) NAND using NOR:-

The Boolean expression for an NOR gate is ̅̅̅̅̅̅

But by DE-Morgan‟s theorem

̅̅̅̅̅ ̅ ̅
̅ ̅
Taking double inversion,
̿̿̿̿̿̿̿
̅ ̅
This is required expression for NAND gate
 A
̅̅̅̅̅

5)EX-OR using NOR:-

The expression for EX- OR gate is

⊕
̅ ̅
Taking double inversion
̿̿̿̿̿̿̿̿̿̿̿̿̿̿
̅ ̅
Let ̅ =X and ̅ =Z

=̿̿̿̿̿̿̿
i g e g he e
̅̅̅̅̅̅̅ ̅ ̅
̅̅̅̅̅
̅ ̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅
̅ ̅̅̅̅̅̅̅̅
̅̅̅

But ̅̅̅̅̅
̅ ̅ and ̅̅̅ ̅

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ ̅

̅̅̅̅̅̅̅̅̅̅̅
̅ ̅̅̅̅̅̅̅̅̅̅
̅

Taking double inversion, we get

̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
̅̅̅̅̅̅̅̅̅̅̅
̅ ̅̅̅̅̅̅̅̅̅̅
̅

This is required expression for EX-OR gate using NOR gate.

 A

𝐴𝐵 𝐴 𝐵̅

Conclusion:-

All the gates are realized using NAND and NOR gates and truth tables are verified.
 Experiment No.3

Aim: Design and Implementation of 3 Bit Binary To Gray Code Convertor

Components: - IC 7486

Apparatus: Digital trainer kit, wires, probes, etc.

Theory:

Gray code is a non-weighted code. It is not an arithmetic code. It has a very special
feature that only one bit in the gray code will change, each time the decimal number is
incremented. As only one bit changes at a time, the gray code is called „unit distance code‟. The
gray code is cyclic code is also exhibits the reflective property.

Steps for converting Binary to Gray code

1) Record the MSB bit as it is.

2) Add this bit to the next bit, recording the sum and neglecting the carry bit(EX-OR
operation).
3) Record Successive sum until completion of all bits.

Logic Diagram: Binary to Gray Code Convertor

K-Map for G3:

G3 = B3

K-Map for G2:

K-Map for G1:

⊕
K-Map for G0:

TRUTH TABLE:

| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Conclusion:-

Thus result for Binary-to-Gray conversion is verified.

 EXPERIMENT: 4
Design and implementation of half/full adder and subtracter using logic
gates/universal gates
AIM: To design and verify
i. Half adder and Full adder
ii. Half subtractor and Full subtractor using basic and NAND gates.

LEARNING OBJECTIVE:
 To design, realize and verify the adder and subtractor circuits using basic gates and
universal gates.
 To design, realize and verify full adder using two half adders.
 To design, realize and verify a full subtractor using two half subtractors.

COMPONENTS REQUIRED: IC 7400, IC 7408, IC 7486, and IC 7432, Patch cards and IC
Trainer Kit.

THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B,
is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and
the other is the carry bit, C. The Boolean functions describing the half-adder are:

S =A ⊕ B C=AB
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This
carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds
two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions
describing the full-adder are:

S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)
Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and the
circuit to realize it is called a half subtractor. The Boolean functions describing the
halfSubtractor are:
S =A ⊕ B C = A’ B
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The Boolean
functions describing the full-subtracter are:
D = (x ⊕ y) ⊕ Cin Br= A’B + A’ (Cin) + B (Cin)
 I. TO REALIZE HALF ADDER

II. FULL ADDER

TRUTH TABLE BOOLEAN EXPRESSIONS:

 BASIC GATES

i) NAND GATES

III. HALF SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

INPUTS OUTPUT
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
IV. FULL SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

PROCEDURE:
 Check the components for their working
 Insert the appropriate IC into the IC base
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT:
 Experiment No. 5

Aim: To implement Booth’s algorithm.

Theory:
Booth algorithm gives a procedure for multiplying binary integers in signed 2’s
complement representation in efficient way, i.e., less number of additions/subtractions
required in general. It operates on the fact that strings of 0’s in the multiplier require no
addition but just shifting and a string of 1’s in the multiplier from bit weight 2k to
weight 2mcan be treated as 2k+1 to 2m.

As in all multiplication schemes, booth algorithm requires examination of the multiplier

bits and shifting of the partial product. Prior to the shifting, the multiplicand may be
added to the partial product, subtracted from the partial product, or left unchanged
according to the following rules:
1. The multiplicand is subtracted from the partial product upon encountering the first
least significant 1 in a string of 1’s in the multiplier.
2. The multiplicand is added to the partial product upon encountering the first 0
(provided that there was a previous ‘1’) in a string of 0’s in the multiplier.
3. The partial product does not change when the multiplier bit is identical to the
previous multiplier bit.

The Booth’s algorithm can be described using the following flowchart. We name the
register that keeps the partial product as A, the multiplicand as M, the multiplier as Q, the
extra bit Q−1 attached to Q0, which is the least significant bit of the multiplier, and the
counter as Count.

A and the appended bit Q−1 are initially cleared to 0 and the sequence Count is set to a
number n equal to the number of bits in the multiplier. The two bits of the multiplier
in Q0 and Q−1 are inspected. If the two bits are equal to 10, it means that the first 1 in a
string has been encountered. This requires subtraction of the multiplicand from the partial
product in A. If the 2 bits are equal to 01, it means that the first 0 in a string of 0’s has
been encountered. This requires the addition of the multiplicand to the partial product in
A.

When the two bits are equal, the partial product does not change. An overflow cannot
occur because the addition and subtraction of the multiplicand follow each other. As a
consequence, the 2 numbers that are added always have a opposite signs, a condition that
excludes an overflow. The next step is to shift right the partial product and the multiplier
(including Q−1). This is an arithmetic shift right (ashr) operation which A, Q, and Q−1
shifts to the right and leaves the sign bit in A unchanged. The sequence counter Count is
decremented and the computational loop is repeated n times.
Flowchart:
Program:
#include <stdio.h>
#include <conio.h>
#include <process.h>
#include <math.h>

int get(int a)
{ char ch =
'B'; int flag =
0; if (a == 1)
ch = 'A';
do {
printf("\nENTER VALUE OF %c: ", ch);
scanf("%d", & a);
if (a < 0) {
a = a * -1;
flag = 1;
}
if (9 <= a)
printf("│\n\t!INVALID NUMBER.ENTER VALUE (-9 < A < 9)!");
} while (9 <= a);
if (flag)
a = a * -1;
return (a);
}

void add(int * a, int * b)

{ int x, i, c = 0;
for (i = 3; i >= 0; i--)
{ x = a[i];
a[i] = c ^ x ^ b[i];
if (((c == 1) && (x == 1)) || ((x == 1) && (b[i] == 1)) || ((b[i] == 1) && (c == 1)))
c = 1;
else
c = 0;
}
}

void binary(int x, int * arr)

{ int i, p = x, c[4] = {
0,
0,
0,
1
};
for (i = 0; i < 4; i++)
arr[i] = 0;
if (x < 0)
x = x * -1;
 i = 3;
do {
arr[i] = x % 2;
x = x / 2;
i--;
} while (x != 0);
if (p < 0) {
for (i = 0; i < 4; i++)
arr[i] = 1 - arr[i];
add(arr, c);
}
printf("\n\nTHE BINARY EQUIVALENT OF %d IS : ", p);
for (i = 0; i < 4; i++)
printf("%d", arr[i]);
}

void rshift(int x, int * y)

{ int i;
for (i = 3; i > 0; i--)
y[i] = y[i - 1];
y[0] = x;
}

void main() {
int q = 0, i, j, a, b, A[4] = {0,0,0,0}, C[4] = {0,0,0,1}, C1[8] = {0,0,0,0,0,0,0,1};
int s = 0, z = 0, Q[4], M[4], temp, temp1[4], ans[8], y, x = 0, c = 0;
//clrscr();
printf("\n Name: Anuj Ganesh Pathare");
printf("\n Roll No: 35 (SE)");
printf("\n Subject: DLCOA");
printf("\n--------BOOTH'S MULTIPLICATION ALGORITHM--------\n");
printf("\nBoth Numbers must be less than 9 and greater than -9");
//printf("\n│----------------------------------------------------\n");
a = get(1);
b = get(0);
//printf("\n│---------------------------------------------------\n");
binary(a, M);
binary(b, Q);
printf("\n\n---------------------------------------------------\n");
printf(" OPERATION\t\t A\t Q\tQ'\t M");
printf("\n\n INITIAL\t\t");
for (i = 0; i < 4; i++)
printf("%d", A[i]);
printf("\t");
for (i = 0; i < 4; i++)
printf("%d", Q[i]);
printf("\t");
printf("%d\t", q);
for (i = 0; i < 4; i++)
printf("%d", M[i]);
for (j = 0; j < 4; j++) {
if ((Q[3] == 0) && (q == 1)) {
printf("\n A:=A+M \t\t");
add(A, M);
for (i = 0; i < 4; i++)
printf("%d", A[i]);
printf("\t");
for (i = 0; i < 4; i++)
printf("%d", Q[i]);
printf("\t%d\t", q);
for (i = 0; i < 4; i++)
printf("%d", M[i]);
}
if ((Q[3] == 1) && (q == 0)) {
printf("\n A:=A-M \t\t");
for (i = 0; i < 4; i++)
temp1[i] = 1 - M[i];
add(temp1, C);
add(A, temp1);
for (i = 0; i < 4; i++)
printf("%d", A[i]);
printf("\t");
for (i = 0; i < 4; i++)
printf("%d", Q[i]);
printf("\t%d\t", q);
for (i = 0; i < 4; i++)
printf("%d", M[i]);
}
printf("\n Shift \t\t\t");
y = A[3];
q = Q[3];
rshift(A[0], A);
rshift(y, Q);
for (i = 0; i < 4; i++)
printf("%d", A[i]);
printf("\t");
for (i = 0; i < 4; i++)
printf("%d", Q[i]);
printf("\t");
printf("%d\t", q);
for (i = 0; i < 4; i++)
printf("%d", M[i]);
}
printf("\n\n---------------------------------------------------\n");
printf("\nTHE ANSWER IN BINARY IS : ");
for (i = 0; i < 4; i++)
ans[i] = A[i];
for (i = 0; i < 4; i++)
ans[i + 4] = Q[i];
if (((a < 0) && (b > 0)) || ((a > 0) && (b < 0))) {
 for (i = 0; i < 8; i++)
ans[i] = 1 - ans[i];
for (i = 7; i >= 0; i--)
{ x = ans[i];
ans[i] = c ^ x ^ C1[i];
if (((c == 1) && (x == 1)) || ((x == 1) && (C1[i] == 1)) || ((C1[i] == 1) && (c == 1)))
c = 1;
else
c = 0;
}
}
for (i = 0; i < 8; i++)
printf("%d", ans[i]);
for (i = 7; i >= 0; i--) {
s = s + (pow(2, z) * ans[i]);
z = z + 1;
}
if (((a < 0) && (b > 0)) || ((a > 0) && (b < 0)))
printf("\nTHE ANSWER IN DECIMAL IS : -%d\n", s);
else
printf("\nTHE ANSWER IN DECIMAL IS : %d\n", s);
getch();
}
Output:
 Experiment No. 6

Aim: To implement restoring division algorithm.

Theory:
A division algorithm provides a quotient and a remainder when we divide two
number. They are generally of two type slow algorithm and fast algorithm. Slow division
algorithm are restoring, non-restoring, non-performing restoring, SRT algorithm and
under fast comes Newton–Raphson and Goldschmidt.

Restoring Division Algorithm is used to divide two unsigned integers. Restoring term is due
to fact that value of register A is restored after each iteration. Here, register Q contain
quotient and register A contain remainder. Here, n-bit dividend is loaded in Q and divisor is
loaded in M. Value of Register is initially kept 0 and this is the register whose value is
restored during iteration due to which it is named Restoring.

The number of steps required to compute the required quotient and remainder is equal to
the number of bits in the dividend. Initially, let the dividend be Q and the divisor be M and
the accumulator A = 0.
Therefore:

1. At each step, left shift the dividend by 1 position.

2. Subtract the divisor from A(A – M).
3. If the result is positive, then the step is said to be successful. In this case, the
quotient bit will be “1” and the restoration is not required.
4. If the result is negative, then the step is said to be unsuccessful. In this case,
the quotient bit will be “0” and restoration is required.
5. Repeat the above steps for all the bits of the dividend.

Note: Here, restoration is performed by adding back the divisor to A.

Flowchart:
Program:

#include <stdio.h>
#include <conio.h>
#include <math.h>

int getsize(int x)
{
int c;
if(x <= 1)
c = 2;
else if(x < 4)
c = 2;
else if(x< 8)
c = 3;
else if(x< 16)
c = 4;
else if(x< 32)
c = 5;
else if(x< 64)
c = 6;
else if(x< 128)
c = 7;
else if(x< 256)
c = 8;
else if(x< 512)
c = 9;
return c;
}

int max(int x,int y)

{
if(x< y)
return(y);
else
return(x);
}

void main()
{
int B,Q,Z,M,c,c1,e,f,g,h,i,j,x,y,ch,in,S,G,P;
int a[24],b[12],b1[12],q[12],carry=0,count=0,option;
long num;
do
{
//clrscr();
printf("\n Name: Anuj Ganesh Pathare");
printf("\n Roll No: 35 (SE)");
printf("\n Subject: DLCOA");
 printf("\n--------RESTORING DIVISION ALGORITHM--------\n");
printf("\n\nENTER DIVIDEND\t: ");
scanf("%d",&Q);
y = getsize(Q);
printf("ENTER DIVISOR\t: ");
scanf("%d",&M);
x = getsize(M);
Z = max(x,y);
printf("\n\tTOTAL BITS CONSIDERED FOR RESULT => %d",2*Z+1);
printf("\n\tINITiALLY A IS RESET TO ZERO:");
for(i=0;i<=Z;i++)
printf("%d ",a[i]=0);
for(i=Z;i>=0;i--)
{
b1[i] = b[i] = M%2;
M = M/2;
b1[i] = 1-b1[i];
}
carry = 1;
for(i=Z;i>=0;i--)
{
c1 = b1[i]^carry;
carry = b1[i]&&carry;
b1[i]=c1;
}
for(i=2*Z;i>Z;i--)
{
a[i] = Q%2;
Q = Q/2;
}
printf("\n\n\tDivisor\t\t(M)\t: ");
for(i=0;i<=Z;i++)
printf("%d ",b[i]); printf("\n\t2'C
Divisor\t(M)\t: ");
for(i=0;i<=Z;i++)
printf("%d ",b1[i]);
printf("\n\tDividend\t(Q)\t: ");
for(i=Z+1;i<=2*Z;i++)
printf("%d ",a[i]);
printf("\n\n\tBITS CONSIDERED:[ A ] [ M ]");
printf("\n\t\t\t");
for(i=0;i<=Z;i++)
printf("%d ",a[i]);
printf(" ");
for(i=Z+1;i<=2*Z;i++)
printf("%d ",a[i]);
count = Z;
do{
for(i=0;i< 2*Z;i++)
a[i] = a[i+1];
printf("\n\nLeft Shift\t\t");
for(i=0;i<=Z;i++)
printf("%d ",a[i]);
printf(" ");
for(i=Z+1;i< 2*Z;i++)
printf("%d ",a[i]);
carry=0;
for(i=Z;i>=0;i--)
{
S=a[i]^(b1[i]^carry);
G=a[i]&&b1[i];
P=a[i]^b1[i];
carry=G||(P&&carry);
a[i]=S ;
}
printf("\nA< -A-M \t\t");
for(i=0;i<=Z;i++)
printf("%d ",a[i]);
printf(" ");
for(i=Z+1;i< 2*Z;i++)
printf("%d ",a[i]);
ch=a[0];
printf("\nBIT Q:%d",ch);
switch (ch)
{
case 0: a[2*Z]=1;
printf(" Q0< -1\t\t");
for(i=0;i<=Z;i++)
printf("%d ",a[i]);
printf(" ");
for(i=Z+1;i<=2*Z;i++)
printf("%d ",a[i]);
break;

case 1: a[2*Z]=0;
printf(" Q0< -0\t\t");
for(i=0;i<=Z;i++)
printf("%d ",a[i]);
printf(" ");
for(i=Z+1;i< 2*Z;i++)
printf("%d ",a[i]);
carry=0;
for(i=Z;i>=0;i--)
{
S=a[i]^(b[i]^carry);
G=a[i]&&b[i];
P=a[i]^b[i];
carry=G||(P&&carry);
a[i]=S ;
}
printf("\nA< -A+M");
printf("\t\t\t");
for(i=0;i<=Z;i++)
printf("%d ",a[i]);
printf(" ");
for(i=Z+1;i<=2*Z;i++)
printf("%d ",a[i]);
break;
}
count--;
}while(count!=0);
num=0;
printf("\n\t\t< < QUOTIENT IN BINARY>> :");
for(i=Z+1;i<=2*Z;i++)
{
printf("%d ",a[i]);
num=num+pow(2,2*Z-i)*a[i];
}
printf("\n\t\tOUOTIENT IN DECIMAL :%d",num);
num=0;
printf("\n\t\t< < REMAINDER IN BINARY>>:");
for(i=0;i<=Z;i++)
{
printf("%d ",a[i]);
num=num+pow(2,Z-i)*a[i];
}
printf("\n\t\tREMAINDER IN DECIMAL :%d",num);
getche();
printf("\n\tDO YOU WANT TO CONTINUE PRESS 0-ESC 1-CONT.:");
scanf("%d",&option);

}while(option!=0);
getch();
}
Output:
 Experiment No. 7

Aim: To implement non restoring division algorithm.

Theory:
In Non-Restoring division, it is less complex than the restoring one because simpler
operation are involved i.e. addition and subtraction, also now restoring step is performed. In
the method, rely on the sign bit of the register which initially contain zero named as A.

Non-restoring division algorithm is used to divide two unsigned integers. The other form of
this algorithm is Restoring Division. This algorithm is different from the other algorithm
because here, there is no concept of restoration and this algorithm is less complex than the
restoring division algorithm.

The number of steps required to compute the required quotient and remainder is equal to
the number of bits in the dividend. Initially, let the dividend be Q and the divisor be M and
the accumulator A = 0. Therefore:
1. At each step, left shift the dividend by 1 position.
2. Subtract the divisor from A (A – M).
3. If the result is positive then the step is said to be “successful”. In this case,
the quotient bit will be “1” and the restoration is NOT Required. So, the next
step will also be subtraction.
4. If the result is negative then the step is said to be “unsuccessful”. In this case,
the quotient bit will be “0”. Here, the restoration is NOT performed like the
restoration division algorithm. Instead, the next step will be ADDITION in
place of subtraction.
5. Repeat steps 1 to 4 for all bits of the Dividend.
Flowchart:
Program:
#include <stdio.h>
#include <conio.h>

int a[5] = {0,0,0,0,0}, q[4], b[5], b2c[5];

void comp()
{ int i = 4;
do {
b2c[i] = b[i];
i--;
} while (b[i + 1] != 1);
while (i >= 0) {
b2c[i] = (b[i] + 1) % 2;
i--;
}
printf("\n\tDivisor's complement:");
for (i = 0; i < 5; i++)
printf("%d", b2c[i]);
printf("\n");
}

void nonresdiv()
{ shiftleft();
if (a[0] == 0)
a_minus_b();
else
a_plus_b();
q[3] = (a[0] + 1) % 2;
}

void shiftleft()
{ int i;
for (i = 0; i < 4; i++)
a[i] = a[i + 1];
a[4] = q[0];
for (i = 0; i < 3; i++)
q[i] = q[i + 1];
}

void a_minus_b() {
int i, carry = 0, sum = 0;
for (i = 4; i >= 0; i--) {
sum = (a[i] + b2c[i] + carry);
a[i] = sum % 2;
carry = sum / 2;
}
}

void a_plus_b() {
int i, carry = 0, sum = 0;
for (i = 4; i >= 0; i--) {
sum = (a[i] + b[i] + carry);
a[i] = sum % 2;
carry = sum / 2;
}
}

void main()
{ int i, j, k;
//clrscr();
printf("\n Name: Anuj Ganesh Pathare");
printf("\n Roll No: 35 (SE)");
printf("\n Subject: DLCOA");
printf("\n--------NON-RESTORING DIVISON ALGORITHM--------\n");
printf("\nEnter dividend in binary form\t: ");
for (i = 0; i < 4; i++)
scanf("%d", & q[i]);
printf("\nEnter divisor in binary form\t: ");
for (i = 0; i < 5; i++)
scanf("%d", & b[i]);
comp();
printf("\n\t[A]\t[M]\n");
for (i = 0; i < 4; i++) {
nonresdiv();
printf("\t");
for (j = 0; j < 5; j++)
printf("%d", a[j]);
printf("\t");
for (k = 0; k < 4; k++)
printf("%d", q[k]);
printf("\n");
}
if (a[0] == 1)
a_plus_b();
printf("\t");
for (j = 0; j < 5; j++)
printf("%d", a[j]);
printf("\t");
for (k = 0; k < 4; k++)
printf("%d", q[k]);
printf("\n");
printf("\n\tThe Quotient Is\t: ");
for (k = 0; k < 4; k++)
printf("%d", q[k]);
printf("\n\tThe Remainder Is: ");
for (j = 0; j < 5; j++)
 printf("%d", a[j]);
getch();
}

Output:
 Experiment No. 8

Aim:- To implement ALU design using Virtual Lab Simulator.

Requirements:- 1. Computer 2. COA Simulator

Theory:- ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic

operations like addition, subtraction,division, multiplication and logical oparations like
and, or, xor, nand, nor etc. A simple block diagram of a 4 bit ALU for operations
and,or,xor and Add is shown here :

The 4-bit ALU block is combined using 4 1-bit ALU block.

Design Issues :

The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal
S1 and S0 the circuit operates as follows:

for Control signal S1 = 0 , S0 = 0, the output is A And B,

for Control signal S1 = 0 , S0 = 1, the output is A Or B,

for Control signal S1 = 1 , S0 = 0, the output is A Xor B,

for Control signal S1 = 1 , S0 = 1, the output is A Add B.

The truth table for 16-bit ALU with capabilities similar to 74181 is shown
here:

Required functionality of ALU (inputs and outputs are active high)

Mode Select Fn for active HIGH operands
Inputs Logic Arithmetic (note 2)
S3 S2 S1 S0 (M = H) (M = L) (Cn=L)
L L L L A' A
L L L H A'+B' A+B
L L H L A'B A+B'
L L H H Logic 0 minus 1
L H L L (AB)' A plus AB'
L H L H B' (A + B) plus AB'
L H H L A⊕B A minus B minus 1
L H H H AB' AB minus 1
H L L L A'+B A plus AB
H L L H (A ⊕ B)' A plus B
H L H L B (A + B') plus AB
H L H H AB AB minus 1
H H L L Logic 1 A plus A (Note 1)
H H L H A+B' (A + B) plus A
H H H L A+B (A + B') plus A
H H H H A A minus 1

The L denotes the logic low and H denotes logic high.

Circuit Diagram:-
The circuit diagram of 4 bit ALU.
Procedure:-
1. Start the simulator as directed.This simulator supports 5-valued logic.
2. To design the circuit we need 4 1-bit ALU, 11 Bit switch (to give input,which will
toggle its value with a double click), 5 Bit displays (for seeing output), wires.
3. The pin configuration of a component is shown whenever the mouse is hovered on any
canned component of the palette. Pin numbering starts from 1 and from the bottom left
corner (indicating with the circle) and increases anticlockwise.
4. For 1-bit ALU input A0 is in pin-9,B0 is in pin-10, C0 is in pin-11 (this is input carry),
for selection of operation, S0 is in pin-12, S1 is in pin-13, output F is in pin-8 and output
carry is pin-7
5. Click on the 1-bit ALU component (in the Other Component drawer in the pallet) and
then click on the position of the editor window where you want to add the component (no
drag and drop, simple click will serve the purpose), likewise add 3 more 1-bit ALU (from
the Other Component drawer in the pallet), 11 Bit switches and 5 Bit Displays (from
Display and Input drawer of the pallet,if it is not seen scroll down in the drawer), 3 digital
display and 1 bit Displays (from Display and Input drawer of the pallet,if it is not seen
scroll down in the drawer)
6. To connect any two components select the Connection menu of Palette, and then click
on the Source terminal and click on the target terminal. According to the circuit diagram
connect all the components. Connect the Bit switches with the inputs and Bit displays
component with the outputs. After the connection is over click the selection tool in the
pallete.
7. See the output, in the screenshot diagram we have given the value of S1 S0=11 which
will perform add operation and two number input as A0 A1 A2 A3=0010 and B0 B1 B2
B3=0100 so get output F0 F1 F2 F3=0110 as sum and 0 as carry which is indeed an add
operation.you can also use many other combination of different values and check the
result. The operations are implemented using the truth table for 4 bit ALU given in the
theory.

Circuit diagram of 4 bit ALU:

Components:
To build any 4 bit ALU, we need:
1. AND gate, OR gate, XOR gate
2. Full Adder
3. 4-to-1 MUX<
4. Wires to connect.

Output :-

Result:
Four bit Arithmetic Logic Unit (ALU) is designed and simulated using logic gates.
 Experiment No. 9

Aim:- To implement memory design Virtual Lab Simulator.

Requirements:- 1. Computer 2. COA Simulator

Theory:-

Design of Memory :

A memory unit is a collection of storage cells together with associated circuits

needed to transform insformation in and out of the device. Memory cells which can
be accessed for information transfer to or from any desired random location is
called random access memory(RAM). The block diagram of a memory unit-

Internal Construction: The internal construction of a random-access memory of m

words with n bits per word consists of m*n binary storage cells and associated decoding
circuits for selecting individual words. The binary cell is the basic building block of a
memory unit.

Design Issues :

A basic RAM cell has been provided here as a component which can be used to design
larger memory units. An IC memory consisting of 4 words each having 3 bits has been
aslo provided.
Circuit diagram of 4X4 RAM memory:
Procedure:-
Design of 4X4 RAM memory:
1. Start the simulator as directed.This simulator supports 5-valued logic.
2. To design the circuit we need 12 binary RAM cell, 9 OR gate, 7 bit switch (to give
input,which will toggle its value with a double click), 3 bit display (to see the output),
wires.
3. The pin configuration of a component is shown whenever the mouse is hovered on any
canned component of the palette or press the 'show pinconfig' button. Pin numbering
starts from 1 and from the bottom left corner (indicated with the circle) and increases
anticlockwise.
4. For a binary RAM cell input is in pin-5, output is in pin-4 and select is pin-8,
Read/Write is in pin-6, for read operation give 1 input to Read/Write pin. For write
operation give 0 input to Read/Write pin.
5. For a 'decoder with enable', input A is in pin-6, B is in pin-5, output D0 is in pin-4, D1
is in pin-3, D2 is in pin-2, D3 is in pin-1 and Enable is in pin-8
6. Click on the 'decoder with enable' component (in the Other Components drawer in the
pallet) and then click on the position of the editor window where you want to add the
component (no drag and drop, simple click will serve the purpose), likewise add 12
binary RAM cell (from the Other Components drawer in the pallet), 9 OR gates (from
Logic Gates drawer in the pallete), 7 bit switches (which will toggle its value with a
double click), 3 bit displays (from Display and Input drawer of the pallet,if it is not seen
scroll down in the drawer)
7. To connect any two components select the Connection menu of Palette, and then click
on the Source terminal and click on the target terminal. According to the circuit diagram
connect all the components, connect 2 bit switches to the inputs of the 'decoder with
enable' (which will act as address input), 1 bit switch to the enable pin of the 'decoder
with enable' (which will act as memory enable input), connect a bit switch to the
Read/Write(R/W') line, 3 bit switches to the data inputs line, 3 bit displays to the data
output line and OR gates according to the diagram shown in the circuit diagram. after athe
connection is over click the selection tool in the pallete.
8. To see the circuit working, Do some read or write operation by properly setting the
R/W', memory enable then give input and check the output. suppose you give, R/W'=1,
memory enable=1, address input=01, data input=101, then it will be a read operation and
you will not see 101 as output, it will store 101 in the word-1. now again set, R/W'=0,
memory enable=1, address input=01, then it will be a write operation and you will see
101 as the content of word-1 on the output display.
Output:-

Result:
The memory design has been implemented using logic gates.
 Experiment No: 10
Aim: - To implement Ripple Carry Adder using Virtual Lab.

Theory: -

Design of Ripple Carry Adders:

Arithmetic operations like addition, subtraction, multiplication, division are basic operations to be
implemented in digital computers using basic gates like AND, OR, NOR, NAND etc. Among all the
arithmetic operations if we can implement addition then it is easy to perform multiplication (by
repeated addition), subtraction (by negating one operand) or division (repeated subtraction).

Half Adders can be used to add two one bit binary numbers. It is also possible to create a logical
circuit using multiple full adders to add N-bit binary numbers. Each full adder inputs a Can, which is
the Count of the previous adder. This kind of adder is a Ripple Carry Adder, since each carry bit
"ripples" to the next full adder. The first (and only the first) full adder may be replaced by a half
adder. The block diagram of 4-bit Ripple Carry Adder is shown here below –

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple
carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from
the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit.
Each full adder requires three levels of logic. In a 32-bit [ripple carry] adder, there are 32 full adders,
so the critical path (worst case) delay is 31 * 2(for carry propagation) + 3(for sum) = 65 gate delays.

Design Issues:

The corresponding Boolean expressions are given here to construct a ripple carry adder. In the half
adder circuit, the sum and carry bits are defined as

sum = A ⊕ B

carry = AB

In the full adder circuit, the Sum and Carry output is defined by inputs A, B and Carrying as

Sum=ABC + ABC + ABC + ABC

Carry=ABC + ABC + ABC + ABC

Having these we could design the circuit. But, we first check to see if there are any logically
equivalent statements that would lead to a more structured equivalent circuit.

With a little algebraic manipulation, one can see that

Sum= ABC + ABC + ABC + ABC

= (AB + AB) C + (AB + AB) C

= (A ⊕ B) C + (A ⊕ B) C

=A ⊕ B ⊕ C

Carry= ABC + ABC + ABC + ABC

= AB + (AB + AB) C

= AB + (A ⊕ B) C

Procedure: -

Design of Ripple Carry Adders:

Procedure to perform the experiment: Design of Ripple Carry Adders

1. Start the simulator as directed. This simulator supports 5-valued logic.

2. To design the circuit, we need 3 full adders, 1 half adder, 8 Bit switch (to give input),
3 Digital display (2 for seeing input and 1 for seeing output sum), 1 Bit display (to see
the carry output), wires.
3. The pin configuration of a component is shown whenever the mouse is hovered on
any canned component of the palette or press the 'show ipconfig' button. Pin
numbering starts from 1 and from the bottom left corner (indicating with the circle)
and increases anticlockwise.
4. For half adder input is in pin-5,8 output sum is in pin-4 and carry is pin-1, For full
adder input is in pin-5,6,8 output sum is in pin-4 and carry is pin-1
5. Click on the half adder component (in the Adder drawer in the pallet) and then click
on the position of the editor window where you want to add the component (no drag
and drop, simple click will serve the purpose), likewise add 3 full adders (from the
Adder drawer in the pallet), 8 Bit switches, 3 digital display and 1 bit Displays (from
Display and Input drawer of the pallet, if it is not seen scroll down in the drawer)
6. To connect any two components, select the Connection menu of Palette, and then
click on the Source terminal and click on the target terminal. According to the circuit
diagram connect all the components, connect 4 bit switches to the 4 terminals of a
digital display and another set of 4 bit switches to the 4 terminals of another digital
display. connect the pin-1 of the full adder which will give the final carry output.
connect the sum(pin-4) of all the adders to the terminals of the third digital display
(according to the circuit diagram shown in screenshot). After the connection is over
click the selection tool in the pallet.
7. To see the circuit working, click on the Selection tool in the pallet then give input by
double clicking on the bit switch, (let it be 0011(3) and 0111(7)) you will see the
output on the output (10) digital display as sum and 0 as carry in bit display.
Circuit diagram of Ripple Carry Adder:

Output: -

Conclusion: - The Ripple Carry Adder is implemented using Virtual Lab.