DesignCon 2006

PCB Loadboard Design

Challenges for Multi-Gigabit
Devices in Automated Test
Applications

Jose Moreira, Agilent Technologies

jose_moreira@agilent.com

Ming Tsai, Xilinx

ming.tsai@xilinx.com
Jonathan Kenton, Intel
jonathan.d.kenton@intel.com
Heidi Barnes, Agilent Technologies
hbarnes_2298@agilent.com

Don Faller, Agilent Technologies

don_faller@agilent.com
Abstract
With future consumer CMOS semiconductor devices reaching data rates of 5 to 10Gb/s
and multiple I/O lanes, designing appropriate PCB loadboards for characterizing and
testing these types of devices in an Automated Test Equipment (ATE) environment is
becoming a difficult challenge. This is not only because of the raw data speed but also the
high-pin count of these devices. The challenge faced by the ATE community is more
stringent than for the system-oriented PCB design community since it is not enough to
have suitable signal integrity for functional behavior, but the signal path must have
enough bandwidth to allow device characterization. This means that the ATE community
must use lower loss materials (e.g. Rogers4350) and more rigorous design techniques to
address this challenge successfully. For example, in an ATE application, trace lengths
might be on the order of 30-50 cm, requiring the use of passive equalization to
compensate for excessive trace loss. Additionally, disruptive PCB features such as inter-
layer vias must be carefully designed in order to minimize their effects on signal
integrity.

This article presents the results of an investigation of design and simulation techniques to
address these challenges. A series of hybrid Rogers4350/Getek boards was designed and
manufactured to evaluate and validate various simulation results and design techniques.
The main challenges addressed in this investigation are: routing and trace necking for sub
1mm pitch BGAs, loss effects from microstrip plating, via design, BGA ball-out
influence on signal performance, full signal path loss, passive equalization, and more.
Authors Biography

Jose Moreira is a senior application consultant in the Center of Expertise of Agilent’s

Semiconductor Test Solutions division in Böblingen, Germany. He focuses on the
challenges of testing high-speed digital devices especially in the area of signal integrity
and jitter testing. He joined Agilent Technologies in 2001 and holds a Master of Science
degree in electrical and computer engineering from the Technical University of Lisbon,
Portugal.

Ming Tsai is a staff hardware development engineer for Xilinx in the Product
Technology Division. His responsibilities include signal integrity analysis for the high-
speed signal transitions, high-speed loadboard design and characterization. He joined
Xilinx in October 2004 and earned his Ph.D. degree from the electrical engineering
department of University of California, Los Angeles in 1996.

Jonathan Kenton is a senior test technology engineer in Intel’s Chipset Group at

Folsom, Calif. He focuses on overcoming the signal integrity challenges of testing high-
speed serial interfaces on Intel’s chipsets. He joined Intel in 1997 and holds a Bachelor of
Science degree in computer engineering from the University of Kansas.

Heidi Barnes is a high frequency device interface board designer for Agilent’s 93000
semiconductor test system focusing on both digital and analog controlled impedance
transition design for full path integrity. Prior to this she was with the Agilent’s
Microwave Technology Center for eight years working with thinfilm, thickfilm, PCB
laminate chip and wire, and machined metal packaging technologies for DC to 20 GHz
high frequency analog and digital applications. She joined Agilent Technologies in 1990
and holds a Bachelor of Science degree in electrical engineering from the California
Institute of Technology.

Don Faller is a senior consultant in Agilent’s Applications Development Center for

Semiconductor Test Equipment. His main responsibility is solving customer’s signal
integrity problems on device interface boards for the Agilent 93000 SOC test system,
focusing on high-speed digital and RF applications. He joined Agilent Technologies in
1990 and holds a Bachelor of Science degree in electrical engineering from the
University of California, Davis.
Introduction
The advent of consumer-oriented CMOS devices with several hundred pins running at
speeds above 2.5Gb/s and stretching to 10Gb/s (Figure 1) presents complex challenges
for characterization and production testing of high-speed digital semiconductor devices
with automated test equipment (ATE). Although testing at-speed in high-volume
production might not be economically feasible, the use of an at-speed ATE system is
becoming more and more important in the characterization phase and early process
evaluation due to the challenges presented by the I/O data rate and the use of nanometer
processes [1, 2]. These challenges require the capability to parametrically test the device
under test (DUT) including the I/O at the full targeted data rate and sometimes even at
higher data rates to verify the design limits.

Figure 1: Intel's view on the future of CPU (left) and memory (right) interface data rates.
In this article we will address the DUT loadboard design challenge by presenting some of
the results of an ongoing collaborative project to investigate design methodologies for
DUT loadboards intended for high-speed applications. The main topics of the project are:

• Microstrip vs. stripline: what are the tradeoffs between a microstrip and a
stripline design strategy? What is the effect of the different plating techniques on
the microstrip performance.
• ATE integrated equalization: How well are we able to compensate for the signal
trace loss through equalization?
• Pogo via and inter-layer via design: what are the better designs and what
performance do those designs offer?
• Trace necking: What is the impact of trace necking when routing inside a dense
BGA?

The next section presents a description of the DUT loadboard design challenge for high-
speed applications. We will then present the results obtained for loss comparison between
microstrip and stripline traces, including the effects of various plating techniques for
microstrip. This is important because for some applications both microstrip and stripline
based designs are possible. After that, we will present how integrated passive
equalization in the ATE pin electronics can address some of the signal integrity
challenges. The challenge of via design will then be addressed, with particular attention
to the design of the pogo via and of inter-layer via transitions. Next we will address the
challenge of routing high-speed signals into large and small pitch BGAs. We will then
present a design example of a real application, incorporating many of the issues discussed
in the preceding sections. Finally we will present an article summary and conclusions.

Challenges for DUT Loadboard Design

Figure 2 shows the main components that are relevant for defining the signal integrity of
an ATE system. The first part of this system is the ATE pin electronics card. Typically,
this part of the system gets more attention as it is the card (or cards) that contains all the
measurement instruments of the ATE system and defines the base data rate and accuracy
of the system.
The second part of an ATE system is the pogo cable assembly. This assembly connects
the pin electronics card to a PCB board where the DUT will be located (DUT loadboard).
This assembly is basically a set of coaxial cables that must connect at the DUT loadboard
side in an automatic way by some mechanical system.

Figure 2: Components from a typical ATE system that have direct impact on the DUT signal
integrity (left: the card containing the ATE pin electronics; center left: the cable assembly connecting
the pin electronics to the DUT loadboard; center right: the DUT loadboard; right: the DUT socket.
Normally these two parts (pin electronics card and pogo assembly) are considered as a
single unit and used by the ATE vendor to define the ATE system performance as these
are the only components of the ATE system that are under complete control of the ATE
manufacturer. The third and fourth parts (DUT loadboard and socket) are typically under
the control of the user. Since these parts can have a significant impact on the ATE system
performance at the DUT in terms of signal integrity, the ATE manufacturer must develop
the specifications for an ATE system independent of them.

The performance of the test system must be measured in manufacturing and compared to
the specifications to guarantee the high quality needed for this type of measurement
equipment. One possible approach to measuring the performance at the DUT is the use of
a “golden” DUT loadboard, which defines the ATE performance at the end of this
specific DUT loadboard. This is not practical, however, as a single ATE system must
address a large number of applications and they can be very different in terms of the DUT
loadboard performance.

On the other hand, from the test engineer perspective, a DUT test application is typically
composed of three parts: the test requirements; the DUT loadboard and socket; and the
test program as shown in Figure 3.
Figure 3: Components of a typical application for testing a DUT in an ATE environment (left: the
DUT test requirements; center: the DUT loadboard and socket; right: the test program).
The ATE platform where the application is to be implemented is normally already
chosen. Since the DUT test requirements are defined at the DUT level, the test engineer
must develop each part of his application in such a way that he can fulfill the test
requirements. If the margin of the ATE system is already small for the application, then
the DUT loadboard performance becomes critical for successfully testing the DUT.
This means that for some applications very little headroom could exist between the
specifications provided by the ATE manufacturer at the ATE pogo assembly and the
specification needed by the test engineer at the DUT. This is represented in Figure 4.

Figure 4: The DUT loadboard signal integrity challenge.

To address this challenge both the ATE end users and the ATE manufacturers must work
together to make sure that reasonable specifications at the DUT can be inferred from the
ATE specifications. This requires the ability to either measure or accurately simulate the
effect of the DUT loadboard and socket, and to use the results to obtain the ATE
performance at the DUT. It is important to note that the performance characteristic can
change significantly for different sockets and DUT loadboards. The resulting “focused”
specifications will be application-dependent. Figure 5 shows an example of the signal
degradation caused by a DUT loadboard signal trace for a high-speed digital signal from
a DUT.
Figure 5: Example of the influence of a 21mil microstrip trace with a length of 14 inches on a 10Gb/s
PRBS31 data pattern (left: the stimulus signal from an Agilent N4901B serial BERT, right: the data
eye after the DUT loadboard signal trace).
In this example the signal trace is a 21 mil microstrip on Rogers4350. The trace length is
14 inches and an Agilent N4901B Serial BERT is used as the stimulus signal at 10 Gb/s.
Although the performance at the end of the DUT loadboard is still impressive, there is a
clear difference between the DUT output and the measured output at the end of the DUT
loadboard. Depending on the test requirements for this particular device, this can be a
problem for the test engineer.

It will be a dominant point of this article that the signal trace length is the main
contributor for the signal degradation of a typical DUT loadboard due to the skin effect
and dielectric loss. For the data rates discussed in this article, it is assumed that only low
loss dielectric materials will be used (e.g. Rogers4350) to minimize the loss component
caused by the dielectric. Even so, both the skin effect and the dielectric loss will
contribute to the total loss through the signal trace on the DUT loadboard

To better demonstrate how serious the influence of the trace length is on the performance
of the DUT loadboard, Figure 6 presents a graph showing the rise-time degradation with
the increase of the signal trace length for a 14mil microstrip in Rogers 4350. It should be
noted that using a 14 mil microstrip width for a very dense BGA application is a
challenge. Taking into account that DUT loadboard lengths can be greater than 30cm, we
may not be able to solve this challenge through DUT loadboard design techniques alone.

Figure 6: Trace length influence on the rise time for a 14mil microstrip on Rogers4350 (using the
approximations in [3]).
This effect is so strong that in some special cases, e.g. when focusing on design
verification testing, the loadboard is designed to use coaxial cables instead of using PCB
signal traces. The effects of adding the connectors for the coaxial cables is significantly
lower than the cumulative effect of the trace loss on the PCB. Figure 7 shows an example
from an actual application using this technique. Apart from lowering the signal path loss
by using coaxial cables, in this specific application the ability to use a smaller number of
ATE resources to test the DUT by changing cables was the main advantage.

Figure 7: Addressing the DUT loadboard signal trace length challenge by using coaxial cables (DUT
loadboard in Rogers4350 for a 5Gb/s application with the Agilent BIST Assist card).
This approach has several disadvantages but it can be a good option for quickly
addressing the trace length challenge.

Another option to address this challenge is the use of passive equalization [4, 5]. This
article will show that the use of integrated equalization in the ATE pin electronics is a
key technique for addressing this challenge.

Although skin effect and dielectric loss are the main contributors to the signal
degradation in a DUT loadboard, other structures like pogo pin vias and inter-layer
transition vias can be of a disruptive nature. If they are correctly designed we should not
be able to see an effect at the DUT due to the dominating effect of the signal trace loss,
but if they are not correctly designed, they can create a performance disruption serious
enough to make the DUT loadboard unusable.

Figure 8 presents an example of two via designs, a “standard” via and an optimized via.
and a comparison of the measured insertion loss. From the insertion loss it is possible to
see that the difference between the two via designs is minimal until around 1.5GHz.
Beyond 1.5GHz the “standard” via design shows very poor performance compared to the
optimized via. This is not a surprise given its design, but DUT loadboard designers have
not worried too much about these structures, since for most of the current high-speed
devices (e.g. PCI-Express graphics chip) the number of high-speed lanes was small
enough that a microstrip routing was possible, and did not require any vias. This will
change as we move forward to higher data rates and higher pin counts.
Figure 8: Comparison of the insertion loss between a "standard" via and an optimized via
(measurement of four consecutive vias on the signal path from a top microstrip to a bottom
microstrip with a 2.54mm height).
A series of PCB boards was designed and manufactured (Figure 9) to measure and
validate the results presented in this article. Two different stackups were used.

Figure 9: Experimental panels (top left: microstrip plating evaluation panel, top right: DUT
loadboard structures evaluation panel, bottom: picture of the manufactured boards).

The first stackup (Figure 10) was used for a series of boards containing only microstrip
signal traces and the main objective was to investigate the effect of different plating
techniques on the microstrip loss. The second stackup (Figure 11) was for a series of
boards containing more complex structures and will be shown in the following sections.
 Figure 10: Plating experiment boards stackup.

Figure 11: Experimental DUT loadboards stackup.

Microstrip vs Stripline Based Designs

The selection of microstrip or stripline routing for high-speed signals often starts with
cost considerations for the board stack-up and fabrication processes. Stripline designs can
provide excellent shielded transmission lines with constant phase delay versus frequency;
however, the extra layers and blind vias to achieve the best performance will add cost to
the fabrication of the board. Experiments were done to evaluate both microstrip and
stripline designs, not to select one over the other, but rather to optimize both and provide
flexibility for the wide variety of applications that might require different DUT loadboard
design strategies.
Microstrip
Initial experiments focused on the lower cost and simpler design of microstrip routing.
Rogers 4350 material was selected for its low loss, material repeatability, and similarity
of board manufacturing to standard FR4 materials. The thickness of the dielectric
material for the microstrip trace becomes a trade-off of loss versus dispersion effects.
Figure 12 shows how dispersion can be significant for a thick 18 mil dielectric, while 10
mil dielectric with a 21 mil trace width has very little dispersion at 10 GHz

Microstrip 36 mil
(18 mil dielectric)

Microstrip 21 mil
(10 mil dielectric)

Stripline 19 mil
(18/18 mil dielectric)

Figure 12: HFSS modeled dispersion for a microstrip (left) and measured loss per inch for 10 mil vs
6.6 mil dielectric (right).
The selection of a 10 mil dielectric is also a better choice when one considers dielectric
and resistive losses. Looking at measured data for a 21 mil microstrip on a 10 mil
dielectric versus that of a 13 mil trace on a 6.6 mil dielectric shows that the 21 mil trace
provides a significant 2dB improvement in loss for a 10 inch long trace. Although for
high pin count devices a 21mil microstrip trace brings other challenges that will be
discussed in the BGA routing section.

The next issue that can cause significant variation in the loss performance of long
microstrip transmission lines is the selection of plating and protective coatings. The skin
effect at higher frequencies [3] will force the current density to be concentrated on the
microstrip periphery where the plating and protection layers will have a significant effect.

Figure 13: Measured loss per inch for Ag plating, OSP, electroplated 30 µinches Au and 15 µinches
Au, soldermask and immersion 5 µinches Au [6].

Experiments done with silver plating, organic OSP coating and thick 30 plus µinches of
gold over nickel (Figure 13) show losses of about 0.32 dB per inch at 10GHz, while the
very thin 5 microinches or less of gold plating over nickel for the immersion gold process
has a loss of 0.5 dB per inch. At the DC end all of the losses are that of the bulk copper,
but at 10 GHz the skin effect can be seen, and the 200 µinch nickel barrier under the gold
plating becomes a source of higher losses [7]. The other problem with the nickel barrier is
that the magnetic permeability can vary significantly with different plating techniques
and while low permeability is desired it often can run as high as 100. Looking at the
models for nickel with a perfect permeability of 1 versus that of 100, one can see roughly
a 0.2 dB/inch increase in loss.

Figure 14: Modeled skin effect and magnetic permeability of nickel

The losses in the nickel barrier plating are not improved by a fabrication process that uses
the electroplated gold over nickel as the barrier for etching the underlying copper to form
the microstrip trace. The resulting cross section of the trace shows a mushroom shape
(Figure 15) where at higher frequencies, the electric currents traveling in the edge of the
conductor will be forced into a larger portion of the higher loss nickel plating. The
modeling in Figure 14 shows that this can add another 0.2 dB/inch of loss at 10GHz.

Figure 15: Cross section of a 23 mil copper microstrip with electroplated gold over nickel (left) and
the PCB board designed for evaluating the different plating techniques.
The measured data for these experiments utilized 10 inch long traces with a 4 inch
calibration trace so that the launch effects can be subtracted out and the loss per inch
determined (Figure 15).
The diagrams in Figure 16 show a time domain comparison between the worst case
immersion 5 µinch Au over Nickel plating and that of a thick 30 µinch Au over Ni. It is
possible to see a significant reduction on the jitter added by the microstrip trace.
Electroplated 30 µinch Au over Ni is already standard on most loadboards to provide
robust pogo and DUT fixture contact pads and thus works out to be the best trade-off
between improved loss and cost of fabrication.
Figure 16: Eye diagram comparison using a 10Gb/s PRBS31 data pattern through 10 inches of
microstrip between different plating options: Stimulus signal from an Agilent N4901B serial BERT
with external InP HBT pulse fidelity enhancement components (top center), 5 µinch immersion
Au/Ni (bottom left), 30 µinch electroplated Au/Ni (bottom right).

Stripline
Stripline modeling shows the loss to be similar to that of a microstrip when one maintains
the same trace width by increasing dielectric thickness. Through the use of optimized via
transitions one can take advantage of the reduced crosstalk that a stripline layout
provides.

Figure 17: Microstrip vs. stripline loss per inch of trace modeled (left) and measured (right).
Combinations of R4350 core and R4450B prepreg were used to achieve the desired trace width for
the microstrip and symmetric stripline geometries.
Another significant advantage of a stripline design is that, because it is on an inner layer,
no plating is required, and therefore none of the plating issues described in the previous
microstrip section are relevant. This results in a simpler model for stripline and less
variation between board manufacturers.
DUT Loadboard Equalization
In recent years there has been a significant amount of work around the topic of
equalization. The objective of equalization is to compensate for the signal distortion
created by the loss of the signal path. Several techniques exist to achieve this objective
and they can be very different in the approach they take to address this problem.

Equalizing circuits (also known as compensation networks) are necessary to push the
upper data rate range of copper links up to 10Gb/s [8,9,10,11,17]. Several different
techniques exist for equalizing lossy signal paths. They can be divided into
automatic/adaptive techniques, split-path or feed-forward amplifier, and continuous time.
For ATE, only continuous time equalization (e.g. passive compensation with a filter)
techniques are acceptable since the objective is not to get a functional data signal path but
to get a signal path that adds no distortion to the signals traveling on that path. This is an
important difference since only the data strobing point is important for a typical receiver,
therefore a discrete time filter approach for equalization can be used. Figure 18 shows the
basics of passive equalization applied to compensate for the skin effect loss of a coaxial
cable.

Figure 18: Passive equalization basics (left) and an example of a passive equalization circuit
implemented with surface mounted components (right).
In short, passive equalization provides the ability to flatten the frequency response by
attenuating the low frequency components of the signal. This means that the typical
passive equalization filter has a high-pass characteristic. Figure 18 (right) shows an
example of a passive equalizer circuit topology.

The difficulty in developing a passive equalization filter is not in developing the

appropriate compensation circuit but in its implementation since issues like size, parasitic
effects, etc. will change the expected performance of the equalization filter. This is
especially true when working at higher data rates.
Passive equalization has been previously used in the ATE arena in the compensation of
long coaxial cables when integrating external instrumentation on an ATE system [4,12].
Figure 19 shows an example from [12].
 Figure 19: Example of a passive equalization filter for a coaxial signal path (from [12]).
From the figure it is possible to see that the challenge was to compensate for more than 4
meters of cable in an ATE system for at-speed wafer probing at 10Gb/s. The addition of a
passive equalizer significantly increased the system bandwidth as presented in the signal
path insertion loss measurement. Notice that the DC loss of the equalizer is calibrated out
on the insertion loss graph. Figure 20 (right) presents another example of the use of a
passive equalizer filter, but in this case it is integrated in the high-speed ATE pin
electronics.

EMBEDDED PERFORMANCE AT
TEST APPLICATION EQUALIZER THE ATE POGO
ATE SYSTEM
POGO ASSEMBLY DUT LOADBOARD
POGO
EQU

Drv

ATE PIN CARD DUT

POGO
EQU

Comp

PERFORMANCE AT THE PERFORMANCE AT

ATE DRIVER/RECEIVER THE DUT

Figure 20: Simplified block diagram of an ATE system with integrated passive equalization in the pin
electronics (left) and example of integrating a passive equalization filter on the pin electronics
(Agilent High Speed Extension card) (right).

Notice that both the driver and receiver components of the pin channel card contain an
equalization filter before the respective measurement ASIC. In this specific example, the
ATE pin electronics is able to run at a maximum data rate of 12.8 Gb/s. We will use the
above example in the remainder of this section to demonstrate the advantages of passive
equalization to address the DUT loadboard challenge.

Figure 20 (left) shows a block diagram of the ATE signal path with an integrated
equalization in the ATE pin electronics and the relevant points for evaluating the
performance of the system.

The passive equalization filter integrated in the pin channel card presented in Figure 20
was designed to compensate for the pogo cable loss and a specific DUT loadboard signal
trace loss (e.g. 14 inch of a 21 mil microstrip in Rogers4350). Figure 21 (left) shows the
insertion loss between the ATE driver/receiver and the pogo pin at the DUT loadboard. A
special R&D bench setup was used for this measurement.

Figure 21: left: Insertion loss between the ATE driver/receiver and the DUT loadboard pogo pin
(including via and a ~2cm trace), right: data eye at the DUT loadboard pogo pin at 12.8Gb/s with a
PRBS31 data pattern.
The high-pass characteristic of the equalizer can be observed on the insertion loss graph.
This is because there was only a very small (~2cm) PCB trace in this measurement after
the pogo pin so the equalizer still shows the “strength” to compensate for an additional
DUT loadboard trace. On Figure 21 (right), the same effect can be seen in the time
domain where the data eye from the driver at the pogo is shown using a PRBS31 pattern
at 12.8 Gb/s. Notice the “overshoot” due to the “over-equalization” that is present at the
pogo pin. It is important not to confuse this overshoot with the overshoot from a driver IC
with pre-emphasis. Although the visual effect is the same, pre-emphasis is a very
different equalization technique and it only applies to the driver while passive
equalization applies to both driver and receiver.

This “over-equalization” effect at the pogo is also of no concern to the test engineer
because only the performance at the DUT matters. This effect will disappear if a typical
lossy DUT loadboard trace is added to the signal path as shown in Figure 22.

Figure 22: Insertion loss between the ATE driver/receiver and the DUT with and without the
integrated passive equalizer for a DUT loadboard 21mil width microstrip trace with a length of
approximately 25 cm.
From the insertion loss graph it can now be seen that there is no “over-equalization”
effect and that the passive equalizer is able to increase the bandwidth of the signal path
significantly. It is important to note that a correctly designed equalizer compensates only
for the signal path; it does not compensate for the DUT performance. A poorly
performing DUT will still be seen by the ATE receiver as a poorly performing DUT. If
the signal path length is larger, of course that signal path bandwidth will be lower but the
equalizer will always help (in comparison to having no equalizer). As long as the DUT
loadboard signal trace loss is larger than the loss for which the equalizer was designed
there will be no “over-equalization” effects.

Figure 23 shows the same result on the time domain, in this case the ATE driver is
running at 12.8 Gb/s with a PRBS31 data pattern. On the left side is the data eye
measured at the receiver if the passive equalization filter is removed from the ATE pin
electronics and on the left the data eye if the equalizer is included in the ATE pin
electronics.

Figure 23: Comparison of the ATE driver data eye measured at the DUT for a DUT loadboard with
a 14 inch 21mil microstrip trace (left: no equalizer; right: with equalizer).
The above results show that the use of integrated equalization on the ATE pin electronics
is a significant step forward in addressing some of the challenges associated with
designing DUT loadboards for high-speed applications.

Via Design
Usually, the planar signal routings on a DUT loadboard, either on microstrip or stripline
can be easily designed (geometry decisions are mainly limited to the trace width). The
main contributors for discontinuities on a DUT loadboard are the vertical transitions,
including pogo vias and inter-layer vias. As described in the introduction, via design is
extremely important since a non-optimized via can destroy the signal integrity of a DUT
loadboard. To address the challenge of designing and optimizing a via, the utilization of a
3D electromagnetic (EM) simulation tool [13] is very important to minimize the
discontinuities, and improve the signal bandwidth. In the following sub-sections we will
demonstrate the design methodology for a pogo via and an inter-layer via design.
Pogo Via Design
The pogo via is the launch point for the ATE signal going onto the DUT loadboard. The
pogo via geometry is primarily determined by the pogo block design which is fixed by
the ATE manufacturer. Some via parameters however are under the control of the
loadboard designer, and the loadboard needs to be carefully designed with proper drill
holes and patterns so it can be mated to the pogo blocks effectively in both electrical and
mechanical aspects.

Parameters Description Value unit

Metal thickness #1 Top and bottom metal layer 1.4 mil
Metal thickness #2 Inner metal layer 0.7 mil
Board thickness PCB thickness 0.25 inch
Signal via / pad dia. The diameter of signal via and pad 29 / 40 mil
GND via / pad dia. The diameter of signal via and pad 29 / 40 mil
Signal to GND via pitch The distance between the signal and GND vias 100 mil
Number of GND vias Number of GND vias around signal via 4
Microstrip width 50 ohms single-ended microstrip line on top layer 21 mil
Table 1: Design parameters for the pogo via 3D simulation example (the red values are set by the
ATE pogo block geometry).
When designing a pogo via for a DUT loadboard the following parameters are under the
DUT loadboard designer’s control and not fixed by the pogo block geometry:

• Signal via and pad diameters / Ground via and pad diameters;
• Ground relief on the inner ground and power planes;
• Signal routing layer / Back-drill or blind via to eliminate via stubs;

To demonstrate the use of 3D EM tools to optimize the pogo via design, the transition
from pogo pins (bottom side) to microstrip line (top side) is chosen. Figure 24 shows the
3D model in Ansoft HFSS. Table 1 presents the parameters that were fixed during this
pogo via study:

Figure 24: 3D HFSS model of the pogo pin and pogo via for a microstrip line transition.
The stackup used for this simulation can be found in Figure 11. The output port on the
top layer is a 50 Ω microstrip line on 10 mil Rogers 4350, and the trace width is 21 mils.
The design parameter studied here is the swell (also known as ground relief or via
clearance) diameter on all the GND layers. Figure 25 (left) shows the simulated insertion
loss and return loss of two cases with swell sizes of 70 mils and 100 mils. At lower
frequencies both cases look very similar, but the insertion loss quickly rolls off beyond
16 GHz. To better show the impedance discontinuities, the simulated scattering
parameters were converted to TDR plots. Figure 25 (right) shows the simulated TDR
results of these two cases. The first dip of both curves is from the pogo pin before
entering the PCB. The blue curve with the 70 mil swell shows more capacitive coupling
during the via transition, while the red curve with the 100 mil swell indicates too much
inductive coupling. The optimal case may be found in between these two values with a
little fine tuning. In fact, the swell size on all GND planes does not need to be identical.
In this case, since the microstrip line is located on top layer, the reference GND plane of
the microstrip line could be treated differently from the other GND layers.

Figure 25: Return loss and insertion loss of pogo via transitions (left) and simulated TDR results
(right) for two cases: swell diameter on GND planes as 70 mils and 100 mils.
Inter-Layer Via Design
Another important category of via design is the inter-layer transition. This is especially
important for high pin count devices. For this type of via, the DUT loadboard designer
has full control of the via geometry and, unlike the pogo via, has no mechanical
restrictions from the ATE system. Inter-layer via designs include the following
transitions:

• Bottom microstrip to (top microstrip / inner stripline);

• Inner stripline to (top microstrip / bottom microstrip / inner stripline);

Similar to the pogo via design, the inter layer via on ATE loadboard includes the
following design parameters:

• Signal via and pad diameters / ground via and pad diameters;
• Distance between signal via to ground vias / number of ground vias;
• Ground relief on the inner ground and power planes;
• Back-drill or blind via to eliminate via stubs;

Notice that unlike the pogo via, we now have control of the distance between the signal
via to the ground vias. To demonstrate a typical simulation design flow, a via with a
transition from a bottom to a top microstrip is chosen for this study. The nominal
dimensions have been chosen from the previous loadboard design and listed in Table 2.
This via was built on a test board and measured by using a network analyzer. Figure 26
shows the test structure on the test board. The board width is about 2.8 inches.

Parameters Description Value unit

Signal via / pad dia. The diameter of signal via and pad 26 / 45 mil
Ground via / pad dia. The diameter of ground via and pad 26 / 45 mil
Signal to GND via pitch The distance between the signal and GND vias 60 mil
Number of GND vias Number of GND vias around signal via 4
Swell diameter Ground relief on the inner ground and power planes 70 mil
Table 2: Design parameters for an inter-layer via transition.

Figure 26: 3D Model of test structure for microstrip-to-microstrip via transition (left) and
manufactured structure (right).
The resulting TDR measurement is shown in Figure 27 (left). The discontinuities at each
end of the graph are due to residues from the connector transition (not included in the
picture). It is clearly observed that the via transition exhibits excess capacitance. To
correlate this result in simulation, a via model has been developed in HFSS, as shown in
Figure 26. The simulated TDR result is presented in Figure 27 (right) and also shows the
excess capaticance, which agrees with the physical measurement.

Figure 27: Measured TDR (left) and simulated TDR (right) of the nominal microstrip-to-microstrip
via transition.
In order to improve the via transition, a simulation model should be set up to investigate
various design parameters. For example, Figure 28 shows the effect of changing the
signal via size. As expected, the smaller via yields excess inductance. Therefore, reducing
the via size will improve the via transition for the nominal case. Other variables that
could be studied as well are swell sizes and signal-to-GND pitch.

Figure 28: Simulated TDR of the microstrip-to-microstrip via transition for various signal via
diameters.

Routing Challenges in the BGA Area

As device packaging increases in both pin count and density, the challenge of routing
signals through a BGA grid becomes increasingly difficult. With the pitch of BGA
packages trending downward from 1mm to 0.7mm and below, the space left for routing
traces through the BGA pads approaches the PCB manufacturing limits. In addition, with
increasing pin count, traces must be routed further into the BGA grid to reach their
intended pad. Whereas it has been shown that trace width should be increased to limit the
conductive loss due to skin effect, the limitations in the BGA region do not allow for this.

Figure 29: The challenge of routing large width traces into small pitch BGA arrays.
To illustrate the routing limitations in the BGA region, consider the PCB manufacturing
limits described in Table 3. With a pitch of 1 mm, there is enough room between pads to
route a 16 mil trace, which is wide enough to limit the conductive loss across the trace
length. If the stripline trace width were 19 mil from the pogo pin to the BGA region,
there would only be a small discontinuity where the trace tapered down to 16 mils to
route into the BGA. However, as the pitch decreases to 0.7mm, the space available for
routing a trace is only 4 mils (Table 3). This presents a rather large discontinuity where
the trace must taper from a width of 19 mils, and will cause significant reflections in the
time domain resulting in signal degradation. To decrease the size of the discontinuity, the
size of the step in trace width must be decreased, resulting in a trace width that is much
less than the 19 mils used in the long distance from the pogo pin to the BGA. If the
resulting trace length is more than 1-2 inches, it can result in sufficient loss to degrade the
signal beyond a tolerable limit. Another issue is that the width of the ground region on
the adjacent layers under the BGA is only as wide as the trace width where the trace
routes between adjacent vias. This will result in a small discontinuity at every point
where the trace routes between adjacent vias in the BGA region. The additive effect of
these discontinuities must also be considered.

BGA Pitch
1.0 mm 0.8 mm 0.7 mm
Minimum drill diameter 10 mils
Minimum pad size 18 mils
Minimum pad-to-trace distance 3 mils
Minimum anti-pad on ground layer 24 mils
Maximum trace width 16 mils 8 mils 4 mils
Maximum ground width under trace 16 mils 8 mils 4 mils
Table 3: PCB manufacturing tolerances and effect on trace width for varying BGA pitch.
To evaluate these effects, an experiment was constructed with varying trace widths both
in the pogo pin to BGA region, and within the BGA region. One set of traces included a
surrounding array of grounded vias to fully simulate the routing path through the BGA
region. The other set did not include the BGA vias so that just the effects of the step in
trace width could be evaluated. In all cases, the trace length through the BGA region was
selected to be as long as might be expected for a typical device in a large package with a
dense I/O count. Since we are dealing with high pin count applications, we have only
investigated this effect on stripline traces but the results can be extrapolated easily for
microstrip traces. Figure 30 illustrates the trace geometry and presents a table of three
different experiments done with different geometries.

Figure 30: Test trace geometry for a single ended stripline (left) and the geometry for three different
experiments (right)
Figure 31 shows the layout for the experiment and a picture of the manufactured board.
Note that the board contains more test structures than what is presented in this section.
Figure 32 and Figure 33 present the measured results for the three experiments.

Figure 31: PCB Layout for evaluating the effect of trace necking for BGA routing of large width
traces (left) and picture of the manufactured board with the test structures (right).

Figure 32: Results from the different test structures experiments: measured insertion loss (left),
measured TDR (right).
The results show that the impedance discontinuity from the trace necking creates a
significant effect that can be seen on the insertion loss and TDR results. In the frequency
domain, the experiments with a wider trace width for the pogo pin to BGA section (1 and
2) show lower loss but with significant ripple due to the large discontinuity at the necked
down region. The TDR data shows the effect of the discontinuity at the necked down
region. At first glance, experiment 3, with a relatively narrow trace width in the pogo pin
to BGA section, would appear to be the better choice because of the smaller discontinuity
at the necked down region within the BGA. However, the eye diagrams in Figure 33
show how the slow rise time caused by the higher trace loss has a negative effect on the
measured eye width. For this set of experiments, experiment 2 appears to be the best
compromise between the effects of the discontinuity at the step in trace width and that of
the trace loss in the pogo pin to BGA region. What has not been examined is to what
degree passive equalization, as discussed previously, would improve the eye diagram for
experiment 3 by improving the rise time. As expected, there will be a compromise
between the trace width for signal traces with a significant length (WT) and the size of the
trace discontinuity when going into the BGA.

Figure 33: Data eye results after each test structure using PRBS31 data pattern at 10Gb/s (top left:
structure 1, top right: structure 2, bottom center: structure 3).

Design Example
In this section we will provide an example of real DUT loadboard design for a 10+ Gb/s
application. The number of high-speed lanes was small enough that a microstrip routing
was possible. The high-speed I/Os of the DUT are on the periphery of the package so no
trace necking was necessary. NiAu plating without solder mask was used for the
microstrip traces. Figure 34 shows a picture of the DUT loadboard and the optimized
pogo via design used for the loadboard. Note that a smaller swell is used on the reference
plane of the microstrip.

70 mil Swell Microstrip Gnd1

100 mil Swell (Everything Else)

29mil +/-1mil drill / 40mil Pad

Topside Microstrip Trace

R4350
GETEK Pogo

Figure 34: DUT loadboard picture (left) and pogo via design (right).
The via optimization was done using the approach presented in a previous section and
some of the results are presented in Figure 35.
Figure 35: Results for different ground swell diameters for the reference plane bellow the microstrip
(left: insertion loss, right: TDR).
In Figure 35 it is possible to observe the results of four different geometries for the
ground swell below the microstrip trace, and the respective insertion loss and TDR
response plots. It is clearly visible from simulation run “C”, with a 70 mil swell, that the
discontinuities are minimized as compared to the other geometries.

As previously mentioned in the article introduction, it is important to be able to simulate

the performance of the entire signal path between the ATE driver/receiver and the DUT,
since this allows the test engineer to verify if the performance of the signal path is
adequate for the intended application. Figure 36 shows an example of a possible setup for
this type of simulation and the simulated insertion loss using the Agilent Advanced
Design System (ADS).

Figure 36: ADS setup of the insertion loss of the complete signal path from the ATE receiver/driver
to the DUT (left) and insertion loss comparison between simulation with the standard model for the
microstrip trace, a tuned model and measured data (right).
This simple example demonstrates that with appropriate models the test engineer can
obtain a good approximation of the expected performance of the entire signal path, even
before building the DUT loadboard. Note that the simulation above includes the model of
the ATE pogo assembly and of the integrated equalizer. It is also important to note that a
more complex model for the microstrip trace that included the losses from the microstrip
plating was used since the standard model of the software package provided an overly
optimistic result. This is typical when trying to obtain realistic simulation results and an
investment has to be made to develop quality simulation models. The model was based
on results from some of the project test boards utilized to measure the effects of the
plating on the microstrip loss.
To show how an integrated equalizer is able to compensate for some of the signal path
loss, we measured the output of the DUT using the DUT loadboard presented in Figure
34 at the ATE receiver using a special R&D setup.

Figure 37 shows the data eye from the Xilinx Virtex 4 FPGA running at 10Gb/s with a
PRBS7 data pattern. This data eye was taken at the output of a R&D characterization
board, which includes approximately 2.5 inch of a 21mil width microstrip trace.

Figure 37: Data eye output from a Xilinx Virtex 4 FPGA MGT at 10Gb/s using a PRBS7 pattern.
Figure 38 shows the same data eye when the DUT is used on the DUT loadboard that
includes a 14 inch 21mil microstrip trace. It shows the difference between the data eye at
the ATE receiver when no integrated equalizer on the pin electronics is used and when
the integrated equalizer of Figure 20 is used.

Figure 38: Data eye at the ATE receiver with a 21mil microstrip DUT loadboard trace with a 14 inch
length with no integrated equalization on the pin electronics (left), data eye at ATE receiver with
integrated equalization (right).
From Figure 38 it is possible to observe that the integrated equalizer, by compensating
for part of the signal path loss is able to bring the measured DUT data eye closer to the
real DUT output.

Summary and Conclusions

The challenges of designing a DUT loadboard for high-speed digital applications are
increasing with the speed and pin count explosion. The fact that some of these
applications are intended for consumer type markets creates even more price and time-to-
market pressure. In this article we have shown that it is possible to extend the
performance of the DUT loadboard to the 10Gb/s range through a more complex design
strategy, better choice of the materials and the use of equalization.

Unfortunately, each application is unique, which means that a DUT loadboard designer
needs to look closely at the application requirements and at the capabilities of the PCB
board manufacturers. When moving to this high-speed arena, it is important to understand
the performance of the DUT loadboards that are being designed. Our suggestion is to use
test coupons that sometimes can be manufactured on the same panel as the DUT
loadboard (Figure 39). The test coupon should mimic the DUT loadboard’s high-speed
signal path except that it uses a connector instead of a socket. On the ATE pogo side a
special pogo block assembly can be used, so that full S-parameter measurements and time
domain measurements can be made.

Figure 39: Example of a DUT loadboard test-coupon board (left) and a socket centric automatic
focus calibration (right).

It should also be noted that even with the best designed DUT loadboard and integrated
equalization, it is still necessary to calibrate the system at the DUT socket level in order
to obtain the maximum performance from the ATE system. This is becoming possible
through the use of automatic or robotic systems that probe the DUT socket directly
(Figure 39).

This paper has addressed a significant portion of the challenges facing designers of multi-
Gigabit PCB loadboards but it cannot address everything. In the author’s opinion, more
work is needed to address the signal integrity challenge and reliability of DUT loadboard
sockets [14]. We also did not investigate the use of exotic materials for PCB dielectrics
(e.g. Teflon) given the complex manufacturing requirements for a typical DUT
loadboard. Finally, an important point is the influence of the PCB manufacturing process
variation. To address this challenge a worst case design methodology must be used [15].

Acknowledgements
The authors would like to thank Kosuke Miyao and Markus Rottacker from Agilent
Technologies for the sponsorship of this project and Roger Nettles and Christoph Zender
also from Agilent Technologies for the feedback and suggestions they provided. We
would like to thank William Burns from Altanova for leading the layout work for this
project and to Crescencio Gutierrez from Harbor for the discussions regarding PCB
manufacturing issues. Our appreciation goes to Rosenberger, especially Roland Hermann
for the connector footprint optimization for our specific boards and to Mike Howieson
and his team from Thin Film Technology for all the discussions around signal integrity
and equalization. We would like to thank David Ferguson from Xilinx for helping with
the Virtex 4 measurements and Morgan Culver and Brandon Hunter from Agilent
Technologies for their assistance with some of the measurements. The author, Jose
Moreira would like to thank Markus Knoch from Agilent Technologies for the freedom
provided in leading this project.

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