Design Report

Project – High gain amplifier at 45 nm and 90 technology node

A report
Submitted in fulfillment of the requirements for the award of
WORKSHOP ON MICRO AND NANO DEVICE
(Electronics and communication engineering)

Submitted to
Dr. Suman Lata Tripathi

Name of Student: Jai Shivam Chaudhary

Registration Number: 12018935
Department: VLSI Design
Course name & Course Code: Workshop on Micro and nano Device (ECE 167)
Email Id: jaishivam555@gmail.com
 ABSTRACT
The objective of this paper is to design a high gain amplifier using different topologies
that are at both 45nm and 90nm technology. Differential amplifiers are the basic building
block in the analog circuit design. amplifier nodes using Cadence Virtuoso. The
characteristics of the high gain amplifier are measured by Gain, Common mode Rejection
Ratio, and Gain Bandwidth product. In this paper a high performance differential
amplifiers are designed using different approaches and a comparison is made between
them The project has comprehensive analyses including DC, transient, and power
analyses to evaluate the performance and efficiency of the amplifier design. Successful
integration of electronics and software engineering is showcased, demonstrating the
collaborative effort required in VLSI design. Despite the achievements, the challenges
associated with miniaturization, such as leakage currents and process variations, are
addressed through appropriate design strategies, possibly involving transistor sizing and
circuit optimizations. The simulation results are verified by using cadence virtuoso, 45nm
and 90nm technology at supply voltage 1v and 1.5v respectively.

Overall, this project contributes to the growing body of knowledge in Micro and Nand
devices and highlights the potential for these technologies to revolutionize various
industries.

Keywords: CMOS,High Gain amplifier, CMRR, VLSI.

 Introduction
Over the past few years, the electronics industry has made tremendous changes in the era of
VLSI technology. The major changes that came through in the market are due to the invention
of MOS transistors. Integration of ICs from small scale, medium scale, large scale to over ultra
large-scale integration has led many changes in the electronic industry. It consists of mainly
memory, small or micro and logic sales, has contributed a worldwide sale of approximately 75%
with the MOS transistors, which enhances the strength of CMOS technology. CMOS technology
involves mainly satisfying all the design constraints like power, area, and speed by minimizing
the feature size and using the optimization techniques by lowering the supply voltage, using
VTCMOS and MTCMOS etc. CMOS technology has more advantages than an NMOS technology
design due to the design flexibility and easily configurable. The high gain amplifier amplifies the
difference of two input signals which are out of phase and rejects the signals which have
common phase due to any noise induced. This is measured or termed as common mode
rejection ratio (CMRR) and its offset voltage. [1]An ideal amplifier circuit has infinite CMRR. A
feedback circuit like common mode feedback circuit is used at the output of the amplifier which
is used to adjust the bias current and hence rejects the common mode signals.

Fig 1. Proposed CMOS level design of Amplifier

Two types of offset voltages input offset voltage and output offset voltage, the output offset
voltage is defined as the difference between the final output voltage to the ideal output voltage
when a common signal is applied at both the ends of inputs, similarly when the output offset
voltage is divided by the differential voltage gain then it is termed as input offset voltage.
 Design and Operation
Implementation of overall design is carried out on Cadence Virtuoso Software at 45 nm and 90
nm Technology node and all the components utilized are of gdk 45 nm and 90 nm.

Fig 2. CMOS level design for High Gain Amplifier

This Fig 2. has the simplified design for High gain Amplifier which have bias current (Ibias) to provide the
voltage and set the operating point of the transistor

.
Fig 3. Symbol created for the amplifier on Cadence.
The CMOS high gain amplifier in this report includes-a bias current, differential mode and
common mode.
Differential mode amplifier:
Differential mode in an amplifier is when the two input voltages change in opposite
directions. In this mode, the two voltage followers oppose each other, with one trying to
increase the voltage of the common emitter point and the other trying to decrease it. The
common point does not change its voltage, behaving like a virtual ground.

Fig.4 Differential mode for high gain amplifier

A differential mode amplifier is a circuit whose output voltage is directly proportional to

the difference between voltages applied at its to inputs. Ideally, this amplification of
voltage difference is useful in eliminating noise signal which is common to[1] both the
inputs i.e. a Common Mode Rejection Ratio of infinity.
In differential mode the applied Vsin to the input are different i.e.one is applied to +ve
and other is applied to -ve.

In this report differential mode amplifier is test on 45nm and 90nm technology mode and
for both mode analysis of various parameters is observed.
Common mode Amplifier:
A common-mode amplifier is a type of amplifier circuit used in electronics to amplify
signals that are common to both input terminals while rejecting signals that are not
common to both terminals. In simpler terms, it amplifies the part of the input signal that
appears equally on both input terminals (the common-mode signal), while ideally
ignoring or minimizing any signal differences between the two terminals (the differential
mode signal). Common-mode signals often arise due to noise or interference picked up
by the input connections of a system. By amplifying only the common-mode signal, the
common-mode amplifier helps in removing or reducing this unwanted noise, which is
crucial in various applications where signal integrity is essential, such as in
communication systems, instrumentation, and sensor applications.

Fig. 5 Common mode high gain amplifier

Common-mode amplifiers are commonly used in differential amplifier configurations,

where one input is the actual signal input, and the other input is connected to a reference
or ground potential. The output of the amplifier provides the amplified common-mode
signal, while ideally rejecting any differential signals. Overall, common-mode amplifiers
play a vital role in ensuring the accurate processing of signals in electronic systems by
improving signal quality and reducing interference.
Value Provided

Common Mode Differential Mode

Parameters 45nm 90nm 45nm 90nm
IDC (input Current) 20u 20u 20u 20u
Supply Voltage 1v 1.5v 1v 1.5v
Capacitor 10p 10p 10p 10p
Frequency 1000 Hz 1000 Hz 1000Hz 1000 Hz

Waveform Analysis

Transient Analysis (45 nm Differential Mode)

DC Analysis(45nm Differential Mode)

AC Response(45nm Differential Mode)

In AC response we can observe the gain in dB which is around 5.

Bandwidth and Gain
freq (Hz) dB20(VF("/out"))Ex
(dB)
pression Value
10 7.297 bandwidth(dB20(VF("/out")) 3 "low" ) 2.63E+05
12.59 7.297
15.85 7.297
19.95 7.297
25.12 7.297
31.62 7.297
39.81 7.297
50.12 7.297
63.1 7.297
79.43 7.297
100 7.297
125.9 7.297
158.5 7.297
199.5 7.297
251.2 7.297
316.2 7.297
398.1 7.297
501.2 7.297
631 7.297

Bandwidth=2.63*10^5
Gain(in db)=7.297
In 45nm differential Mode Amplifier the gain calculated is 7.29, which is still not a
acceptable gain for a High Gain Amplifier.

Average Power
time (s) getData(":pwr" ?result
Expression
"tran") (W) Value
0 2.01E-05 average(getData(":pwr" 2.01E-05
?result "tran"))
5.00E-06 2.01E-05
1.50E-05 2.01E-05
3.50E-05 2.01E-05
7.50E-05 2.01E-05
1.55E-04 2.01E-05
2.38E-04 2.01E-05
3.22E-04 2.01E-05
4.05E-04 2.01E-05
4.88E-04 2.01E-05
5.72E-04 2.01E-05
6.55E-04 2.01E-05
7.38E-04 2.01E-05
8.22E-04 2.01E-05
9.05E-04 2.01E-05
9.88E-04 2.01E-05
1.07E-03 2.01E-05
1.16E-03 2.01E-05
1.24E-03 2.01E-05

The average power for 45nm differential mode amplifier is 2.01*10^-5 W.

Transient Analysis (45 nm Common Mode)

DC Response(45nm Common Mode)

AC Response(45nm Common Mode)

Here the Gain in dB is -5dB as it is common mode amplifier.

Gain in Common mode
freq (Hz) dB20(VF("/out")) (dB)
1 -6.745
1.259 -6.745
1.585 -6.745
1.995 -6.745
2.512 -6.745
3.162 -6.745
3.981 -6.745
5.012 -6.745
6.31 -6.745
7.943 -6.745
10 -6.745
12.59 -6.745
15.85 -6.745
19.95 -6.745
25.12 -6.745
31.62 -6.745
39.81 -6.745
50.12 -6.745
63.1 -6.745

Gain(dB)=-6.745 dB

CMRR=14.03

Transient Analysis (90 nm Differential Mode)

AC Analysis (90 nm Differential Mode)

Overall Gain(90nm differential amplifier)

freq (Hz) dB20(VF("/out")) (dB)
10 16.81
12.59 16.81
15.85 16.81
19.95 16.81
25.12 16.81
31.62 16.81
39.81 16.81
50.12 16.81
63.1 16.81
79.43 16.81
100 16.81
125.9 16.81
158.5 16.81
199.5 16.81
251.2 16.81
316.2 16.81
398.1 16.81
501.2 16.81

Here overall gain observed is 20dB.

Power observed.
time (s) getData(":pwr" ?result
Expression
"tran") (W) Value
0 7.25E-05 average(getData(":pwr" ?result
7.25E-05
"tran"))
5.00E-06 7.25E-05
1.50E-05 7.25E-05
3.50E-05 7.25E-05
7.50E-05 7.25E-05
1.55E-04 7.25E-05
2.38E-04 7.25E-05
3.22E-04 7.25E-05
4.05E-04 7.25E-05
4.88E-04 7.25E-05
5.72E-04 7.25E-05
6.55E-04 7.25E-05
7.38E-04 7.25E-05
8.22E-04 7.25E-05
9.05E-04 7.25E-05
9.88E-04 7.25E-05
1.07E-03 7.25E-05
1.16E-03 7.25E-05
1.24E-03 7.25E-05

Transient Analysis (90 nm Common Mode)

DC Analysis (90 nm Common Mode)

AC Analysis (90 nm Common Mode)

Here the gain can be observed is around -10dB.

Overall Gain(90nm common mode)

freq (Hz) dB20(VF("/out")) (dB)
10 -15.26
12.59 -15.26
15.85 -15.26
19.95 -15.26
25.12 -15.26
31.62 -15.26
39.81 -15.26
50.12 -15.26
63.1 -15.26
79.43 -15.26
100 -15.26
125.9 -15.26
158.5 -15.26
199.5 -15.26
251.2 -15.26
316.2 -15.26
398.1 -15.26
501.2 -15.26
631 -15.26

Gain observed through accuracy on table is -15.26dB.

CMRR=45.26

Multistage Amplifier (90nm technology)

A Multistage Amplifier is obtained by connecting several single-stage amplifiers in
series or cascaded form. Whenever we are unable to get the required amplification
factor, input, and output resistance values by using a single-stage amplifier, that time
we will use Multistage amplifiers. Based on the requirement, we will connect the
number of transistors to the output of a single-stage amplifier.
If the gain obtained by a single-stage amplifier is not sufficient, then we
will connect multiple transistors to increase the gain of the AC input signal.
Since multiple stages are present between the input and output of this
circuit, it is known as a Multistage amplifier.
 Fig 6. CMOS level design for Multistage High Gain Amplifier(90 nm)

Here the design of multistage amplifier is done on 90nm technology node at supply
voltage of 1.5V.

In Multi-stage amplifiers, the output of first stage is coupled to the input of next
stage using a coupling device. These coupling devices can usually be a capacitor or a
transformer. This process of joining two amplifier stages using a coupling device can
be called Cascading.
 Fig 7. Testing design for Multistage High Gain Amplifier(90 nm)

This figure have a supply voltage of 1.5V and input supply at 0.8V and the frequency in
Vsin=1000 Hz.

Transient Analysis (multistage)

DC Response(multistage)

AC Response(multistage)

In this graph the gain observed is 25dB.

And the Bandwidth is 1.56*10^9.
Power Analysis
time (s) getData(":pwr" ?result
Expression
"tran") Value
(W)
0 5.79E-05 average(getData(":pwr"
5.78E-05
?result "tran"))
5.00E-06 5.80E-05
1.50E-05 5.81E-05
2.63E-05 5.82E-05
4.88E-05 5.84E-05
9.40E-05 5.87E-05
1.77E-04 5.91E-05
2.61E-04 5.92E-05
3.44E-04 5.90E-05
4.27E-04 5.85E-05
5.11E-04 5.78E-05
5.94E-04 5.70E-05
6.77E-04 5.64E-05
7.61E-04 5.63E-05
8.44E-04 5.66E-05
9.27E-04 5.72E-05
1.01E-03 5.80E-05
1.09E-03 5.87E-05
1.18E-03 5.91E-05

Average Power of Overall circuit is 5.78*10^-5 W.

Multistage amplifier with changed W/L

Changing the W/L [2]ratio of a transistor in a multistage amplifier can result in a higher
current for a given gate-source voltage and can increase the overall gain is changed
accordingly.

In the above Multistage amplifier, the total width of transistor was 120nm which now
change to double that means 240nm but in one single transistor to observe the change .
 W=240n
m

Now Here the Total width of Highlighted transistor is 240nm.

Transient Response
AC Response

Bandwidth and Gain

freq (Hz) dB20(VF("/out"))
Expression
(dB) Value
10 27.67 bandwidth(dB20(VF("/out"))
3.18E+3 "low"
09 )
12.59 27.67
15.85 27.67
19.95 27.67
25.12 27.67
31.62 27.67
39.81 27.67
50.12 27.67
63.1 27.67
79.43 27.67
100 27.67
125.9 27.67
158.5 27.67
199.5 27.67
251.2 27.67
316.2 27.67
398.1 27.67
501.2 27.67
631 27.67
In the above table overall Gain is 27.67 dB which is maximum is all observation and
Bandwidth is 3.18*10^9.

Power Analysis
time (s) getData(":pwr" ?result "tran")
Expression
(W) Value
0 5.74E-05 average(getData(":pwr"
5.73E-05
?result "tran"))
5.00E-06 5.75E-05
1.32E-05 5.76E-05
2.27E-05 5.77E-05
4.17E-05 5.79E-05
7.96E-05 5.84E-05
1.56E-04 5.90E-05
2.39E-04 5.93E-05
3.22E-04 5.91E-05
4.06E-04 5.85E-05
4.89E-04 5.76E-05
5.72E-04 5.64E-05
6.56E-04 5.55E-05
7.39E-04 5.51E-05
8.22E-04 5.54E-05
9.06E-04 5.62E-05
9.89E-04 5.73E-05
1.07E-03 5.83E-05
1.16E-03 5.90E-05

Overall Power =5.73*10^-5 W.

Outcome
Now through the observation if we look the all amplifiers designed till now, the single
stage amplifier will comparatively have less gain than multistage ,but in multistage
amplifier the gain with unchanged W/L ratio was around 25dB but when the Width or
W/L ratio is changed from normal which was 120nm to 240nm for a single
transistor ,overall gain increased and the maximum gain observed till now is 28dB.
Comparison of Gain for all designs

Gain (dB)
30 27
25
25
20
20
15
10
5
5
0
45nm 90nm Multistage
-5
-10 -7

-15
-15
-20

Common Mode Differential Mode Changed W/L

Power Analysis

Technology Node Average Power(uW)

45nm 2.01*10^-5
90nm 7.25*10^-5
Multistage(90nm) 5.78*10^-5
 Future Scope and Application
 Telecommunications: Vital for signal transmission and processing in
communication networks.
 Wireless Communication: Essential for improving signal strength and
quality in 5G and beyond.
 Radar and Sensing Systems: Integral in detecting and tracking objects
across military, aerospace, and automotive sectors.
 Medical Devices: Used in MRI machines, ultrasound, and medical imaging
equipment for signal amplification.
 Instrumentation and Measurement: Crucial for precise signal analysis in
various industries like manufacturing and automotive.
 Consumer Electronics: Found in audio amplifiers, smartphones, and TV
signal processing for enhanced user experiences.

Conclusion
In conclusion, this whole project was designed on Cadence virtuoso as it is powerful EDA
to analyze and observe all required details. The aim to design the high gain amplifier on
different technology nodes which are 45nm and 90nm had been efficiently. Comparison
of Amplifier had been for both Common Mode and Differential mode to observe every
change in waveforms. Transient, DC, AC, Power along with Bandwidth and gain was
observed and recorded to analysis.
Additionally a multistage amplifier was also designed to compare and observe the gain
with respect to other designs, this also includes the above analysis .And a concept to
observe the change with variation in W/L ration was also tested and recoded. For a
better understanding of all related waveforms, tables, graph has been included in the
report .
The implementation was on CMOS level due to which every object was seamlessly
changeable with the requirement. The successful observation of the high gain
amplifier underscores the importance of innovation and collaboration
in advancing analog circuit design. It serves as to pushing the
boundaries of what is possible, propelling us towards new horizons of
achievement in field of VLSI and Electronics
As concluding this report, the depth knowledge gained and the lessons learned will
continue to guide us in future endeavors, and the journey with the high gain amplifier
not only expands the understanding of analog circuitry but also fuels the passion for
innovation and discovery.

References
1)Amir Baghi Rahin & Vahid Baghi Rahin (2016). A Low-Voltage and Low-Power Two-Stage Operational
Amplifier Using FinFET Transistors in International Academic Journal of Science and Engineering

2) Priti Gupta & Sanjay Kumar Jana (2021). Design of DTMOS based third-order Gm-C filter for fast
locking PLL in Analog Integrated Circuits and Signal Processing.