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Sequential Circuits

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16 views12 pages

Sequential Circuits

Uploaded by

manansakhiya3112
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Design of Sequential Circuits

Dr. P Sasipriya
Associate Professor
Introduction

Block diagram of Sequential Circuit


Inputs Outputs

Combinational Circuits

Memory

2/9/2024 P Sasipriya 2
Memory

• Cross coupled inverter holds the data.

• When we want to write a new data we can go for force writing by


implementing 2 input gate with external input.
• External input will change the data stored in latch

2/9/2024 P Sasipriya 3
Latches vs Flip-flop

There are two types of memory elements based on the type of


triggering that is suitable to operate it.
➢Latches
➢Flip-flops

Latches operate with enable signal, which is level sensitive.


Whereas, flip-flops are edge sensitive.

2/9/2024 P Sasipriya 4
NOR based SR

S R Q Q’(t)
R
Q 1 0 1 0
0 1 0 1
0 0 Q Q’
1 1 Indeterminate

Q’
S

2/9/2024 P Sasipriya 5
SR latch using compound CMOS logic
R

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NAND based SR Latch
S’ S’ R’ Q Q’(t)
Q
1 0 0 1
0 1 1 0
1 1 Q Q’
0 0 Indeterminate

R’ Q’

2/9/2024 P Sasipriya 7
SR Latch with Enable/ SR Flip-Flop
E S R Q Q’
1 1 0 1 0
1 0 1 0 1
1 0 0 Q Q’
1 1 1 Indeterminate
0 X X Q Q’

E is Enable signal activated with Logic ‘1’.

When it is logic ‘0’ , the latch is deactivated and maintains the same state.

E can also be Clock Pulse and this latch can be called as positive level triggered Latch
2/9/2024 P Sasipriya 8
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SR Flipflop using NAND gates

E S R Q Q’
1 1 0 1 0
1 0 1 0 1
1 0 0 Q Q’
1 1 1 Indeterminate
0 X X Q Q’

2/9/2024 P Sasipriya 10
D latch

E’ D Q Q’(t)
0 0 0 1
0 1 1 0
1 X Q Q’

2/9/2024 P Sasipriya 11
Thank You

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