NAAC Accredited ‘A++’ Grade

Affiliated to Anna University, Chennai

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

(B.E. (EEE) - Accredited by NBA – 6 years, II time)

LABORATORY MANUAL

U23EE309 DIGITAL SYSTEMS DESIGN LABORATORY

(For Third Semester B.E. - EEE Students)

Name : _________________________

Register No. : _________________________

Year / Section : _________________________

Batch No. : _________________________

Students Copy – Ver. Aug 2024

 CONTENTS

SN Content Page No.

1 Index iii
2 Vision, Missions & Quality Policy of the Institution iv
3 Vision, Missions, PEOs, PSOs & POs of EEE Department v
4 Safety Precautions and Laboratory rules vii
5 Guidelines for laboratory Record notebook viii
6 Laboratory Syllabus & list of lab requirements ix
7 Theory Syllabus xi

SN Experiments (Hardware) Page No.

1 Verification of Digital Logic ICs 1
2 Implementation of Boolean Functions (DeMorgan’s Theorem) 7
3 Design of Code Converters 11
4 Design of Adders and Subtractors 15
5* Implementation of Decoder, Demultiplexer and Multiplexer 19
6 Conversion of flip-flops 25
7 Implementation of Shift Registers 29
8 Design and Implementation of Asynchronous Counters 33
9 Design and Implementation of Synchronous Counters 37
10* Implementation of Ring counter and Johnson counter 43
A1 Pin Diagram and Function Table of Digital ICs 48
A2 ICs Nomenclature 51
A3 ICs and BreadBoard Usage Instructions 53
* Beyond Syllabus Experiments

Experiment order
Hardware : (1) (2 & 3) (4) (6) (7 & 8) (9) 6 sessions + *(10, 5)
Software : (1) (2 & 3) (4) (6 & 7) (8 & 9) 5 sessions + *(10 & 5)

ii
 Index

Exp. Page.
Date Name of the Experiment Marks Sign.
No. No.

iii
 SONA COLLEGE OF TECHNOLOGY
VISION - SCT
To become an institute of great repute, in the fields of Science, Engineering, Technology and
Management studies, by offering a full range of programmes of global standard to foster research,
and to transform the students into globally competent personalities.
MISSIONS - SCT
Sona College of Technology is a private engineering institution that offers engineering
degree programmes at under graduate level and post graduate level, computer applications and
management studies at post graduate level and doctoral programmes in the areas of engineering
and science and humanities.
The college aims to provide a full-fledged education, to produce graduates with competency
to excel in the organizations they serve and to cater to the needs of the community as a whole. Our
mission for next three years will be
✓ To offer Graduate, Post-graduate, Doctoral and other value-added programmes beneficial for
the students
✓ To establish state-of-the-art facilities and resources required to achieve excellence in teaching-
learning, and supplementary processes
✓ To provide Faculty and Staff with the required qualification and competence and to provide
opportunity to upgrade their knowledge and skills
✓ To motivate the students to pursue higher education, appear for competitive exams, and other
value added programmes for their holistic development
✓ To provide opportunities to the students and bring out their inherent talent
✓ To establish Centres of excellence in the emerging areas of research
✓ To have regular interaction with the Industries in the area of R & D, and offer consultancy,
training and testing services
✓ To offer Continuing education, and Non-formal vocational education programmes that are
beneficial to the society
✓ To inculcate entrepreneurial attitude in the students and to provide a platform to start their
own startups in the campus.
Quality Policy - SCT
SONA COLLEGE OF TECHNOLOGY is committed to provide quality education to the
students enabling them to excel in the fields of Science, Engineering, Technology and Management
to cater to the changing and challenging needs of society and industry through the following
initiatives:
✓ Contributing to the academic standing and overall knowledge development of the students
✓ Maintaining state-of-the-art infrastructure and congenial learning environment
✓ Enhancing the competence of the faculty to a very high level and to make them adopt all
modern and innovative methods in teaching-learning process
✓ Inculcating moral and ethical values among the students and staff
✓ Collaborating with industry, other institutions and organizations for mutual benefit
✓ Promoting Research and Development programme for the growth of the economy
✓ Disseminating technical knowledge in the region through continuing education programmes
✓ Ensuring continual improvement of Quality Management System

iv
 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
VISION - EEE
To be a leader in electrical and electronics engineering education and training by producing
globally competent graduates who excel in their chosen careers and are successfully involved in
innovative research and entrepreneurship with a strong commitment towards societal development.
MISSIONS - EEE
• To offer undergraduate, postgraduate and doctoral programmes in EEE through formal, non-
formal, part-time and full-time delivery modes.
• To provide state-of-the-art resources that contribute to the achievement of excellence in
teaching-learning, research and development activities.
• To organise faculty development programmes in need-based areas to enhance their capability
in teaching, publishing research papers in peer reviewed journals, filing patents and for their
overall career enhancement.
• To provide special learning opportunities and a conducive environment for students to enhance
their skills in technical, co-curricular and extra-curricular activities, soft skills and personality
traits, and entrepreneurship.
• To enhance the research facilities, training and consultancy services to bridge the gap between
industry and academia.
• To offer continuing education and need-based skill development programmes to the students
for sustainable improvement and development of the society.
PROGRAMME EDUCATIONAL OBJECTIVES (PEOs) - EEE
The Electrical and Electronics Engineering programme of Sona College of Technology will
prepare its graduates to,
I. apply their knowledge and skills to provide solutions to electrical and electronics engineering
problems in industry and governmental organizations or to enhance student learning in
educational institutions.
II. work as a team with a sense of ethics and professionalism, and communicate effectively to
manage cross-cultural and multidisciplinary teams.
III. update their knowledge continuously through lifelong learning that contributes to personal,
organizational and societal growth.
PROGRAMME SPECIFIC OUTCOMES (PSOs) - EEE
On completion of the B.E. (Electrical and Electronics Engineering) degree the graduates will
be able to
➢ apply the fundamental knowledge of mathematics, science, electrical and electronics
engineering to analyse and solve the complex problems in electrical, electronics and allied
interdisciplinary areas.
➢ design, develop and implement electrical and electronics and allied interdisciplinary projects to
meet the demands of industry and to provide solutions to the current real time problems.

v
PROGRAMME OUTCOMES (POs) [defined by NBA]
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. Design / development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of
the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

vi
 SAFETY PRECAUTIONS
1. Wear leather shoes and overcoat.
2. Ensure that the main switch of the table is in the OFF position at time of giving connections.
3. Verify the connection before switching ON.
4. Switch OFF the main switch of the worktable in case of emergency.
5. Use good wires.

TROUBLESHOOTING HINTS
1. Be sure that the power is turned ON.
2. Be sure the ground/neutral connections are common.
3. Be sure the circuit you build is identical to the circuit diagram (Do node by node check).
4. Be sure that the supply voltages are correct. Be sure that the equipment is set up correctly and
that you are measuring the proper parameters.
5. If steps 1 through 4 are correct then you probably have used a component with the wrong value
or one that doesn’t work. To find your problem you must trace through the voltages in your
circuit node by node and compare the signal you expect to have.

LABORATORY SAFETY RULES & INSTRUCTIONS

1) SAFETY is of paramount importance in the Electrical Engineering Laboratories. Electricity
NEVER EXCUSES careless persons. So, follow safety practices in the laboratory.
(Electricity is a good servant but a bad master).
2) Avoid direct contact with any voltage source and power line voltages. (Otherwise, any such
contact may subject you to electrical shock).
3) Wear rubber-soled shoes. (To insulate you from the earth so that even if you accidentally
contact a live point, current will not flow through your body to earth).
4) Wear a laboratory coat and avoid loose clothing. (Loose clothing may get caught on
equipment and this may lead to an accident). Girl students should have their hair tucked under
their coats or have it in a knot.
5) Do not wear any metallic rings, bracelets, wristwatches, and neck chains. (When you move
your body, such conducting items may touch a live point and be subject to electric shock).
6) Be certain that your hands are dry and that you are not standing on the wet floor. (Wet parts
of the body reduce the contact resistance thereby increasing the severity of the shock).
7) Ensure that the power is OFF before you start connecting the circuit. (Otherwise, you will be
touching the live parts in the circuit).
8) Get your circuit diagram approved by the faculty member and connect the circuit strictly as
per the approved circuit diagram.
9) Do not make any change in the connection without the approval of the faculty member.
10) Switch the power to your circuit and equipment only after getting them checked up and
approved by the staff member.
11) Measure with one hand in your pocket. (To avoid shock in case you accidentally touch two
points at different potentials with your two hands).
12) In case you notice any abnormal condition in your circuit (like insulation heating up, smoke
etc.), switch OFF your circuit immediately and inform the faculty member.
13) After completing the experiment show your readings to the faculty member and switch OFF
the power after getting approval.

vii
 GENERAL GUIDELINES FOR LABORATORY RECORD NOTEBOOK

The laboratory notebook is a record of all work on the experiment. This record should
be sufficiently complete so that you or anyone else of similar technical background can
duplicate the experiment and data by simply following your laboratory notebook. Record
everything directly into the observation notebook during the experiment. Do not trust your
memory to fill in the details later.
Organization of your notebook is important. Descriptive headings should be used to
separate and identify the various parts of the experiment. A neat, organized, and complete
record of an experiment is just as important as the experimental work.
1. Heading: The experiment identification (number) should be at the top of each page. The
date should be at the top of the first page of each day's experimental work.
2. Aim: A brief but complete statement of what you intend to find out or verify in the
experiment should be at the beginning of each experiment.
3. Equipment List: List those items of equipment which have a direct effect on the accuracy
of the data. It may be necessary later to locate specific items of equipment for rechecks if
discrepancies develop in the results.
4. Procedure: In general, lengthy explanations of procedures are unnecessary. Be brief. Short
commentaries alongside the corresponding data may be used. Keep in mind the fact that
the experiment must be reproducible from the information given in your notebook.
5. Circuit Diagram: A circuit diagram should be drawn and labelled so that the actual
experiment circuitry can be easily duplicated at any time in the future. Be especially careful
to record all circuit changes made during the experiment.
6. Data: Think carefully about what data is required and prepare suitable data tables. Record
instrument readings directly. Do not use calculated results in place of direct data; however,
calculated results may be recorded in the same table as the direct data. Data tables should
be identified, and each data column labelled and headed by the proper units of measure.
7. Calculations: Not always necessary but equations and sample calculations are often given
to illustrate the treatment of the experimental data in obtaining the results.
8. Results: The results should be presented in a form that makes the interpretation easy. Large
amounts of numerical results are generally presented in graphical form. Tables are
generally used for small amounts of results. Theoretical and experimental results should
be arranged in the same table for easy correlation of results.

Record Notebook Organization

Recommended Notebook: Right side ruled & left side unruled; min. 100 pages.
Left Side : Expression, Circuit Diagram; Tabulation and Program.
Right Side : Exp. No., Date, Title, Aim, Apparatus, Theory, Procedure, and Result.
Either Side : Design, and Pin diagram.

Observation Notebook: Unruled notebook; 60 pages. Contents can be written on either side.
Theory and Procedure need not be written in the observation notebook.

viii
 U23EE309 DIGITAL SYSTEMS DESIGN LABORATORY 0 0 2 0 1

List of Experiments
Implement the circuits using Digital ICs and Verilog HDL
Design of Combinational Circuits
1) Verification of logic gates.
2) Implementation of Boolean functions.
3) Implementation of code converters.
4) Implementation of half and full Adders.
5) Implementation of half and full subtractors.
Design of Sequential Circuits
6) Verification of (D & JK) Flip-flops.
7) Conversion of D flip-flop to JK / T flip-flop.
8) Implementation of SISO & SIPO Shift Registers.
9) Design and implementation of asynchronous counters.
10) Design and implementation of synchronous counters.
Total: 30 Hours

List of Equipments
For a batch of 15 teams (each group shall consist of 3 or 4 students)
SN Description of the Equipment Quantity
For Hardware Experiments
1. Digital IC trainer kit with power cord 15
Hex inverters (IC 7404); Quad 2-input AND gate (IC 7408);
2. Each 15
Quad 2-input OR gate (IC 7432); Quad XOR gates (IC 7486)
3. Dual positive edge triggered D flip-flop (IC 7474) 30
4. Dual positive edge triggered JK flip-flop (IC 7476) 15
5. Single-strand wires -
For Software Experiments
6. Computer with Windows OS 45
7. Verilog HDL software (Xilinx Vivado / Icarus Verilog) Freeware
8. Printer 1
Note: Maintaining 10% to 25% of equipment as backup is recommended.

ix
 U23EE309 – DIGITAL SYSTEMS DESIGN LABORATORY
Course Outcomes (COs) mapping with List of Experiments

CO 1 : implement the combinational circuits using digital ICs and Verilog HDL.
SN List of Experiments
1 Verification of logic gates
2 Implementation of Boolean functions using logic gates
3 Design and implementation of code converters
4 Design and Implementation of half and full Adders
5 Design and Implementation of half and full subtractors

CO 2 : implement the sequential circuits using digital ICs and Verilog HDL.
SN List of Experiments
1 Verification of (D & JK) Flip-flops
2 Conversion of D flip-flop to JK & T flip-flop
3 Implementation of SISO & SIPO Shift Registers
4 Design and implementation of asynchronous counters
5 Design and implementation of synchronous counters

CO 3 : implement a digital circuit for given logic using digital ICs and Verilog HDL.
SN List of Experiments
1 Realtime problems to be solved using digital combinational circuits
2 Realtime problems to be solved using digital sequential circuits

Course Outcomes (COs) PROGRAMME OUTCOMES (PO) PSO

After successful completion of the course, the
1 2 3 4 5 6 7 8 9 10 11 12 1 2
students will be able to
1 implement the combinational circuits using
3 3 3 3 3 1 - - 3 3 - 2 3 3
digital ICs and Verilog HDL.
2 implement the sequential circuits using
3 3 3 3 3 1 - - 3 3 - 2 3 3
digital ICs and Verilog HDL.
3 implement a digital circuit for given logic
3 3 3 3 3 1 - - 3 3 - 2 3 3
using digital ICs and Verilog HDL.

U23EE305 DIGITAL SYSTEMS DESIGN

Course Outcomes (COs) PROGRAMME OUTCOMES (POs) PSO
After successful completion of the course, the
students will be able to 1 2 3 4 5 6 7 8 9 10 11 12 1 2
1 optimise logic functions using minimisation
techniques & compare the properties of digital 3 3 2 2 - 1 - - - 2 - 2 3 3
families.
2 implement the combinational logic circuits
3 3 3 3 - 1 - - - 2 - 2 3 3
using logic gates.
3 implement the synchronous sequential logic
3 3 3 3 - 1 - - - 2 - 2 3 3
circuits using flip-flops and gates.
4 implement the asynchronous sequential logic
3 3 3 3 - 1 - - - 2 - 2 3 3
circuits using flip-flops and gates.
5 implement the digital systems using Verilog
3 3 2 2 3 1 - - - 2 - 2 3 3
HDL.
* 3 – Strong; 2 – Medium; 1 – Weak.

x
 U23EE305 DIGITAL SYSTEMS DESIGN 2 1 0 0 3
COURSE OUTCOMES
At the end of this course, the students will be able to
CO1) optimise logic functions using minimisation techniques & compare the properties of digital families.
CO2) implement the combinational logic circuits using logic gates.
CO3) implement the synchronous sequential logic circuits using flip-flops and gates.
CO4) implement the asynchronous sequential logic circuits using flip-flops and gates.
CO5) implement the digital systems using Verilog HDL.

UNIT I BOOLEAN ALGEBRA AND LOGIC FAMILIES 9

Number systems: Binary, Octal, and Hexa-Decimal – Binary codes: Gray and BCD – Logic gates –
Boolean algebra: Laws and theorems, Simplification – Minterm and Maxterm – Minimization using
K-Map (up to 5 variables). Logic families: Terminologies, Types – TTL, ECL, CMOS – Comparison.
UNIT II COMBINATIONAL LOGIC CIRCUITS AND PLDS 9
Analysis and Design procedure – Design of half, full adders and subtractors – Code Converters
(Binary, Gray & BCD) – Decoder, Demultiplexer, and Multiplexer – Realization of combinational
circuits using decoders and multiplexer – Hazards in combinational circuits: Types, hazards free
realisation. PLDs: PROM, PAL, and PLA – Comparison – Implementation of Boolean functions
using PLDs.
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC CIRCUITS 9
SR Latch – Triggering – Flip-flops: SR, JK, D, and T – Conversion of flip-flops – Clocked sequential
circuits: Moore and Mealy model – Analysis of synchronous circuits – Design of synchronous
circuits: State reduction – Shift registers (SISO, SIPO, PISO, and PIPO) – Synchronous counters (Up,
Down, Modulo and Sequence).
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC CIRCUITS 9
Introduction to Asynchronous circuits – Analysis procedure: Transition table, flow table – Circuits
with SR latches – Design procedure: Reduction of the primitive flow table, Implication table, Merger
diagram – Race conditions, Race-free state assignment – Asynchronous counters (Up, Down, and
Modulo).
UNIT V VERILOG HDL FOR DIGITAL CIRCUITS 9
Introduction to HDL – Types – Module and Ports declaration – User-defined primitives – Gate level
modeling – Dataflow modeling – Behavioral modeling – Test bench – Truth table model – State
diagram-based models. Verilog code for logic gates, Boolean functions, half and full adders, half and
full subtractors, flip-flops, shift registers, and counters.
Lecture: 30, Tutorial: 15, Total: 45 Hours
TEXT BOOKS:
1. Morris Mano M and Michael D. Ciletti, “Digital Design”, Pearson Education, 6th Edition, 2018.
2. Anand Kumar A, “Fundamentals of Digital Circuits”, PHI Learning, 4th Edition, 2018.
REFERENCE BOOKS:
1. Thomas L. Floyd, “Digital Fundamentals”, Pearson India, 11th Edition, 2018.
2. J Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design”, McGraw
Hill, 3rd edition, 2014.
3. Ananda Natarajan R, “Digital Design”, PHI Learning, 2015.
4. Bhasker J, “A Verilog HDL Primer”, BS Publications, 3rd Edition, 2008.

xi
 Ex. No:
VERIFICATION OF DIGITAL LOGIC ICs
Date:

Aim
To verify the truth table of logic gates, and flip-flops.

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 Hex NOT gate (IC 7404) 1
3 Quad 2-input AND gate (IC 7408) 1
4 Quad 2-input OR gate (IC 7432) 1
5 Quad 2-input Ex-OR gate (IC 7486) 1
6 Triple 3-input AND gate (IC 7411) 1
7 Dual +ve edge triggered D flip-flop (IC 7474) 1
8 Dual +ve edge triggered JK Flip-flop (IC 7476) 1
9 Single strand wires -

Theory
Logic gates are the basic building blocks of any digital system. It is an electronic circuit
having one or more than one input and only one output. The relationship between the input and the
output is based on a certain logic. A logic gate is an idealized model of computation or physical
electronic device implementing a Boolean function, a logical operation performed on one or more
binary inputs that produce a single binary output.
Digital Logic Gates can be made from discrete components such as Resistors, Transistors and
Diodes to form RTL (resistor-transistor logic) or DTL (diode-transistor logic) circuits, but today’s
modern digital 74xxx series integrated circuits are manufactured using TTL (transistor-transistor
logic) based on NPN bipolar transistor technology or the much faster and low power CMOS based
MOSFET transistor logic used in the 74Cxxx, 74HCxxx, 74ACxxx and the 4000 series logic chips.

Combinational circuits consist of Logic gates. These circuits operate with binary values. The
result is that combinational logic circuits have no feedback, and any changes to the signals being
applied to their inputs will immediately have an effect at the output. In other words, in a
Combinational Logic Circuit, the output is always dependent on the combination of its inputs. Thus,
a combinational circuit is memoryless.

1
Sequential Circuits
A flip flop is an electronic circuit with two stable states that can be used to store binary data.
The stored data can be changed by applying varying inputs. Flip-flops and latches are used as data
storage elements. It is the basic storage element in sequential logic. Flip-flops can be divided into
common types: SR ("set-reset"), D ("data" or "delay"), T ("toggle"), and JK. The flip-flops are used
in digital electronic circuits and applications like Counters, Frequency Dividers, Shift Registers and
Storage Registers.
Sequential circuit outputs depend not only on the combination of present inputs but also on
the previous outputs. Previous output is nothing but the present state. Sequential circuits contain
combinational circuits along with memory storage elements. Some sequential circuits may not contain
combinational circuits, but only memory elements. The two types of sequential circuits are
Asynchronous sequential circuits and Synchronous sequential circuits.

Triggering
The clock signal is a periodic signal and its ON time and OFF time need not be the same.
This signal stays at a logic High of 5 V for some time and stays at a logic Low of 0 V. All sequential
circuits are operated with the clock signal. The two possible types of triggering that are used in
sequential circuits are level triggering and Edge triggering.

2
Circuit Diagram Truth Table

NOT gate (IC 7404)

Input Output
A Y = A’
0 1
1 0

AND gate (IC 7408)

Inputs Output
A B Y=A•B
0 0 0
0 1 0
1 0 0
1 1 1

OR gate (IC 7432)

Inputs Output
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1

XOR gate (IC 7486)

Inputs Output
A B AB
0 0 0
0 1 1
1 0 1
1 1 0

3
Circuit Diagram Truth Table

3-input AND gate (IC 7411)

Inputs Output
A B C Y=A•B•C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

D flip-flop (IC 7474)

Inputs Output
PRE’ CLR’ D Q+
0 X X 1
1 0 X 0
1 1 0 0
1 1 1 1
Q’ is always complement to Q

Q+ = D

JK flip-flop (IC 7476)

Inputs Output
PRE’ CLR’ J K Q+
0 X X X 1
1 0 X X 0
1 1 0 0 NC
1 1 0 1 0
1 1 1 0 1
1 1 1 1 T
* NC – No Change T – Toggle
Q’ is always complement to Q

Q+ = JQ’ + K’Q

4
 Digital ICs Pin Diagram

NOT gate (IC 7404) 3-input AND gate (IC 7411)

AND gate (IC 7408) D Flip-Flop (IC 7474)

OR gate (IC 7432)

JK Flip-Flop (IC 7476)

EX-OR gate (IC 7486)

Simplified Representation

5
 Level triggering: If the sequential circuit is operated with the clock signal when it is in Logic
High, then that type of triggering is known as Positive level triggering. If the sequential circuit is
operated with the clock signal when it is in Logic Low, then that type of triggering is known as
Negative level triggering.
Edge triggering: If the sequential circuit is operated with the clock signal that is transitioning
from Logic Low to Logic High, then that type of triggering is known as Positive edge triggering. It
is also called as rising edge triggering. If the sequential circuit is operated with the clock signal that
is transitioning from Logic High to Logic Low, then that type of triggering is known as Negative edge
triggering. It is also called as falling edge triggering.
Triggering Positive Negative

Level

Edge

Positive and Negative Logic

The binary signal at the inputs and outputs of any gate has one of two values, except during
transition. One signal value represents logic 1 and the other logic 0. Choosing the high‐level H to
represent logic 1 defines a positive logic system. Choosing the low‐level L to represent logic 1 defines
a negative logic system. The conversion from positive logic to negative logic and vice versa is
essentially an operation that changes 1’s to 0’s and 0’s to 1’s in both the inputs and outputs of a gate.

Result

***** ***** ***** ***** *****

1) This experiment didn’t discuss the NAND & NOR gates and SR & T Flip-flops. Are
such gates & flip-flops ICs available in the market? If yes, find the IC number and pin
diagram.

6
 Ex. No: IMPLEMENTATION OF BOOLEAN FUNCTIONS
Date: (DEMORGAN’S THEOREM)

Aim
To construct the given Boolean functions using Logic Gates and to verify its truth table.

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 NOT gate (IC 7404) 1
3 AND gate (IC 7408) 1
4 OR gate (IC 7432) 1
5 Single strand wires -

DeMorgan’s Theorem
Boolean theorems and laws are used to simplify the various logical expressions. In a digital
designing problem, a unique logical expression evolved from the truth table. If this logical expression
is simplified the designing becomes easier. The Boolean algebra is mainly used in digital electronics,
set theory and digital electronics. It is also used in all modern programming languages.
There are a few basic laws and theorems of Boolean algebra, some of which are familiar to
everyone such as Cumulative Law, Associative Law, Distributive law, DeMorgan’s Theorems,
Double Inversion law and Duality Theorems.
DeMorgan's theorem is a powerful tool in digital design. It defines the uniformity between
the gates with the same inverted input and output. It is used to implement basic gate operations like
NAND gate and NOR gate. Demorgan’s theorem is mostly used in digital programming and making
digital circuit diagrams. The theorem explains that the complement of the product of all the terms is
equal to the sum of the complement of each term. Likewise, the complement of the sum of all the
terms equals the product of each term's complement.
̅̅̅̅̅̅̅̅
𝐀+𝐁=𝐀 ̅ •𝐁
̅ ̅̅̅̅̅̅̅
𝐀 •𝐁=𝐀 ̅+𝐁
̅
According to DeMorgan's theorem, a NAND gate is equivalent to an OR gate with inverted
inputs. Similarly, a NOR gate is equivalent to an AND gate with inverted inputs.

Duality Theorems
It states that every algebraic expression deducible from the postulates of Boolean algebra
remains valid if the operators and identity elements are interchanged. The new Boolean relation can
be derived with the help of the Duality theorem.

7
 Verification of DeMorgan’s Theorem 1

Boolean Expression
Y1 = ̅̅̅̅̅̅̅
A+B ̅·B
Y2 = A ̅

Circuit Diagram

Truth Table

Inputs Output 1 Output 2

A B A+B Y1 = (A + B)’ A’ B’ Y2 = A’ • B’
0 0
0 1
1 0
1 1

8
 Verification of DeMorgan’s Theorem 2

Boolean Expression
Y1 = ̅̅̅̅̅̅
A·B ̅+B
Y2 = A ̅

Circuit Diagram

Truth Table

Inputs Output 1 Output 2

A B A•B Y1 = (A • B)’ A’ B’ Y2 = A’ + B’
0 0
0 1
1 0
1 1

9
 According to this theorem for the given Boolean relation, the new Boolean relation can be
derived by the following steps:
➢ Changing each OR sign to an AND sign.
➢ Changing each AND sign to an OR sign.
➢ Complementing each 0 or 1 appearing in the given Boolean identity.

Truth Table
The input and output binary table of a Boolean function that shows the output for all the
possible combinations of inputs. For the ‘n’ number of inputs, there are a ‘2n’ number of possible
input combinations.

Procedure
1) The circuit is designed as per the problem specification using logic gates and/or flip-flops.
2) Connections are given as per the circuit diagram in the digital IC trainer kit.
3) Binary inputs are applied as per the truth table.
4) The output of the glowing LED is verified with the truth table.

Result

***** ***** ***** ***** *****

1) Can you understand the duality in Boolean expressions?
2) Can you draw a logic circuit for any given Boolean expression?

10
 Ex. No:
DESIGN OF CODE CONVERTERS
Date:

Aim
To design and verify the operations of Binary to Gray code & Gray to Binary code converters
using logic gates.

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 Ex-OR gate (IC 7486) 1
3 Single strand wires -

Theory
The communication system requires various types of data codes for security purposes, so we
need some code converters to convert the actual data into some other form. The commonly used code
converters are binary code to Gray code and BCD to Excess 3 code and vice versa converters.

Binary code
A binary code represents text, computer processor instructions, or any other data using a two-
symbol system. The two-symbol system used is often "0" and "1" from the binary number system.
The binary code assigns a pattern of binary digits, also known as bits, to each character, instruction,
etc.

Gray Code
Gray code also known as Cyclic Code, Reflected Binary Code (RBC), Reflected Binary (RB)
or Gray code – is defined as an ordering of the binary number system such that each incremental
value can only differ by one bit. In Gray code, while traversing from one step to another step only
one bit in the code group changes. That is to say that two adjacent code numbers differ from each
other by only one bit.

11
 Binary to Gray Code Converter
Boolean Expression
𝐆𝟑 = B3 𝐆𝟐 = B3 ⨁ B2
𝐆𝟏 = B2 ⨁ B1 𝐆𝟎 = B1 ⨁ B0

Circuit Diagram

Truth Table
Decimal Binary Input Gray Output
min. B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

12
 Gray to Binary Code Converter
Boolean Expression
𝐁𝟑 = G3 𝐁𝟐 = G3 ⨁ G2
𝐁𝟏 = G3 ⨁ G2 ⨁ G1 𝐁𝟎 = G3 ⨁ G2 ⨁ G1 ⨁ G0

Circuit Diagram

Truth Table
Decimal Gray Input Binary Output
min. G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

13
Applications of Gray Code
The Gray code is used in a few specific applications. The main applications include being
used in analog to digital converters, as well as being used for error correction in digital
communication. Gray code is used to minimize errors in converting analog signals to digital signals.
Some other applications of Gray code: Boolean circuit minimization, Communication between clock
domains, Error correction, Genetic Algorithms, Mathematical puzzles, and Position encoders.
Advantages of Gray Code
➢ Better for error minimization in converting analog signals to digital signals.
➢ Reduces the occurrence of “Hamming Walls” (undesirable state) when used in GAs.
➢ Can be used to minimize a logic circuit.
➢ Useful in clock domain crossing.
Disadvantages of Gray Code
➢ Not suitable for arithmetic operations.
➢ Limited practical use outside of a few specific applications.

Procedure
1) The circuit is designed as per the problem specification using logic gates and/or flip-flops.
2) Connections are given as per the circuit diagram in the digital IC trainer kit.
3) Binary inputs are applied as per the truth table.
4) The output of the glowing LED is verified with the truth table.

Result

***** ***** ***** ***** *****

1) What is the importance of using Gray code?
2) Try to design and implement the Binary to BCD code converter and vice versa.

14
 Ex. No:
DESIGN OF ADDERS AND SUBTRACTORS
Date:

Aim
To Design and Construct the following functions using Logic Gates and to verify the truth
table. (i) Half Adder; (ii) Full Adder; (iii) Half Subtractor and (iv) Full Subtractor.

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 NOT Gate (IC 7404) 1
3 AND Gate (IC 7408) 1
4 OR Gate (IC 7432) 1
5 Ex-OR Gate (IC 7486) 1
6 Single strand wires -

Theory
Half Adder
A basic module used in binary arithmetic elements is the half adder. The function of half adder
is adding two binary digits producing a sum and carry. These are two inputs to the half-adder
designated sum and carry. The half-adder performs binary addition operations for two binary inputs.
This is an arithmetic addition, not a logical or Boolean addition.
If either of the inputs is a ‘1’ but not both, the output on the Sum will be ‘1’.
If both the inputs are 1’s then the output on the C will be 1 for other states, there will be a ‘0’
output on the carry line. The relationship can be written as
Sum, S = A  B Carry out, Cout = A • B

Full Adder
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. The
full adder accepts three inputs and generates a sum output and carries output. The relationship can be
written as
Sum, S = (A  B)  C Carry out, Cout = AB + BC + AC = AB + (A  B) Cin
The full Adder can be constructed using two Half Adders and an OR Gate.

15
 Half Adder
Boolean Expression
𝐒=A⨁B 𝐂𝐨𝐮𝐭 = A · B
Circuit Diagram

Truth Table
Inputs Outputs
A B Cout = AB S=AB
0 0
0 1
1 0
1 1

Full Adder
Boolean Expression
𝐒 = A ⨁ B ⨁ Cin 𝐂𝐨𝐮𝐭 = AB + BCin + ACin = (A ⨁ B)Cin + AB
Circuit Diagram

Truth Table
Inputs Outputs
A B Cin Cout = AB + (A  B)Cin S = A  B  Cin
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

16
 Half Subtractor
Boolean Expression
𝐃=A⨁B ̅·B
𝐁𝐨𝐮𝐭 = A
Circuit Diagram

Truth Table
Inputs Outputs
A B Bout = A’B D=AB
0 0
0 1
1 0
1 1

Full Subtractor
Boolean Expression
𝐃 = A ⨁ B ⨁ Cin ̅B + A
𝐁𝐨𝐮𝐭 = A ̅ Bin + BBin = (A
̅̅̅̅̅̅̅̅ ̅B
⨁ B)Bin + A
Circuit Diagram

Truth Table
Inputs Outputs
A B Bin Bout = (A  B)’Bin + A’B D = A  B  Bin
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

17
Half Subtractor
A Half Subtractor is a combinational circuit that subtracts two bits and produces their
difference. It also has an output to specify if a 1 has been borrowed. Designate the minuend bit by A
and the subtrahend bit by B. To perform A - B, we have to check the relative magnitude of A and B.
The result is called the difference bit. The half subtractor needs two outputs. One output generates
the difference and will be designated by the symbol D. The second output, designated Bout for borrow,
generates the binary signal that informs the next stage that a 1 has been borrowed.
Difference, D = A  B Borrow out, Bout = A’ • B

Full Subtractor
A full subtractor is a combinational circuit that performs the subtraction between two bits,
taking into account that 1 has been borrowed by a lower significant stage. The circuit has three inputs
and two outputs. The three inputs A, B, and Bin denote the minuend, subtrahend and previous borrow
respectively. The two outputs D and Bout represent the difference and output borrow respectively.
Difference, D = (A  B)  Bin Borrow out, Bout = A’B + BBin + A’Bin = A’B + (A  B)’Bin
The full subtractor can be constructed using two Half subtractors and an OR Gate.

Procedure
1) The circuit is designed as per the problem specification using logic gates and/or flip-flops.
2) Connections are given as per the circuit diagram in the digital IC trainer kit.
3) Binary inputs are applied as per the truth table.
4) The output of the glowing LED is verified with the truth table.

Result

***** ***** ***** ***** *****

1) Can you understand the full adder/subtractor consisting of the half adders/subtractors?
2) Identify that a minor change in adder circuits forms the subtractor circuits.
3) Is a 3-input or 4-input Ex-OR gate available in the market?

18
 Ex. No: IMPLEMENTATION OF DECODER, DEMULTIPLEXER AND
Date: MULTIPLEXER

Aim
To design and implement the decoder, demultiplexer and multiplexer circuits.

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 NOT gate (IC 7404) 1
3 AND gate (IC 7408) 1
4 OR gate (IC 7432) 1
5 3-i/p AND gate (IC 7411) 2
6 Single strand wires -

Theory
Decoder:
A binary decoder is a digital circuit that converts a binary code into a set of outputs. The
binary code represents the position of the desired output and is used to select the specific output that
is active. Binary decoders are the inverse of encoders and are commonly used in digital systems to
convert a serial code into a parallel set of outputs.
In Digital Electronics, discrete quantities of information are represented by binary codes. A
binary code of n bits is capable of representing up to 2n distinct elements of coded information. The
name “Decoder” means to translate or decode coded information from one format into another, so a
digital decoder transforms a set of digital input signals into an equivalent decimal code at its output.
A decoder is a combinational circuit that converts binary information from n input lines to a maximum
of 2n unique output lines.
Advantages of using Binary Decoders
• Increased flexibility: Binary decoders provide a flexible way to select one of multiple outputs
based on a binary code, allowing for a wide range of applications.
• Improved performance: By converting a serial code into a parallel set of outputs, binary decoders
can improve the performance of a digital system by reducing the amount of time required to
transmit information from a single input to multiple outputs.
• Improved reliability: By reducing the number of lines required to transmit information from a
single input to multiple outputs, binary decoders can reduce the possibility of errors in the
transmission of information.

19
Demultiplexer
The demultiplexer is a combinational logic circuit designed to switch one common input line
to one of several separate output line. The data distributor, known more commonly as the
demultiplexer or “Demux” for short, is the exact opposite of the Multiplexer we saw in the previous
tutorial. The demultiplexer takes one single input data line and then switches it to any one of several
individual output lines one at a time. The demultiplexer converts a serial data signal at the input to
parallel data at its output lines.
A De-multiplexer is a combinational circuit that has only 1 input line and 2 n output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The information is
received from the single input lines and directed to the output line. Based on the values of the selection
lines, the input will be connected to one of these outputs. De-multiplexer is opposite to the
multiplexer.
Applications of Demultiplexer
➢ Communication System
➢ Arithmetic Logic Unit
➢ Serial to Parallel Converter

Multiplexer
It is a combinational circuit which have many data inputs and single output depending on
control or select inputs. For N input lines, 2n input lines, and ‘n’ selection lines are required.
Multiplexers are also known as Data n selectors, parallel to serial converters, many-to-one circuits,
and universal logic circuits”. Multiplexers are mainly used to increase amount of the data that can be
sent over the network within a certain amount of time and bandwidth.
Multiplexing is the generic term used to describe the operation of sending one or more
analogue or digital signals over a common transmission line at different times or speeds and as such,
the device we use to do just that is called the multiplexer.
Applications of Multiplexers
➢ Communication System
➢ Computer Memory
➢ Telephone Network
➢ Transmission from the Computer System of a Satellite

20
 2 x 4 Decoder Circuit
Boolean Expression
̅B
2 x 4 Decoder => 𝐘𝟎 = A ̅ ̅B
𝐘𝟏 = A ̅
𝐘𝟐 = AB 𝐘𝟑 = AB

Logic Circuit Diagram

Truth Table
Decimal Inputs Outputs
min. A B Y3 Y2 Y1 Y0
0 0 0
1 0 1
2 1 0
3 1 1

21
 DE-MULTIPLEXER CIRCUITS
Boolean Expression
1 x 4 De-Multiplexer => 𝐘𝟎 = DS̅1 ̅̅̅
S0 𝐘𝟏 = DS̅1 S0 𝐘𝟐 = DS1 ̅̅̅
S0 𝐘𝟑 = DS1 S0
1 x 2 De-Multiplexer => 𝐘𝟎 = DS̅̅̅0 𝐘𝟏 = DS0

Logic Circuit Diagram

1 x 4 De-Multiplexer 1 x 2 De-Multiplexer

Truth Table
1 x 4 De-Multiplexer (Data input, D = ___ )
Inputs Outputs
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 D
0 1 0 0 D 0
1 0 0 D 0 0
1 1 D 0 0 0

1 x 2 De-Multiplexer (Data input, D = ___ )

Input Outputs
S0 Y1 Y0
0 0 D
1 D 0
D – Data Input
* Set Data input as the initial condition.

22
 MULTIPLEXER CIRCUITS
Boolean Expression
4 x1 Multiplexer => Y = D0 S̅1 ̅̅̅
S0 + D1 S̅1 S0 + D2 S1 ̅̅̅
S0 + D3 S1 S0
2 x1 Multiplexer => Y = D0 ̅̅̅
S0 + D1 S0

Logic Circuit Diagram

4 x 1 Multiplexer 2 x 1 Multiplexer

Truth Table
4 x 1 Multiplexer (Data inputs, D0, D1, D2, D3 = _________ )
Inputs Output
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

2 x 1 Multiplexer (Data inputs, D0, D1 = _____ )

Input Output
S0 Y
0 D0
1 D1
D0, D1, D2, D3 – Data Inputs
* Set Data inputs as the initial condition.

23
Procedure
1) The circuit is designed as per the problem specification using logic gates and/or flip-flops.
2) Connections are given as per the circuit diagram in the digital IC trainer kit.
3) Binary inputs are applied as per the truth table.
4) The output of the glowing LED is verified with the truth table.

Result

***** ***** ***** ***** *****

1) What is the relationship between the decoder and demultiplexer?
2) Do we have dedicated ICs to perform the decoder, demultiplexer and multiplexer
operations? If yes find the IC numbers and function table.
3) It is simpler to design any combinational circuit using the decoder/demultiplexer
than using logic gates (Analyse the outputs of the decoder/demultiplexer). How?

24
 Ex. No:
CONVERSION OF FLIP-FLOPS
Date:

Aim
To convert and implement a given flip-flop to another flip-flop.
(1) Convert D flip-flop to JK flip-flop
(2) Convert D flip-flop to T flip-flop

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 D Flip-flop (IC 7474) 1
3 AND gate (IC 7408) 1
4 OR gate (IC 7432) 1
5 Single strand wires -

Theory
Flip-Flop
The flip-flop is a circuit that maintains a state until directed by input to change the state. The
flip-flop is popularly known as the basic digital memory circuit. It has two states logic-1 (High) and
logic-0 (Low). A flip-flop is a sequential circuit that consists of a single binary state of information
or data. It has two outputs that are of complement to each other. It is also known as a Bistable
Multivibrator. There are 4 flip-flops: SR, JK, D and T.

Conversion of Flip-flops
A flip-flop is an essential part of the design of sequential circuits. Any flip-flop can be used
to design a sequential circuit. Consider the case a design is available with a desired flip-flop, but the
flip-flop is not available. This case necessitates converting another available flip-flop to operate
similarly to the desired flip-flop so that the design can be implemented.
Any flip-flop can be converted into any other flip-flop with proper computation and design.

25
 D flip-flop to JK flip-flop
Design
Available Flip-flop => D Desired flip-flop => JK
Present Available FF
Desired FF inputs Next State
min State Excitation
J K Q Q+ D
0
1
2
3
4
5
6
7

̅ +𝐊
𝐃=𝐉𝐐 ̅𝐐

Logic Circuit Diagram

Truth Table
FF inputs Present State Next State
J K Q Q+ Comment
0 0 0 0
No Change
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 1
Toggle
1 1 1 0

26
 D flip-flop to T flip-flop
Design
Available Flip-flop => Desired flip-flop =>
Desired FF Present Available FF
Next State
min input State Excitation

0
1
2
3

𝐃=

Logic Circuit Diagram

Truth Table
FF input Present State Next State
T Q Q+ Comment
0 0 0
No Change
0 1 1
1 0 1
Toggle
1 1 0

27
Procedure for Flip-flop Conversion
Step 1: Write the Truth Table of the Desired Flip-Flop.
Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table.
Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-
Flop Appropriately to obtain the Conversion Table.
Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop.
Step 5: Design the Necessary Circuit and make the Connections accordingly.

Required FF
SR JK D T
Available FF
SR --- S = JQ’; R = KQ S = D; R = D’ S = TQ’; R = TQ
JK J = S; K = R --- J = D; K = D’ J=K=T
D D = S + R’Q D = JQ’ + K’Q --- D=T⨁Q
T T = SQ’ + RQ T = JQ’ + KQ T=D⨁Q ---

Applications of Flip-Flops
Frequency dividers, Counters, Storage registers, Shift registers, Data storage, Bounce
elimination switches, Data transfer, and Memory devices.

Procedure
1) The circuit is designed as per the problem specification using logic gates and/or flip-flops.
2) Connections are given as per the circuit diagram in the digital IC trainer kit.
3) Binary inputs are applied as per the truth table.
4) The output of the glowing LED is verified with the truth table.

Result

***** ***** ***** ***** *****

1) What is your understanding of this experiment?
2) Which flip-flop is the most versatile one? Why?
3) D flip-flop is just transferring the input to the output. What is the purpose of it?

28
 Ex. No:
IMPLEMENTATION OF SHIFT REGISTERS
Date:

Aim
To implement the Serial In Serial Out (SISO) and Serial In Parallel Out (SIPO) shift registers
and verify their operation using a truth table. (using D flip-flop or JK flip-flop).

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 D Flip-flop (IC 7474) 2
3 Single strand wires -

Theory
A register capable of shifting the binary information held in each cell to its neighbouring cell,
in a selected direction, is called a shift register. The logical configuration of a shift register consists
of a chain of flip‐flops in cascade, with the output of one flip‐flop connected to the input of the next
flip‐flop. All flip‐flops receive common clock pulses, which activate the shift of data from one stage
to the next.
Serial-in to Parallel-out (SIPO): the register is loaded with serial data, one bit at a time, with the
stored data being available at the output in parallel form.
Serial-in to Serial-out (SISO): the data is shifted serially “IN” and “OUT” of the register, one bit at
a time in either a left or right direction under clock control.
Parallel-in to Serial-out (PISO): the parallel data is loaded into the register simultaneously and is
shifted out of the register serially one bit at a time under clock control.
Parallel-in to Parallel-out (PIPO): the parallel data is loaded simultaneously into the register and
transferred together to their respective outputs by the same clock pulse.

29
 Serial In Serial Out (SISO) – Shift Register

Boolean Expression
Synchronized Clock DA = Data input QC = Data output
DB = QA DC = QB

Logic Circuit Diagram

Truth Table
Data Input = __________
Data In Clock Data Out
Initial
1
2
3
4
5
6
7
8
9

30
 Serial In Parallel Out (SIPO) – Shift Register

Boolean Expression
Synchronized Clock DA = Data input QA, QB, QC = Data outputs
DB = QA DC = QB
Logic Circuit Diagram

Truth Table
Data Input = __________
Data In Clock QA QB QC
Initial
1
2
3
4
5
6
7
8
9

31
Universal Shift Registers
These universal shift registers can perform any combination of parallel and serial input-to-
output operations but require additional inputs to specify the desired function and to pre-load and
reset the device. A commonly used universal shift register is the IC 74194. They can be configured
to respond to operations that require some form of temporary memory storage or for the delay of
information such as the SISO or PIPO configuration modes or transfer data from one point to another
in either a serial or parallel format. Universal shift registers are frequently used in arithmetic
operations to shift data to the left or right for multiplication or division.
Shift Register Summary
➢ A simple Shift Register can be made using only D-type flip-flops (FF), one FF for each data bit.
➢ The output from each FF is connected to the D input of the FF at its right.
➢ Shift registers hold the data in their memory which is moved or “shifted” to their required
positions on each clock pulse.
➢ Each clock pulse shifts the contents of the register one-bit position to either the left or the right.
➢ The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded
simultaneously in a parallel input (PI) configuration.
➢ Data may be removed from the register one bit at a time for a series output (SO) or removed all
at the same time from a parallel output (PO).
➢ One application of shift registers is in the conversion of data between serial and parallel, or
parallel to serial.
➢ Shift registers are identified individually as SIPO, SISO, PISO, PIPO, or as a Universal Shift
Register with all the functions combined within a single device.
Procedure
1) The circuit is designed as per the problem specification using logic gates and/or flip-flops.
2) Connections are given as per the circuit diagram in the digital IC trainer kit.
3) Binary inputs are applied as per the truth table.
4) The output of the glowing LED is verified with the truth table.

Result

***** ***** ***** ***** *****

1) What are the real-time applications of a shift register?
2) Can you design the shift registers using another flip-flop?
3) Can you design a SISO shift register to shift the data from Left to Right?

32
 Ex. No: DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS
Date: COUNTERS

Aim
To design and implement the following asynchronous (ripple) counters using D flip-flop and
verify its truth table. (a) 3-bit up counter; (b) 3-bit down counter.

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 D Flip-flop (IC 7474) 2
3 Single strand wires -

Theory
What is a Counter?
A counter is a device that can count any particular event based on how many times the
particular event(s) occurred. In a digital logic system or computers, this counter can count and store
the number of times any particular event or process have occurred, depending on a clock signal. The
most common type of counter is a sequential digital logic circuit with a single clock input and multiple
outputs. The outputs represent binary or binary-coded decimal numbers. Each clock pulse either
increases the number or decreases the number.
What is Asynchronous?
Asynchronous stands for the absence of synchronization. Something that does not exist or
occurring at the same time. In computing or telecommunication stream, Asynchronous stands for
controlling the operation timing by sending a pulse only when the previous operation is completed
rather than sending it in regular intervals.

Asynchronous Counters
Asynchronous counters are those whose output is free from the clock signal. Because the flip
flops in asynchronous counters are supplied with different clock signals, there may be a delay in
producing output. The required number of logic gates to design asynchronous counters is very small.
So, they are simple in design. Another name for Asynchronous counters is “Ripple counters”.
The number of flip flops used in a ripple counter is depends up on the number of states of the
counter (ex: Mod 4, Mod 2 etc.). The number of output states of the counter is called the “Modulus”
or “MOD” of the counter. The maximum number of states that a counter can have is 2n where n
represents the number of flip-flops used in a counter.

33
 3-bit Asynchronous (Ripple) UP Counter
Boolean Expression
Input / Output => Self-Starting Counter QAQBQC => Data Outputs
Clock => CLKA = Main Clock CLKB = QA’ CLKC = QB’
Flip-flop inputs => DA = QA’ DB = QB’ DC = QC’
Circuit Diagram

Truth Table
Clock QC QB QA Decimal Equivalent
Initial
1
2
3
4
5
6
7
8

Timing Diagram

34
 3-bit Asynchronous (Ripple) Down Counter
Boolean Expression
Input / Output => Self-Starting Counter QAQBQC => Data Outputs
Clock => CLKA = Main Clock CLKB = QA CLKC = QB
Flip-flop inputs => DA = QA’ DB = QB’ DC = QC’
Circuit Diagram

Truth Table
Decimal
Clock QC QB QA Equivalent
Initial
1
2
3
4
5
6
7
8

Timing Diagram

35
Asynchronous UP counter
It is capable of counting numbers in ascending order. The clock inputs of all flip flops are
cascaded, and the input(s) of each flip flop is connected to a state output of the flip flop. That means
the flip-flops will toggle at each active edge or positive edge of the clock signal. The clock input is
connected to the first flip-flop. The other flip flops in the counter receive the clock signal input from
Q’ output of the previous flip flop. The output of the first flip-flop will change when the positive edge
on the clock signal occurs. The flip flops are connected in toggle mode.
Asynchronous DOWN counter
It is a simple modification of the UP counter. The DOWN counter will count numbers
downwards. The clock inputs of all flip flops are cascaded, and the input(s) of each flip flop is
connected to logic 1. That means the flip-flops will toggle at each active edge (positive edge) of the
clock signal. The clock input is connected to the first flip-flop. The other flip flops in the counter
receive the clock signal input from the Q output of the previous flip flop, rather than Q’ output.
Advantages and Disadvantages of Asynchronous Counter
Asynchronous counters can be easily built using Type D & T flip-flops. They can be
implemented using a “divide by n” counter circuit, which offers much more flexibility on larger
counting range-related applications.
While using the Asynchronous counter, an additional re-synchronizing output flip-flops is
required for resynchronizing the flip-flops. Also, For the truncated sequence count, when it is not
equal to, extra feedback logic is needed. When counting a large number of bits, due to the chain
system, propagation delay by successive stages became too large which is very difficult to get rid of.
In such a situation, Synchronous counters are faster and more reliable. There are also counting errors
in the Asynchronous Counter when high clock frequencies are applied across it.
Procedure
1) Connections are given to the components as shown in the diagram.
2) Binary bits are applied as per the truth table.
3) Verification of the glowing of LEDs confirming to the required data as per the truth.

Result

***** ***** ***** ***** *****

1) Can you use SR flip-flop to design an asynchronous counter? Why?
2) Which flip-flop is more convenient to design asynchronous counters? Why?

36
 Ex. No: DESIGN AND IMPLEMENTATION OF SYNCHRONOUS
Date: COUNTERS

Aim
To design and implement the following synchronous counters using D flip-flop and verify its
truth table. (a) 2-bit up counter; (b) 2-bit down counter; (c) MOD-5 counter; (d) Sequence counter.

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 D Flip-flop (IC 7474) 2
3 NOT gate (IC 7404) 1
4 AND gate (IC 7408) 1
5 OR gate (IC 7432) 1
6 Ex-OR gate (IC 7486) 1
7 Single strand wires -

Theory
Synchronous Counter
The significant difference between synchronous and asynchronous counters is made by the way
the clock signal is provided to these digital devices. A synchronous counter is one in which all the
flip flops are clocked simultaneously with a similar clock input. On the contrary, an asynchronous
counter is a device in which all the flip flops that constitute that counter are clocked with different
input signals at different instants of time.
The synchronous counter, also known as parallel counter, is the one in which each constituting
flip flops are clocked with the same clock input simultaneously. Basically, in the synchronous
counter, all the flip flops in the cascade connection are individually connected to an external clock.
This facilitates the clocking of all the flip-flops constituting the counter at the same time instant with
the same clock input. This means the output of each flip-flop varies in synchronization with the clock
input. So, due to this, the common clock signal causes the change in the state of each flip-flop
simultaneously. This resultantly leads to no ripple effect thus propagation delay does not exist in this
counter. Logic gates are used in synchronous counters to control the count sequence.
Advantages: Easier to design than the Asynchronous counter; Acts simultaneously; No
propagation delay; Count sequence is controlled using logic gates, error chances are lower; Faster
operation than the Asynchronous counter. One major disadvantage is that it requires a lot of extra
logic to perform.

37
 2-bit Synchronous UP Counter
Design
Present State Next State FF Inputs
min
A B A+ B+ DA DB
0 0 0 0 1 0 1
1 0 1 1 0 1 0
2 1 0 1 1 1 1
3 1 1 0 0 0 0

DA = A’B + AB’ = A ⨁ B DB = B’

Circuit Diagram

Truth Table
Decimal
Clock QA QB Equivalent
Initial
1
2
3
4

38
 2-bit Synchronous Down Counter

Design
Present State Next State FF Inputs
min
A B A+ B+ DA DB
0
1
2
3

Circuit Diagram

Truth Table
Decimal
Clock QA QB Equivalent
Initial
1
2
3
4

39
 3-bit Synchronous MOD-5 Counter
Design
Present State Next State FF Inputs
min
A B C A+ B+ C+ DA DB DC
0 0 0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 0 1 0
2 0 1 0 0 1 1 0 1 1
3 0 1 1 1 0 0 1 0 0
4 1 0 0 0 0 0 0 0 0
5 1 0 1 X X X X X X
6 1 1 0 X X X X X X
7 1 1 1 X X X X X X

DA = B C DB = B’C + BC’ =B ⨁ C DC = A’ C’

Circuit Diagram

Truth Table
Decimal
Clock QA QB QC Equivalent
Initial
1
2
3
4
5

40
 Design the Sequence generator: 0, 1, 5, 7, 2, 4, 3, 0, … (Don’t care the unused state)

Design
Present State Next State FF Inputs
min
A B C A+ B+ C+ DA DB DC
0 0 0 0 0 0 1 0 0 1
1 0 0 1 1 0 1 1 0 1
2 0 1 0 1 0 0 1 0 0
3 0 1 1 0 0 0 0 0 0
4 1 0 0 0 1 1 0 1 1
5 1 0 1 1 1 1 1 1 1
6 1 1 0 X X X X X X
7 1 1 1 0 1 0 0 1 0

DA = B’C + BC’ =B ⨁ C DB =A DC = B’

Circuit Diagram

Truth Table
Clock QA QB QC Decimal
Initial
1
2
3
4
5
6
7

41
 Applications: Machine Motion control; Motor RPM counter; Rotary Shaft Encoders; Digital
clock or pulse generators; Digital Watch and Alarm systems.
Types: Binary counters; UP / DOWN counter; Modulo counters; Sequence generators; Loadable
counters; Ring counters; Johnson counters; etc…
Basis for
Synchronous Counter Asynchronous Counter
Comparison
Also called as Parallel Counter Serial Counter
Each flip-flop is triggered with a
Principle of Each flip-flop is triggered with the
different clock signal at different
operation same clock signal at the same time.
instant of time.
Decoding errors Not produced Produced
Operating speed Fast Comparatively slow
Design Complex Simple
Delay in signal
Very Low Comparatively high
propagation
Count sequence Not Fixed Fixed
There is no simultaneous change in
Response to the Each flip-flop changes its state
the state of all flip flops with a
clock signal simultaneously.
change in clock input.
Maximum settling time out of the
Overall settling Summation of the settling time of
settling time of each flip flop in the
time each flip-flop.
configuration.
Flip-flop direct
Not Exist Exist
interconnection
In moving machine controlling, alarms In ring and Johnson counters,
Applications
clocks, multiplexing circuits, etc. frequency dividers, etc.

Procedure
1) The circuit is designed as per the problem specification using logic gates and/or flip-flops.
2) Connections are given as per the circuit diagram in the digital IC trainer kit.
3) Binary inputs are applied as per the truth table.
4) The output of the glowing LED is verified with the truth table.

Result

***** ***** ***** ***** *****

1) How many flip-flops are required to design a MOD-10 (Decade) counter?
2) Can you design the same circuits using JK flip-flop? Which circuit is simple?
3) How can you decide which flip-flop can be used for a design?

42
 Ex. No: DESIGN AND IMPLEMENTATION OF RING COUNTER AND
Date: JOHNSON COUNTER

Aim
To design and implement the following synchronous counters using D flip-flop and verify its
truth table. (a) 3-bit ring counter; (b) 3-bit Johnson (twisted ring) counter.

Apparatus Required
S.No. Components Quantity
1 Digital IC Trainer 1
2 D Flip-flop (IC 7474) 2
3 Single strand wires -

Theory
Ring Counter
A ring counter is a typical application of the SISO Shift register. The ring counter is almost
the same as the shift counter. The only change is that the output of the last flip-flop is connected to
the input of the first flip-flop in the case of the ring counter but in the case of the shift register it is
taken as output.

Johnson (Twisted Ring) Counter

A twisted ring counter is a type of ring counter in which the complement of the output of the
last shift register is connected to the input of the first register. It circulates a stream of 1s followed by
0s around the ring.

Parameter Ring Counter Johnson Counter

Name of counter Straight ring; One hot counter Twisted ring; Walking ring counter
The output of the last shift registers to The complemented output of the last
Connection
the input of the first shift register register to the input of the first register
Output circulates The single ‘1’ bit around the ring Stream of 1 followed by a stream of 0
No. of States = No. of Flip-flops = 2 x no. of Flip-flops
PRESET Used in the first register Not used
CLEAR Used for last (n – 1) flip-flops Used for all flip-flops
Successive approximation; Phase shift
Application
Stepper motor control. Function generator

43
 3-bit Ring Counter
Boolean Expression
Synchronized Clocks QA QB QC = Data Outputs
DA = QC DB = QA DC = QB

Circuit Diagram

Truth Table
Note: To set the initial condition, OFF the ‘Ring’ switch and bring it back to the default condition.

Clock QA QB QC
Initial 1 0 0
1 0 1 0
2 0 0 1
3 1 0 0
4 0 1 0
5 0 0 1

In this case, we must set the initial condition manually.

Think and find to avoid it. i.e. Design a self-starting ring counter.
Hint: Design a circuit to ‘set’ the first flip-flop when all flip-flops are in state 0.

44
 3-bit Johnson (Twisted Ring) Counter
Boolean Expression
Synchronized Clocks QA QB QC = Data Outputs
DA = QC’ DB = QA DC = QB

Circuit Diagram

Truth Table

Clock QA QB QC
Initial 0 0 0
1 1 0 0
2 1 1 0
3 1 1 1
4 0 1 1
5 0 0 1
6 0 0 0

In this case, each flip-flop in state ‘1’ for 3 clock periods.

Think and find a solution to keep each flip-flop in state ‘1’ only for 2 clock periods.
Hint: Design a circuit to reset the first flip-flop after reaching the desired condition.

45
Procedure
1) The circuit is designed as per the problem specification using logic gates and/or flip-flops.
2) Connections are given as per the circuit diagram in the digital IC trainer kit.
3) Binary inputs are applied as per the truth table.
4) The output of the glowing LED is verified with the truth table.

Result

***** ***** ***** ***** *****

Can you design the Ring / Johnson counter in Asynchronous mode? Why?

46
Space for Hints & Rough Work

47
 Digital ICs Pin Diagram and Functional Table
H => High (1) L => Low (0) X => High or Low (1 or 0)
+ Vcc => +5 Volts GND => 0 Volt
A, B, C => Inputs Y => Output

NOT (Inverter) gate [Hex] 2-input NAND, AND, OR & EX-OR gates [Quad]

1A 1 14 +Vcc 1A 1 14 +Vcc

1Y 2 13 6A 1B 2 13 4A

2A 3 12 6Y 1Y 3 12 4B
IC 7408
2Y 4 IC 7404 11 5A 2A 4 IC 7432 11 4Y

2A 5 10 5Y IC 7486
2B 5 10 3A

3Y 6 9 4A 2Y 6 9 3B

GND 7 8 4Y GND 7 8 3Y

NOT gate (IC 7404)

Input Output AND gate (IC 7408)
A Y = A’ Inputs Output
H L A B Y=A•B
L H H H H
L X L
X L L

48
 OR gate (IC 7432) 3-input AND gate [Triple]
Inputs Output
A B Y=A+B
H X H 1A 1 14 +Vcc
X H H
L L L 1B 2 13 1C

2A 3 12 1Y

2B 4 IC 7411 11 3A

2C 5 10 3B

2Y 6 9 3C

GND 7 8 3Y

EX-OR gate (IC 7486)

Inputs Output 3-i/p AND gate (IC 7411)
A B Y=AB
Inputs Output
L L L
A B C Y=A•B•C
L H H
H H H H
H L H
L X X L
H H L
X L X L
X X L L

49
 D Flip-flop with Preset & Clear [Dual] JK Flip-flop with Preset & Clear [Dual]

̅̅̅̅̅̅
1𝐂𝐋𝐑 1 14 +Vcc ̅̅̅̅̅̅
1𝐂𝐋𝐊 1 16 1K

1D 2 13 ̅̅̅̅̅̅
2𝐂𝐋𝐑 ̅̅̅̅̅̅
1𝐏𝐑𝐄 2 15 1Q

1CLK 3 12 2D ̅̅̅̅̅̅
1𝐂𝐋𝐑 3 14 ̅
1𝐐

̅̅̅̅̅̅
1𝐏𝐑𝐄 4 IC 7474 11 2CLK 1J 4 IC 7476 13 GND

1Q 5 10 ̅̅̅̅̅̅
2𝐏𝐑𝐄 +Vcc 5 12 2K

̅
1𝐐 6 9 2Q ̅̅̅̅̅̅
2𝐂𝐋𝐊 6 11 2Q

GND 7 8 ̅
2𝐐 ̅̅̅̅̅̅
2𝐏𝐑𝐄 7 10 ̅
2𝐐

̅̅̅̅̅̅
2𝐂𝐋𝐑 8 9 2J
+ Vcc => +5 V GND => 0 V CLK => Clock
D => Input Q => Output
PRE => Pre-set (Q = 1) CLR => Clear (Q = 0) + Vcc => +5 V GND => 0 V CLK => Clock
J, K => Inputs Q => Output
PRE => Pre-set (Q = 1) CLR => Clear (Q = 0)
Inputs Output
PRE’ CLR’ CLK D Q Inputs Output
PRE’ CLR’ CLK J K Q
L X X X H
H L X X L L X X X X H
H H ↑ L L H L X X X L
H H ↑ H H H H ↑ L L Q0
H H L X Q0 H H ↑ L H L
H H ↑ H L H
H H ↑ H H ̅̅̅̅
𝐐𝟎
Q0 – Present State

50
 ICs NOMENCLATURE

7400 series parts were constructed using bipolar transistors, forming what is referred to as
transistor–transistor logic or TTL. Newer series, more or less compatible in function and logic level
with the original parts, use CMOS technology or a combination of the two (BiCMOS).

Bipolar
➢ 74 - "Standard TTL" logic family had no letters between the "74" and the part number.
➢ 74L - Low power (compared to the original TTL logic family), very slow
➢ H - High speed (still produced but generally superseded by the S-series)
➢ S - Schottky (obsolete)
➢ LS - Low Power Schottky
➢ AS - Advanced Schottky
➢ ALS - Advanced Low Power Schottky
➢ F - Fast (faster than normal Schottky, similar to AS)

CMOS
➢ C - CMOS 4–15 V operation similar to buffered 4000 (4000B) series
➢ HC - High speed CMOS, similar performance to LS, 12 nS
➢ HCT - High speed, compatible logic levels to bipolar parts
➢ AC - Advanced CMOS, performance generally between S and F
➢ AHC - Advanced High-Speed CMOS, three times as fast as HC
➢ ALVC - Low voltage - 1.65 to 3.3 V, Time Propagation Delay 2 nS
➢ AUC - Low voltage - 0.8 to 2.7 V, TPD < 1.9 nS@1.8 V
➢ FC - Fast CMOS, performance similar to F
➢ LCX - CMOS with 3 V supply and 5 V tolerant inputs
➢ LVC - Low voltage – 1.65 to 3.3 V and 5 V tolerant inputs,
tpd < 5.5 nS@3.3 V, tpd < 9 nS@2.5 V
➢ LVQ - Low voltage - 3.3 V
➢ LVX - Low voltage - 3.3 V with 5 V tolerant inputs
➢ VHC - Very High-Speed CMOS - 'S' performance in CMOS and power

BiCMOS
➢ BCT - BiCMOS, TTL-compatible input thresholds, used for buffers
➢ ABT - Advanced BiCMOS, TTL-compatible input thresholds, faster than ACT and BCT

51
IC Number and Details

➢ IC 7400 – quad 2-input NAND gate

➢ IC 7402 – quad 2-input NOR gate
➢ IC 7404 – hex inverter (NOT)
➢ IC 7408 – quad 2-input AND gate
➢ IC 7411 – triple 3-input AND gate
➢ IC 7432 – quad 2-input OR gate
➢ IC 7486 – quad 2-input XOR gate
➢ IC 7474 – dual D positive edge triggered flip-flop
➢ IC 7476 – dual J-K flip-flop with preset and clear

➢ IC 7445 – BCD to decimal decoder/driver

➢ IC 7447 – BCD to 7-segment decoder/driver with 15 V open collector outputs
➢ IC 7473 – dual J-K flip-flop with clear
➢ IC 7483 – 4-bit binary full adder
➢ IC 7485 – 4-bit magnitude comparator
➢ IC 7491 – 8-bit shift register, serial In, serial out, gated input
➢ IC 7494 – 4-bit shift register, dual asynchronous presets
➢ IC 74148 – 8-line to 3-line priority encoder
➢ IC 74150 – 16-line to 1-line data selector/multiplexer
➢ IC 74151 – 8-line to 1-line data selector/multiplexer
➢ IC 74153 – Dual 4-line to 1-line data selector/multiplexer
➢ IC 74157 – Quad 2-line to 1-line data selector/multiplexer
➢ IC 74238 – 3-line to 8-line Decoder / Demultiplexer
➢ IC 74239 – Dual 2-line to 4-line Decoder / Demultiplexer

52
 Integrated Circuits (ICs) & BreadBoard Usage Instructions

The IC’s supplied with the kit are used in a variety of experiments. Each looks similar to the
one shown below:

Figure: IC Pin Numbering

Note the numbering system, which progresses counterclockwise from pin 1. Pin 1 is
designated by a dot or a notch Usually on TTL logic (the type of chips supplied with the kit), the last
pin is to be connected to the +5 V supply, and the pin diagonally opposite is connected to the ground.
These are pins 14 and 7, respectively, for 14-pin ICs and 16 and 8 for 16-pin ICs.
There are some exceptions to this rule, so always check!
Special caution should be taken when inserting and removing ICs from the Breadboard (or)
protoboard.
When shipped from the factory, the leads (legs) of the ICs are slightly bent apart to aid in
machine insertion.
It is necessary to straighten the legs before insertion into the protoboards. This can be done
easily by flattening the legs on a tabletop as shown below. Ask your instructor to show you how this
is done if you need help.

From the factory Bend one side then the other till the legs are parallel

When you remove a chip (IC) from the Breadboard, it is very easy to bend the legs by not
exercising caution. You should not simply pull on the chip with two fingers to remove it One end will
invariably rise before the other causing the legs on the other end to bend. It may even result in a
puncture wound to one of your fingers because the legs of the ICs are very sharp. Be careful if an IC
extractor is not available, you should use the tip of a pen or pencil to gently pry up the legs on one
end of the chip, and then the other, as shown below.

53
 Figure: Placing IC in BreadBoard Figure: Removing an IC

To interconnect your Integrated Circuits (IC’s) properly, the pin numbers must be known.
Each chip has an orientation “notch” which defines where pin 1 is located. When the notch is on the
left, pin one is on the bottom left. The pins are numbered counterclockwise from 1.

Each chip has a part number stamped on it which gives the chip’s manufacturer, function, and
performance. As shown above, the chip DV74LS374N is a 74374 logic chip which is an “octal D-
type tri-state flip flop.” The LS means it is a “Low-power Schottky.”
The “Breadboard” contains a grid of holes in which wires can be inserted to make an electrical
connection with the pins (“legs”) of the IC. The diagram below shows how contacts are connected
internally.

Figure: Breadboard Internal Connection

*************************

54