Not 2004251708 Xinluda-Xl74ls04 C513511
Not 2004251708 Xinluda-Xl74ls04 C513511
VCC
NC
2Y 5A
1Y
1A
6A
4 11
3A 5 10 5Y
3Y 6 9 4A 3 2 1 20 19
2A 4 18 6Y
GND 7 8 4Y
NC 5 17 NC
2Y 6 16 5A
XD54LS04 . . . W PACKAGE NC NC
7 15
(TOP VIEW)
3A 8 14 5Y
9 10 11 12 13
1A 1 14 1Y
3Y
4Y
4A
GND
NC
2Y 2 13 6A
2A 3 12 6Y
VCC 4 11 GND NC − No internal connection
3A 5 10 5Y
3Y 6 9 5A
4A 7 8 4Y
ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube
PDIP − N Tube XD74LS04 XD74LS04
Tube
Tube
7404
Tape and reel
Tube
SOIC − D XL74LS04 LS04
0°C
0 C to 70
70°C
C Tape and reel
Tube
S04
Tape and reel
Tape and reel SN7404
SOP − NS Tape and reel 74LS04
XL74LS04NS
Tape and reel 74S04
SSOP − DB Tape and reel LS04
Tube
Tube
Tube
CDIP − J
Tube
Tube
−55°C
−55 C to 125
125°C
C Tube
Tube
CFP − W Tube
Tube
Tube
LCCC − FK
Tube
1
XL74LS04 SOP14/XD74LS04/DIP14 XD54LS04 DIP14
FUNCTION TABLE
(each inverter)
INPUT OUTPUT
A Y
H L
L H
1A 1Y
2A 2Y
3A 3Y
4A 4Y
5A 5Y
6A 6Y
Y=A
2
XL74LS04 SOP14/XD74LS04/DIP14 XD54LS04 DIP14
schematics (each gate)
’04
VCC
4 kΩ 1.6 kΩ 130 Ω
Input A
Output Y
1 kΩ
GND
’LS04 ’S04
VCC VCC
20 kΩ 8 kΩ 120 Ω 2.8 kΩ 50 Ω
900 Ω
Input
A 3.5 kΩ Output
Input 4 kΩ Output Y
A Y
12 kΩ
250 Ω
500 Ω
3 kΩ
1.5 kΩ
GND
GND
3
XL74LS04 SOP14/XD74LS04/DIP14 XD54LS04 DIP14
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
4
XL74LS04 SOP14/XD74LS04/DIP14 XD54LS04 DIP14
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
XD54LS04
FROM TO XL74LS04
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 12 22
A Y RL = 400 Ω, CL = 15 pF ns
tPHL 8 15
5
XL74LS04 SOP14/XD74LS04/DIP14 XD54LS04 DIP14
recommended operating conditions (see Note 3)
XD54LS04 XL74LS04
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current −1 −1 mA
IOL Low-level output current 20 20 mA
TA Operating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VCC
RL
From Output Test
Under Test Point
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
6
XL74LS04 SOP14/XD74LS04/DIP14 XD54LS04 DIP14
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
VCC Under Test (see Note B)
RL CL
From Output RL (see Note A) 5 kΩ
Under Test (see Note B) From Output Test
CL Under Test Point
(see Note A) CL
(see Note A) S2
3V
High-Level Timing
Pulse 1.3 V 1.3 V Input 1.3 V
0V
tw th
tsu
3V
Low-Level 1.3 V 1.3 V Data
1.3 V 1.3 V
Pulse Input
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD TIMES
Output 3V
Control
(low-level 1.3 V 1.3 V
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ
tPLH tPHL
Waveform 1 ≈1.5 V
In-Phase VOH 1.3 V
(see Notes C
Output 1.3 V 1.3 V VOL + 0.5 V
and D)
(see Note D) VOL VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase Waveform 2 VOH − 0.5 V
VOH
Output (see Notes C 1.3 V
1.3 V 1.3 V
and D) ≈1.5 V
(see Note D) VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time, with one input transition per measurement.