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Activity2 Exploring EDA Playground

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32 views4 pages

Activity2 Exploring EDA Playground

Uploaded by

lopeznathan272
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Hands-On Activity #2

Exploring EDA Playground

Name: DAVID, RONALYN O.

Section: BSCPE 3-4

Date: 10/11/2024

Part 1: Given the design and testbench source codes below, perform the following items:

1. Create and log in to your EDA playground account.


2. Copy both the provided design code and testbench code to their respective blocks.
3. Configure the language and libraries to use.
4. Click Run. Copy the results from the Logs output and place it in the designated block below.
5. In the testbench, add $monitor(or_out); after the $dumpvars statement. Re-run the
simulation. What did you observe? Write your answer on the space provided below.
6. Check the “Open EPWave after run” then re-run the simulation. Screenshot the popped-out
result and paste on the space provided below.
7. Try to change one of the time units of simulation (e.g., #5 to #10) and re-run (make sure EPWave
is enabled). What happened to the execution of signals after it? Write your observation on the
space provided below.
8. Click the Save button and add title to your playground. Select Public(anyone with the link can
view) and click save again.
9. Provide the public link on the space provided below.

Verilog design code for OR-gate: Verilog testbench code for OR-gate:
module or_gate module tb_or;
reg or_in1, or_in2;
(or_y,or_a,or_b); wire or_out;

input or_a,or_b; or_gate g1(.or_y(or_out), .or_a(or_in1), .or_b(or_in2));


output or_y;
initial begin
$dumpfile("dump.vcd");
or(or_y, or_a, or_b); $dumpvars(1,tb_or);

or_in1 = 1'b0;
endmodule or_in2 = 1'b0;
#5
$display("A=%d, B=%d, Y=%d",or_in1,or_in2,or_out);
or_in1 = 1'b0;
or_in2 = 1'b1;
#5
$display("A=%d, B=%d, Y=%d",or_in1,or_in2,or_out);
or_in1 = 1'b1;
or_in2 = 1'b0;
#5
$display("A=%d, B=%d, Y=%d",or_in1,or_in2,or_out);
or_in1 = 1'b1;
or_in2 = 1'b1;
#5
$display("A=%d, B=%d, Y=%d",or_in1,or_in2,or_out);
or_in1 = 1'b0;
or_in2 = 1'b0;
#5
$display("A=%d, B=%d, Y=%d",or_in1,or_in2,or_out);

end
endmodule
Log results after run:

VCD info: dumpfile dump.vcd opened for output.


A=0, B=0, Y=0
A=0, B=1, Y=1
A=1, B=0, Y=1
A=1, B=1, Y=1
A=0, B=0, Y=0
Finding VCD file...
Answer for item #5:

This illustrates the signal value at each step when there is a change from the initial value of 0 to 1. It
captures and presents the signal values at each step or timestamp where a change occurs. Starting from
an initial state (such as 0), it records the transitions in signal values (A, B, Y) whenever they switch
between 0 and 1.

Answer for item #6:

Answer for item #7:

The waveform spans from 0s to 45s, showing how the signals change during this time. The signals shown
here appear to take longer durations between transitions. Also, EPWave is likely used to capture
changes in logic or signals over time, and in this particular case, the duration of 45 seconds is used for
observation.
Public link of your playground:

https://www.edaplayground.com/x/cKd6

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