IEEE TRANSACTIONS ON COMPUTERS, VOL. 72, NO.

3, MARCH 2023 893

High-Speed Counter With Novel LFSR independent of the size, it can be used to produce a high-speed
State Extension and constant-time synchronous counter [7], [9], [10]. There are
two types of LFSR that are different in the way of feedback con-
nection [11], [12], [13], [14]. One is a many-to-one LFSR, where
Hyungjoon Bae , Yujin Hyun , Member, IEEE, many F/Fs are involved in making one feedback value, and the
Suchang Kim , other is a one-to-many LFSR, where one F/F value is fed back to
Sangsoo Park , Student Member, IEEE, many F/Fs. If the number of input bits participating in the feed-
Jaeyoung Lee , Boseon Jang , back increases, the operating speed of the many-to-one LFSR
Suyoung Choi, and decreases like a binary counter [14]. Nevertheless, many previ-
In-Cheol Park , Senior Member, IEEE ous works have used a many-to-one LFSR as a basic counter
Abstract—This paper presents a high-speed counter architecture associated with
without considering the speed difference between the two types.
novel LFSR state extension. By employing the proposed state extension, an m-bit In [15], for example, a digital CMOS image sensor utilizes a
LFSR counter with ð2m  1Þ states is modified to cover 2m states without degrading counter to convert analog pixel values to digital values, and a
the counting rate. Based on the property that only the low-order bits are frequently many-to-one LFSR counter was incorporated to achieve high-
switched, the proposed counter consists of two sub-counters to achieve a high speed conversion. In addition, a ring oscillator-based physically
counting rate and reduce the hardware complexity needed to convert an LFSR unclonable function utilizes a many-to-one LFSR counter to pro-
state into a binary state. The low-order sub-counter is implemented with the
duce a pseudo-random sequence [16]. Furthermore, in [12]
proposed LFSR counter, and the high-order sub-counter is designed by employing
the conventional synchronous binary counter. In addition, the implemented counter
and [17], a many-to-one LFSR was included to implement a mul-
takes into account the speed degradation caused by the large fan-out of the high- tistage LFSR counter for a time-of-flight camera system.
order sub-counter. The proposed counter designed with standard cells operates at There is a drawback that needs to be considered in using the
2.08 GHz in a 65 nm CMOS technology, and its counting rate is almost LFSR as a counter. Since an m-bit LFSR is associated with up to
independent of the counter size. (2m  1) states, additional circuits are inevitable to extend the num-
ber of states to 2m and to convert an LFSR state into a binary
Index Terms—Arithmetic and logic units, combinational logic, high-speed arith- state [7], [12], [13], [14], [18]. Furthermore, the state extension
metic, sequential circuits should be synchronous with the LFSR in order not to degrade
the counting rate. For instance, [9] presented a time-memory
Ç tradeoff that combines the iteration method and the direct
look-up table (LUT) method. However, the LUT size becomes
huge as the counter size increases, and the state extension has
not been considered in the time-memory tradeoff, which makes
it difficult to convert an LFSR state into a binary state. A multi-
1 INTRODUCTION stage LFSR counter was presented in [12], where the complex-
Recently there have been increasing demands for high-speed coun- ity of the decoding logic is logarithmically proportional to the
ters that support wide bit-width for various applications such as counter size, and the state extension degrades the counting
frequency synthesizers, phase-locked loops (PLLs), analog-to-digi- speed significantly.
tal converters (ADCs), and time-to-digital converters (TDCs) [1], [2], In this paper, we present a high-speed counter associated with a
[3], [4], [5]. As the counter size and the counting rate conflict with novel state extension. The proposed counter consists of an LFSR
each other, the conventional binary counter cannot achieve a high sub-counter and a binary sub-counter, and its delay is almost con-
counting rate unless the counter size is small enough. Furthermore, stant regardless of the counter size. The proposed LFSR counter
most synchronous binary counters that combine an adder and a has a state detection circuit to extend the number of states from
state register are not effective in achieving a constant clock rate inde- (2m  1) to 2m without degrading the counting rate for an m-bit
pendent of the counter size, as the delay of the adder depends on the LFSR. A prototype counter and the previous counters are designed
counter size [6], [7], [8]. with standard cells and evaluated in a 65 nm CMOS technology.
In the circumstances that the binary state is not immediately The prototype counter achieves a higher counting rate than the pre-
required, a state generator can be exploited to realize a constant- vious counters.
time synchronous counter [7]. One of the most common state The remainder of this paper is organized as follows. The
generators is the linear feedback shift register (LFSR), where the previous counters are briefly introduced in Section 2, and the
next state is derived from the present state by using a feedback proposed counter architecture with the novel LFSR state exten-
connection. As the LFSR is realized with only D flip flops (F/Fs) sion is described in Section 3. The implementation details are
and exclusive-OR (XOR) gates and its delay is almost explained in Section 4. Finally, concluding remarks are made in
Section 5.
 Hyungjoon Bae, Yujin Hyun, Suchang Kim, Sangsoo Park, Jaeyoung Lee, Boseon
Jang, and In-Cheol Park are with the Department of Electrical Engineering, Korea
Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Korea. 2 PREVIOUS COUNTERS
E-mail: {hjbae, yjhyun, sckim, sspark, jylee, bsjang}@ics.kaist.ac.kr, icpark@kaist.edu.
 Suyoung Choi is with SK hynix Inc, Icheon-si, Gyeonggi-do 17336, Korea. This section describes the conventional binary counter, pre-scaled
E-mail: suyoung.choi@sk.com. counter, and LFSR. Then the previous work on the LFSR counter is
Manuscript received 30 November 2021; revised 24 May 2022; accepted 23 June 2022. briefly introduced.
Date of publication 30 June 2022; date of current version 10 February 2023.
This work was supported in part by the National Research Foundation of Korea under
Grant NRF-2017R1E1A1A01076992, in part by the (MSIT) Ministry of Science and 2.1 Binary Counter
ICT, South Korea, in part by ITRC (Information Technology Research Center) support The conventional synchronous binary counter that generates a
program under Grant IITP-2020-0-01847, and in part by the (IITP) Institute of Informa- binary sequence is illustrated in Fig. 1. The counter is made of a set
tion & Communications Technology Planning & Evaluation. of T F/Fs and a chain of AND gates. A T F/F can be realized by a
(Corresponding author: In-Cheol Park.)
Recommended for acceptance by K. Gaj. combination of an XOR gate and a D F/F, as shown on the left side
Digital Object Identifier no. 10.1109/TC.2022.3187343 of Fig. 1 [7]. Since the counter needs to be synchronized to a count
0018-9340 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See ht_tps://www.ieee.org/publications/rights/index.html for more information.

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894 IEEE TRANSACTIONS ON COMPUTERS, VOL. 72, NO. 3, MARCH 2023

Fig. 1. Conventional 8-bit synchronous binary counter.

(CNT) signal as well as CLK, the CNT signal is connected to the

XOR gate of the first F/F and the EN port of the other F/Fs. Due to
the nature of the binary sequence, an upper bit is switched only
when all the lower bits are 1’s, which is realized with the chain of
AND gates called a ripple carry chain. Since the outputs of the
chain are valid when all the lower outputs are stabilized, it forms a
critical path limiting the counting rate. Also, the propagation delay Fig. 3. LFSR types. (a) Many-to-one LFSR and (b) one-to-many LFSR with 4 taps.
of the chain is proportional to the counter size, making it unsuit-
able for applications needing large counters.
polynomial so as to indicate the location of the taps affecting the
next state. Also, the relationship is implemented with XOR gates,
2.2 Pre-Scaled Counter
and allows the LFSR to generate a sequence of pseudo-random
An N-bit pre-scaled counter depicted in Fig. 2 was proposed in [19]
numbers [14], [18], [21], [22], [23]. Fig. 3 shows two types of 8-bit
to achieve a constant counting rate independent of the counter size.
LFSR: a many-to-one type in Fig. 3a and a one-to-many type in
The counter is divided into a low-order m-bit sub-counter and a
Fig. 3b. They are frequently referred to as a Fibonacci LFSR and a
high-order ðN mÞ-bit sub-counter, where m is much smaller than
Galois LFSR, respectively [12], [13], [14]. Both the 8-bit LFSRs have
N. As the ith bit of the counting results is switched every 2i clock
taps at the 4th, 5th, 6th, and 8th bits and can be expressed as a poly-
cycles, the high-order sub-counter can operate with a long clock
nomial shown below,
period [7], [20]. The slow clock is sufficient for the high-order sub-
counter even if the size of the low-order sub-counter is less than or
equal to 6 bits [19]. After the low-order sub-counter has counted x8 þ x6 þ x5 þ x4 þ 1; (1)
2m states, the high-order sub-counter is enabled once by using a
2m -bit straight ring counter, as shown on the upper right of Fig. 2. where the last 1 corresponding to x0 means the input to Q[0]. The
Only the leftmost F/F of the straight ring counter is initialized to 1, initial value can be configured into the LFSR by appropriately
and the ring counter is shifted right by one every clock cycle. selecting F/Fs with set and reset capability.
There are two important drawbacks that must be addressed for Although the two counters are similar in terms of the number of
the pre-scaled counters. First, as the size of the straight ring counter taps and the associated polynomial, their operating speeds are dif-
is proportional to 2m , the number of F/Fs required increases expo- ferent. In case of the many-to-one LFSR, the feedback signal is
nentially as m increases. Although the size m of the low-order sub- obtained by performing XOR operations for the signals coming
counter is not large, the number of F/Fs additionally needed to from the taps. The more taps, the slower the feedback signal is. In
build the straight ring counter, 2m , is usually larger than that contrast, all the taps in the one-to-many LFSR are derived by the
required for the baseline counter, N. Second, the pre-scaled counter last F/F Q[7] in Fig. 3b, which means that the one-to-many LFSR is
is not as fast as expected since the pre-scaler enable (PEN) signal advantageous over the many-to-one LFSR in terms of operation
drives ðN mÞ bits, requiring a large fan-out. Therefore, it is neces- speed. To use the LFSR as a counter, a combination of taps that is
sary to take the fan-out issue into account. associated with the longest sequence is desired [13]. The combina-
tion of taps having the maximum-length sequence is called a primi-
2.3 Linear Feedback Shift Register (LFSR) tive polynomial, and the length is (2m  1) states except for the
state that all bits are zeros [7], [12], [13], [14], [18]. Since the maxi-
2.3.1 Conventional LFSR
mal length is one less than 2m , one state should be extended to
An LFSR is a kind of shift register that has a feedback network rep- make a sequence of 2m states.
resenting the linear relationship between the input and the output.
The linear relationship is, in general, expressed as a binary
2.3.2 Multistage LFSR Counter
As depicted in Fig. 4, the multistage LFSR counter [12] concate-
nates identical m-bit LFSR blocks that extend the number of states
to 2m . By combining the feedback and the state extension into a
block, as shown in Fig. 4a, the overall hardware complexity of the
additional circuit is reduced. When an LFSR state Q[m1:0] of
100...02 is detected, the missing state is inserted by disabling the
feedback path. However, the (m  1)-input NOR gate detecting the
LFSR state is equivalent to a chain of small-sized OR and NOR
gates, so the delay of the state detection is comparable to that of the
AND-gate chain used in the conventional binary counter. Since the
delay of the state detection depends on the size of a block counter,
the m-bit LFSR is not as fast as expected. Table 1 shows the critical
path of the LFSR blocks [12] whose lengths range from 3 bits to 10
bits. For all the block sizes, the combination of feedback and state
extension induces a critical path. The critical path tends to increase
Fig. 2. N-bit pre-scaled counter. as the LFSR block [12] size increases.

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IEEE TRANSACTIONS ON COMPUTERS, VOL. 72, NO. 3, MARCH 2023 895

Fig. 4. Multistage LFSR counter. (a) An m-bit LFSR block with state extension, and
(b) the overall block diagram.

As shown in Fig. 4b, the multistage LFSR counter [12] is divided

into k m-LFSR so as to keep m small and eventually reduce the total
number of LUT entries that perform state conversion from 2km to
k  2m . The km-bit counter should be controlled to traverse 2km
states, so a ripple carry logic that enables the subsequent LFSR
block is inserted between adjacent stages. When the ripple carry
logic detects an LFSR state of 11...102 , the next stage is switched
once. However, the structure can induce a ripple error that sequen-
tially switches all subsequent stages as well as the next stage. In
other words, an additional circuit is required to correct the ripple
error [12].

3 PROPOSED COUNTER
This section first describes the proposed LFSR counter with novel
state detection and then elaborates on the overall architecture of Fig. 5. (a) The proposed 3-bit LFSR counter with the proposed state detection cir-
the proposed high-speed counter. cuit, (b) states of the conventional 3-bit LFSR counter with a primitive polynomial
x3 þ x2 þ 1, and (c) states of the LFSR counter with the proposed state extension.

3.1 Proposed LFSR Counter With State Extension

The proposed LFSR counter with state extension is exemplified in initialized to 1112 , and the state detection circuit is initialized to
Fig. 5a, and the sequences of LFSR states without and with the 0002 . In Fig. 5b, the conventional 3-bit LFSR generates a sequence
extension are illustrated in Figs. 5b and 5c, respectively. Since the of states from 1112 to 1012 , and state 0002 is not in the sequence. As
proposed method is applicable irrespective of the LFSR size, a 3-bit the number of states provided by an m-bit LFSR is ð2m  1Þ, we
LFSR counter with two taps, Q[1] and Q[2], is exemplified to dem- need a special method to extend the number of states to 2m . The
onstrate the concept clearly. state detection circuit in Fig. 5a detects a diagonal bit-pattern of
As shown in Fig. 5a, the proposed LFSR counter is divided into 0012 , which is marked with a solid circle in Fig. 5c, by considering
two parts: a Galois LFSR and a state detection circuit. The counter three consecutive cycles. The last F/F S[2] in the state detection cir-
is synchronized with the clock and reset (nRST) signal and enabled cuit detects the first 02 of the diagonal pattern, and the second F/F
by the CNT signal. When nRST is 0 or S[0] is 1, the Galois LFSR is S[1] detects the pattern of 002 at the next cycle by using the pattern
of 02 detected in S[2], and then at the third cycle, the first F/F S[0]
detects the pattern of 0012 based on the pattern of 002 detected by S
TABLE 1
[1]. These detections are indicated with dotted lines in Fig. 5c.
Critical Path of the LFSR blocks [12] With State Extension When the diagonal pattern of 0012 is detected, S[0] becomes 1 and
then it resets the LFSR and the state detection circuit at the next
LFSR Block Size (bits) Critical Path cycle, leading to two consecutive states of Q[2:0] = 1112 . However,
3 Q ! XOR2!XOR2!Da states 0 and 7 are distinguishable by examining the value of S[0].
4 Q ! XOR2!XOR2!D This mechanism can be generalized to an m-bit LFSR, and we can
5 Q ! NOR4!XOR2!D find a unique diagonal pattern that can be used to reset the LFSR
6 Q ! OR2!NOR3!XOR2!D by permutating the order of bits and selecting an appropriate ini-
7 Q ! OR2!NOR3!XOR2!D tial value. Given a pattern of m bits, Q[m1] is directly latched to S
8 Q ! OR2!NOR4!XOR2!D [m1], and at the other positions, the value derived with Q[i] and
9 Q ! OR2!NOR4!XOR2!D
10 Q ! OR3!NOR3!XOR2!D S[i þ 1] is latched into S[i]. This process is repeated m-times to
detect the diagonal pattern. Table 2 shows some configurations of
a. D is the input of leftmost F/F, as shown in Fig. 4a. the proposed LFSR counter that can be used as a low-order sub-

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896 IEEE TRANSACTIONS ON COMPUTERS, VOL. 72, NO. 3, MARCH 2023

TABLE 2
Examples of the Proposed Counter Configuration

Galois LFSRa Size (Bits) Primitive Polynomial Detecting Patternb

3 2
3 x þx þ1 (Q[2], Q[1], Q[0]) = (0, 0, 1)
4 x4 þ x3 þ 1 (Q[2], Q[1], Q[0], Q[3]) = (1, 0, 1, 1)
5 x5 þ x3 þ 1 (Q[4], Q[3], Q[2], Q[1], Q[0]) = (0, 1, 0, 0, 1)
6 x6 þ x5 þ 1 (Q[4], Q[3], Q[2], Q[1], Q[0], Q[5]) = (1, 0, 0, 1, 1, 1)
7 x7 þ x6 þ 1 (Q[6], Q[5], Q[4], Q[3], Q[2], Q[1], Q[0]) = (0, 0, 0, 0, 1, 1, 1)
8 x8 þ x6 þ x5 þ x4 þ 1 (Q[4], Q[3], Q[2], Q[1], Q[0], Q[7], Q[6], Q[5]) = (0, 0, 1, 0, 0, 1, 1, 0)
9 x9 þ x5 þ 1 (Q[8], Q[7], Q[6], Q[5], Q[4], Q[3], Q[2], Q[1], Q[0]) = (0, 0, 1, 1, 0, 0, 0, 1, 1)
10 x10 þ x7 þ 1 (Q[6], Q[5], Q[4], Q[3], Q[2], Q[1], Q[0], Q[9], Q[8], Q[7]) = (1, 1, 0, 0, 0, 1, 1, 1, 1, 1)

a. The LFSR is initialized to 11...12 .

b. The leftmost element in Q is connected to the rightmost F/F of the state detection circuit, as shown in Fig. 5a.

counter. Note that a unique detecting pattern can be found for all corresponding to Q[m1:0] is made by looking at a translation
the LFSR counters examined and other detecting patterns can be table that has 2m entries. Thanks to the pre-scaling, m is small, usu-
found by investigating different primitive polynomials. ally less than or equal to 6 for practical counters of which size is up
Since the proposed state detection circuit sequentially detects a to 64 bits [19]. Though the conversion of an LFSR state to a binary
unique diagonal pattern bit by bit, its delay is mainly composed of state may take a long time [9], it is required only when the counter
a gate delay and some delay components needed to access F/Fs, stops. In other words, the counting rate is not affected by the
which is usually comparable to the delay of the LFSR that has an conversion.
XOR gate in the feedback path. The delay of an XOR gate is usually
longer than that of a simple gate used in the state detection circuit.
4 IMPLEMENTATION DETAILS
Therefore, the counting rate of the proposed LFSR counter is close
to that of the conventional Galois LFSR. Table 3 shows the critical In this section, the proposed counter is compared to the conven-
path of the proposed single-stage LFSR block counters. As tional synchronous binary counter and the multistage LFSR
expected, the feedback connection forms the most critical path for counter [12]. The performance is analyzed in terms of the maximum
all LFSR sizes. counting rate of single-stage block counters that range from 3 bits to
10 bits, and the maximum counting rate and the hardware complex-
3.2 High-Speed Pre-Scaled Counter ity of practically sized counters that range from 16 bits to 64 bits. All
counters are designed with standard cells in a 65 nm CMOS technol-
In the proposed pre-scaled counter architecture, an N-bit counter
ogy. The counting rate is measured at an operating voltage of 1.2 V
that generates Q[N1:0] is composed of two sub-counters, m-bit
and a temperature of 25  C. The conventional binary counter is real-
wide CL and ðN  mÞ-bit wide CH , as shown in Fig. 6a. The CL
ized in a single stage, and the multistage LFSR counter [12] is con-
sub-counter is an LFSR associated with the proposed state detec-
structed by concatenating 8-bit LFSRs serially, as shown in Fig. 4b.
tion, but the CH sub-counter is realized with a conventional binary
The proposed counter shown in Fig. 7a consists of a 6-bit LFSR
counter as it counts only once during the time that CL traverses all
counter and a 58-bit binary counter in order to form a 64-bit counter.
2m states. The m-bit LFSR counter CL generates m-bit states repre-
The 6-bit LFSR counter shown in Fig. 7b is based on the sixth-order
sented in Q[m1:0], and the binary counter CH provides binary
polynomial described in Table 2, where Q[5] is connected to S[0] not
states expressed in Q[N 1:m]. The enable port of CL is connected
to S[5]. The proposed state detection circuit detects a unique diago-
to the CNT signal, and that of CH is triggered by PEN generated by
nal pattern of 1001112 marked with a solid circle in Fig. 7c. Note that
ANDing S[0] of CL and the CNT signal, as shown in Figs. 6a and
6b. When CL traverses all the states, it activates S[0] to trigger PEN
connected to the upper binary counter. The proposed state detec-
tion circuit composed of m F/Fs and ðm  1Þ logic gates in CL dra-
matically reduces the overhead compared to the conventional pre-
scaled counter [19] requiring 2m F/Fs in the straight ring counter,
as shown in Fig. 2.
In general, the drive gate in Fig. 6a should be associated with
high strength, as it activates ðN  mÞ F/Fs. If the high-order sub-
counter size exceeds the strength of the gate, the counter will suffer
from speed degradation. Therefore, it is necessary to constrain the
number of F/Fs driven by a drive gate and change the number of
drive gates according to the size of the high-order sub-counter. An
example of drive gate configuration will be presented in the next
section.
The counting rate of the proposed counter is mainly determined
by the low-order LFSR counter CL , as the entire counter is designed
in the pre-scaled manner [7], [19]. In CL , the desired binary value

TABLE 3
Critical Path of the Proposed Single-Stage LFSR Block Counters

LFSR Counter Size (bits) Critical Path

3 - 10 Q ! XOR2!D
Fig. 6. (a) The proposed N-bit counter, and (b) timing diagram of the operation.

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IEEE TRANSACTIONS ON COMPUTERS, VOL. 72, NO. 3, MARCH 2023 897

Fig. 7. The proposed 64-bit counter. (a) The overall structure, (b) the 6-bit LFSR counter with the proposed state detection, and (c) its state changes.

4 PEN signals in Fig. 7a are used to derive the binary counter, which
is to reduce the delay caused by the large fan-out. In the proposed
counter, the 4 AND gates drive 14, 14, 14, and 16 F/Fs each. The 64-
bit structure can be also used to make smaller-sized counters by
reducing only the size of the binary counter, which means that the
6-bit LFSR counter can be commonly used to realize other smaller-
sized counters. If the size of the binary counter decreases, the drive
gates can be reduced accordingly.
The maximum counting rates of single-stage block counters are
depicted in Fig. 8. The binary counter and the multistage LFSR
counter [12] decrease the maximum counting rate as the size
increases. In the case of the binary counter, it has a counting rate
ranging from 1.96 GHz to 1.08 GHz, and the counting rate of the
multistage LFSR counter [12] ranges from 1.85 GHz to 1.58 GHz
Fig. 8. Counting rates of single-stage block counters. and the critical path is described in Table 1. The main reason for

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898 IEEE TRANSACTIONS ON COMPUTERS, VOL. 72, NO. 3, MARCH 2023

due to the gate chain in LFSR blocks and the ripple carry logic
between two stages. For the conversion from an LFSR state to a
binary state, the proposed counter needs a table of 64 entries, as
the least significant 6 bits are realized with an LFSR counter. How-
ever, the multistage LFSR counter [12] needs a table of 256 entries
for each 8-bit block. A table can be iteratively used to reduce the
complexity of the tables, but this approach lengthens the conver-
sion time and needs additional hardware.

5 CONCLUSION
This paper has proposed a high-speed counter architecture with a
novel LFSR state extension method. To reduce the delay caused by
Fig. 9. Counting rates of practically sized counters. detecting an LFSR state in a cycle, such a state is detected by con-
sidering only one bit in a cycle, which leads to a diagonal m-bit pat-
tern that can be detected for m cycles. This unique diagonal pattern
is detected with m F/Fs and ðm  1Þ gates. Based on a small-sized
TABLE 4
Critical Path of the Practically Sized Counters
LFSR counter, the proposed counter is realized by taking a pre-
scaled binary counter at the upper bit positions. In other words,
Counter Size (Bits) Counter Type Critical Path the proposed 64-bit counter consists of two sub-counters: a 6-bit
LFSR counter at the lower bit positions and a conventional 58-bit
16 - 64 Multistage m=8 [12] Q ! OR2!NOR4!XOR2!D
Proposed S[0]! AND2 !T binary counter at the upper bit positions. The conventional pre-
scaled counter requires a straight ring counter to ensure that both
sub-counters count correctly, while the proposed LFSR counter
enables the counting of the high-order sub-counter by detecting a
TABLE 5 specific state. The novel state extension method makes the pro-
Hardware Complexities of the Three Counters posed m-bit LFSR counter traverse 2m states as fast as the conven-
tional LFSR, and thus the counting rate of the proposed counter is
Counter Size Counter Type F/Fs Equivalent LUT almost independent of the counter size. In a 65 nm CMOS technol-
(Bits) Gatesa Entries ogy, the proposed 64-bit counter operates at 2.08 GHz, which is
Binary 16 55 0 much faster than the conventional binary counter as well as the
16 Multistage m=8 16 92 512 multistage LFSR counter.
[12]
Proposed 22 100 64
Binary 32 113 0 ACKNOWLEDGMENTS
32 Multistage m=8 32 190 1,024
Proposed 38 161 64
The authors would like to thank the IC Design Education Center
Binary 64 229 0 (IDEC), Korea, for supporting EDA tools.
64 Multistage m=8 64 386 2,048
Proposed 70 286 64
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