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Exp 1

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0% found this document useful (0 votes)

16 views32 pages

Exp 1

Uploaded by

Sam Felix

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1)a) nand gate

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fourinputuniversal is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

o : out STD_LOGIC);

end fourinputuniversal;

architecture dataflow of fourinputuniversal is

begin

o<=(a nand b) nand (c nand d);

end dataflow;

TESTBENCH CODE

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY fourinputuniversal_tb IS

END fourinputuniversal_tb;

ARCHITECTURE behavior OF fourinputuniversal_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fourinputuniversal

PORT(

a : IN std_logic;

b : IN std_logic;

c : IN std_logic;

d : IN std_logic;

o : OUT std_logic

);

END COMPONENT;
--Inputs

signal a : std_logic := '0';

signal b : std_logic := '0';

signal c : std_logic := '0';

signal d : std_logic := '0';

--Outputs

signal o : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fourinputuniversal PORT MAP (

a => a,

b => b,

c => c,

d => d,

o => o

);

-- Stimulus process

stim_proc: process

begin

a<='0';

b<='1';

c<='0';

d<='1';

wait for 100 ns;

a<='0';

b<='0';

c<='0';

d<='1';

wait for 100 ns;

a<='1';

b<='0';

c<='1';

d<='0';

wait for 100 ns;

a<='0';

b<='0';

c<='1';

d<='1';

wait;

end process;

END;

1)a)nor gate

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fourinputuniversalnor is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

o : out STD_LOGIC);
end fourinputuniversalnor;

architecture dataflow of fourinputuniversalnor is

begin

o<=(a nor b) nor (c nor d);

end dataflow;

TESTBENCH CODE

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY fourinputuniversalnor_tb IS

END fourinputuniversalnor_tb;

ARCHITECTURE behavior OF fourinputuniversalnor_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fourinputuniversalnor

PORT(

a : IN std_logic;

b : IN std_logic;

c : IN std_logic;

d : IN std_logic;

o : OUT std_logic

);

END COMPONENT;

--Inputs

signal a : std_logic := '0';

signal b : std_logic := '0';

signal c : std_logic := '0';

signal d : std_logic := '0';

--Outputs

signal o : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: fourinputuniversalnor PORT MAP (

a => a,

b => b,

c => c,

d => d,

o => o

);

stim_proc: process

begin

a<='0';

b<='1';

c<='0';

d<='1';

wait for 100 ns;

a<='0';

b<='0';

c<='0';

d<='1';

wait for 100 ns;

a<='1';

b<='0';

c<='1';

d<='0';

wait for 100 ns;

a<='0';

b<='0';

c<='1';

d<='1’;

wait;

end process;
END;

1)b xor

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity derivedxor is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

o : out STD_LOGIC);

end derivedxor;

architecture dataflow of derivedxor is

begin

o<= (a xor b) xor (c xor d);

end dataflow;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY derivedxor_tb IS

END derivedxor_tb;
ARCHITECTURE behavior OF derivedxor_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT derivedxor

PORT(

a : IN std_logic;

b : IN std_logic;

c : IN std_logic;

d : IN std_logic;

o : OUT std_logic

);

END COMPONENT;

--Inputs

signal a : std_logic := '0';

signal b : std_logic := '0';

signal c : std_logic := '0';

signal d : std_logic := '0';

--Outputs

signal o : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: derivedxor PORT MAP (

a => a,

b => b,

c => c,

d => d,

o => o

);

-- Stimulus process

stim_proc: process
begin

a<='0';

b<='1';

c<='0';

d<='1';

wait for 100 ns;

a<='0';

b<='0';

c<='0';

d<='1';

wait for 100 ns;

a<='1';

b<='0';

c<='1';

d<='0';

wait for 100 ns;

a<='0';

b<='0';

c<='1';

d<='1';

wait;

end process;

END;
1)b xnor

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity derivedxnor is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

o : out STD_LOGIC);

end derivedxnor;

architecture dataflow of derivedxnor is

begin

o<= (a xnor b) xnor (c xnor d);

end dataflow;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY derivedxnor_tb IS

END derivedxnor_tb;

ARCHITECTURE behavior OF derivedxnor_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT derivedxnor

PORT(

a : IN std_logic;

b : IN std_logic;

c : IN std_logic;

d : IN std_logic;

o : OUT std_logic

);

END COMPONENT;
--Inputs

signal a : std_logic := '0';

signal b : std_logic := '0';

signal c : std_logic := '0';

signal d : std_logic := '0';

--Outputs

signal o : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: derivedxnor PORT MAP (

a => a,

b => b,

c => c,

d => d,

o => o

-- Stimulus process

stim_proc: process

begin

a<='0';

b<='1';

c<='0';

d<='1';

wait for 100 ns;

a<='0';

b<='0';

c<='0';

d<='1';

wait for 100 ns;

a<='1';

b<='0';

c<='1';

d<='0';

wait for 100 ns;

a<='0';

b<='0';

c<='1';

d<='1';

wait;

end process;

END;

1)b) nand gate

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fourinputuniversal is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

o : out STD_LOGIC);

end fourinputuniversal;

architecture dataflow of fourinputuniversal is

begin

o<=(a nand b) nand (c nand d);

end dataflow;

TESTBENCH CODE

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY fourinputuniversal_tb IS

END fourinputuniversal_tb;

ARCHITECTURE behavior OF fourinputuniversal_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fourinputuniversal

PORT(

a : IN std_logic;

b : IN std_logic;

c : IN std_logic;

d : IN std_logic;

o : OUT std_logic

);

END COMPONENT;

--Inputs

signal a : std_logic := '0';

signal b : std_logic := '0';

signal c : std_logic := '0';

signal d : std_logic := '0';

--Outputs

signal o : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fourinputuniversal PORT MAP (

a => a,

b => b,

c => c,

d => d,

o => o

);

-- Stimulus process

stim_proc: process

begin

a<='0';

b<='1';

c<='0';

d<='1';

wait for 100 ns;

a<='0';

b<='0';

c<='0';

d<='1';

wait for 100 ns;

a<='1';

b<='0';

c<='1';

d<='0';

wait for 100 ns;

a<='0';

b<='0';

c<='1';

d<='1';

wait;

end process;
END;

1)b)nor gate

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fourinputuniversalnor is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

o : out STD_LOGIC);

end fourinputuniversalnor;

architecture dataflow of fourinputuniversalnor is

begin

o<=(a nor b) nor (c nor d);

end dataflow;

TESTBENCH CODE

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
ENTITY fourinputuniversalnor_tb IS

END fourinputuniversalnor_tb;

ARCHITECTURE behavior OF fourinputuniversalnor_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fourinputuniversalnor

PORT(

a : IN std_logic;

b : IN std_logic;

c : IN std_logic;

d : IN std_logic;

o : OUT std_logic

);

END COMPONENT;

--Inputs

signal a : std_logic := '0';

signal b : std_logic := '0';

signal c : std_logic := '0';

signal d : std_logic := '0';

--Outputs

signal o : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fourinputuniversalnor PORT MAP (

a => a,

b => b,

c => c,

d => d,

o => o

);
stim_proc: process

begin

a<='0';

b<='1';

c<='0';

d<='1';

wait for 100 ns;

a<='0';

b<='0';

c<='0';

d<='1';

wait for 100 ns;

a<='1';

b<='0';

c<='1';

d<='0';

wait for 100 ns;

a<='0';

b<='0';

c<='1';

d<='1’;

wait;

end process;

END;
1)c and

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity basicand is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

o : out STD_LOGIC_VECTOR (3 downto 0));

end basicand;

architecture dataflow of basicand is

begin

o<= a and b;

end dataflow;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY basicand_tb IS

END basicand_tb;

ARCHITECTURE behavior OF basicand_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT basicand

PORT(

a : IN std_logic_vector(3 downto 0);

b : IN std_logic_vector(3 downto 0);

o : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs

signal a : std_logic_vector(3 downto 0) := (others => '0');

signal b : std_logic_vector(3 downto 0) := (others => '0');

--Outputs

signal o : std_logic_vector(3 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: basicand PORT MAP (

a => a,

b => b,

o => o

);

-- Stimulus process

stim_proc: process

begin

a<="0000";

b<="1111";

wait for 100 ns;

a<="1010";

b<="0101";

wait for 100 ns;

a<="1100";

b<="1100";

wait for 100 ns;

a<="0101";

b<="1100";
wait;

-- insert stimulus here

wait;

end process;

END;

1)c or

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity basicor is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

o : out STD_LOGIC_VECTOR (3 downto 0));

end basicor;

architecture dataflow of basicor is

begin

o<= a or b;

end dataflow;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY basicor_tb IS

END basicor_tb;

ARCHITECTURE behavior OF basicor_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT basicor

PORT(

a : IN std_logic_vector(3 downto 0);

b : IN std_logic_vector(3 downto 0);

o : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs

signal a : std_logic_vector(3 downto 0) := (others => '0');

signal b : std_logic_vector(3 downto 0) := (others => '0');

--Outputs

signal o : std_logic_vector(3 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: basicor PORT MAP (

a => a,

b => b,

o => o

);

-- Stimulus process

stim_proc: process

begin

a<="0000";

b<="1111";

wait for 100 ns;

a<="1010";

b<="0101";

wait for 100 ns;

a<="1100";

b<="1100";

wait for 100 ns;

a<="0101";

b<="1100";

wait;

-- insert stimulus here

wait;

end process;

END;

1)c not

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity basicnot is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

o : out STD_LOGIC_VECTOR (3 downto 0));

end basicnot;

architecture dataflow of basicnot is

begin

o<= (not a);

end dataflow;

TEST BENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY basicnot_tb IS

END basicnot_tb;

ARCHITECTURE behavior OF basicnot_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT basicnot

PORT(

a : IN std_logic_vector(3 downto 0);

o : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs

signal a : std_logic_vector(3 downto 0) := (others => '0');

--Outputs

signal o : std_logic_vector(3 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: basicnot PORT MAP (

a => a,

o => o

);

-- Stimulus process

stim_proc: process

begin

a<="0000";

wait for 100 ns;

a<="0101";

wait for 100 ns;

a<="1010";
wait for 100 ns;

a<="0011";

wait;

end process;

END;

1)d nand

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity derived3nand is

Port ( a : in STD_LOGIC_VECTOR (2 downto 0);

b : in STD_LOGIC_VECTOR (2 downto 0);

c : in STD_LOGIC_VECTOR (2 downto 0);

o : out STD_LOGIC_VECTOR (2 downto 0));

end derived3nand;

architecture dataflow of derived3nand is

begin

o<=(a nand b) nand c;

end dataflow;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY derived3nand_tb IS

END derived3nand_tb;
ARCHITECTURE behavior OF derived3nand_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT derived3nand

PORT(

a : IN std_logic_vector(2 downto 0);

b : IN std_logic_vector(2 downto 0);

c : IN std_logic_vector(2 downto 0);

o : OUT std_logic_vector(2 downto 0)

);

END COMPONENT;

--Inputs

signal a : std_logic_vector(2 downto 0) := (others => '0');

signal b : std_logic_vector(2 downto 0) := (others => '0');

signal c : std_logic_vector(2 downto 0) := (others => '0');

--Outputs

signal o : std_logic_vector(2 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: derived3nand PORT MAP (

a => a,

b => b,

c => c,

o => o

);

-- Stimulus process

stim_proc: process

begin

a<="000";

b<="111";
c<="000";

wait for 100 ns;

a<="001";

b<="010";

c<="010";

wait for 100 ns;

a<="101";

b<="100";

c<="111";

wait for 100 ns;

a<="011";

b<="110";

c<="101";

wait;

end process;

END;

1)d nor

MODULE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity derived3nor is

Port ( a : in STD_LOGIC_VECTOR (2 downto 0);

b : in STD_LOGIC_VECTOR (2 downto 0);

c : in STD_LOGIC_VECTOR (2 downto 0);

o : out STD_LOGIC_VECTOR (2 downto 0));

end derived3nor;

architecture dataflow of derived3nor is

begin

o<=(a nor b) nor c;

end dataflow;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY derived3nor_tb IS

END derived3nor_tb;

ARCHITECTURE behavior OF derived3nor_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT derived3nor

PORT(

a : IN std_logic_vector(2 downto 0);

b : IN std_logic_vector(2 downto 0);

c : IN std_logic_vector(2 downto 0);

o : OUT std_logic_vector(2 downto 0)

);

END COMPONENT;

--Inputs

signal a : std_logic_vector(2 downto 0) := (others => '0');

signal b : std_logic_vector(2 downto 0) := (others => '0');

signal c : std_logic_vector(2 downto 0) := (others => '0');

--Outputs

signal o : std_logic_vector(2 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: derived3nor PORT MAP (

a => a,

b => b,

c => c,

o => o

);

-- Stimulus process

stim_proc: process

begin

a<="000";

b<="111";

c<="000";

wait for 100 ns;

a<="001";

b<="010";

c<="010";

wait for 100 ns;

a<="101";

b<="100";

c<="111";

wait for 100 ns;

a<="011";

b<="110";

c<="101";

wait;

end process;

END;
1)d xor

Module code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity derived3xor is

Port ( a : in STD_LOGIC_VECTOR (2 downto 0);

b : in STD_LOGIC_VECTOR (2 downto 0);

c : in STD_LOGIC_VECTOR (2 downto 0);

o : out STD_LOGIC_VECTOR (2 downto 0));

end derived3xor;

architecture dataflow of derived3xor is

begin

o<=(a xor b) xor c;

end dataflow;

Testbench code

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY derived3xor_tb IS

END derived3xor_tb;

ARCHITECTURE behavior OF derived3xor_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT derived3xor

PORT(

a : IN std_logic_vector(2 downto 0);

b : IN std_logic_vector(2 downto 0);

c : IN std_logic_vector(2 downto 0);

o : OUT std_logic_vector(2 downto 0)

);

END COMPONENT;

--Inputs

signal a : std_logic_vector(2 downto 0) := (others => '0');

signal b : std_logic_vector(2 downto 0) := (others => '0');

signal c : std_logic_vector(2 downto 0) := (others => '0');

--Outputs

signal o : std_logic_vector(2 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: derived3xor PORT MAP (

a => a,

b => b,

c => c,

o => o

);

-- Stimulus process

stim_proc: process

begin

a<="000";

b<="111";

c<="000";

wait for 100 ns;

a<="001";

b<="010";

c<="010";

wait for 100 ns;

a<="101";

b<="100";

c<="111";

wait for 100 ns;

a<="011";

b<="110";

c<="101";

wait;

end process;

END;

1)d xnor

Module code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity derived3xnor is

Port ( a : in STD_LOGIC_VECTOR (2 downto 0);

b : in STD_LOGIC_VECTOR (2 downto 0);

c : in STD_LOGIC_VECTOR (2 downto 0);

o : out STD_LOGIC_VECTOR (2 downto 0));

end derived3xnor;

architecture dataflow of derived3xnor is

begin

o<=(a xnor b) xnor c;

end dataflow;

Testbench code
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY derived3Xnor_tb IS

END derived3Xnor_tb;

ARCHITECTURE behavior OF derived3Xnor_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT derived3xnor

PORT(

a : IN std_logic_vector(2 downto 0);

b : IN std_logic_vector(2 downto 0);

c : IN std_logic_vector(2 downto 0);

o : OUT std_logic_vector(2 downto 0)

);

END COMPONENT;

--Inputs

signal a : std_logic_vector(2 downto 0) := (others => '0');

signal b : std_logic_vector(2 downto 0) := (others => '0');

signal c : std_logic_vector(2 downto 0) := (others => '0');

--Outputs

signal o : std_logic_vector(2 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: derived3xnor PORT MAP (

a => a,

b => b,

c => c,

o => o

);

-- Stimulus process
stim_proc: process

begin

a<="000";

b<="111";

c<="000";

wait for 100 ns;

a<="001";

b<="010";

c<="010";

wait for 100 ns;

a<="101";

b<="100";

c<="111";

wait for 100 ns;

a<="011";

b<="110";

c<="101";

wait;

end process;

END;

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