e-Notes by N.K.

Srinath, RVCE, Bangalore

8086/8088 - CPU Architecture

The 8086/8088 architecture can be broadly divided into two groups: (i) Execution Unit (EU) (ii) Bus Interface Unit (BIU)
2 0
A d d e r

E C S D I P

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I n t e r f a c e n it

In s t r u c t i o n q u e u e

A X B X C X D X S P B P D I S I

A H ( 8 ) A B H ( 8 ) B C H ( 8 ) C D H ( 8 ) D

L ( 8 ) L ( 8 ) L ( 8 ) L ( 8 )

C G R e n e r a l e g i s t e r s U

o n t r o l n i t

o n t r o l li n e s

E A L U

x e c u t io n U n it

F l a g s

Fig 1.3 8086 Architecture

The execution unit contains the Data and Address registers, the Arithmetic and Logic Unit and the Control Unit. The Bus Interface Unit contains Bus Interface Logic, Segment registers, Memory addressing logic and a Six byte instruction object code queue (4-byte instruction object-code queue in case of 8088 microprocessor). The execution unit and the Bus Interface unit operate asynchronously. The EU waits for the instruction object code to be fetched from the memory by the BIU. The BIU fetches or pre-fetches the object code (16-bits at a time) and loads it into the six bytes queue. Whenever the EU is ready to execute a new instruction, it fetches the instruction object code from the front of the instruction queue and executes the instruction in specified number of clock periods. If memory or Input/output devices must be accessed in the course of executing an instruction, then the EU informs the BIU of its needs. The BIU completes its operation code (opcode) fetch cycle, if in progress, and executes an appropriate external access machine cycle in response to the EU demand. The BIU is independent of the EU and attempts to keep the six-bytes queue filled with instruction object codes. If two or more of these six bytes are empty, then the BIU executes instruction fetch machine cycles as long as the EU does not have an active request for the bus access pending. If the EU issues a request for the bus access while the BIU is in the middle of an

instruction fetch machine cycle, then the BIU will complete the instruction fetch machine cycle before honoring the EU bus access request. The EU does not use machine cycles; it executes instructions in some number of clock periods that are not subjected to any type of machine cycles. The only time clock periods are grouped is clock when the bus control logic wishes to access memory or I/O devices. Execution Unit (EU) The execution unit consists of General Registers Arithmetic Logic Unit Control unit Flag Registers General Registers The CPU has eight 16-bit general registers. They are divided into two files of four registers each. They are: (a) The data register file and (b) The pointer and index register file
A B C D H H H H A B C D L L L L A B C D X X X X

Fig. 1.4 Data Register File

AX, BX, CX and DX registers are the data registers. The upper and lower halves of the data registers are individually addressable. AX register can be addressed as AL and AH registers, BX register can be addressed as BL and BH register, CX register can be addressed as CL and CH register, DX register can be addressed as DL and DH. The data registers can be used in most arithmetic and logic operations. Some instructions however require these registers for specific use. This implicit register usage allows a more compact instruction encoding. Fig.1.4 shows the data registers specific one. The index register file consists of the Stack Pointer (SP), the Base Pointer (BP), Source Index (SI) and Destination Index (DI) registers all are of 16-bits. They can also be used in most arithmetic and logic operations. These registers are usually used to hold offset addresses for addressing within a segment. Offset addressing reduces program size by eliminating the need for each instruction to specify frequently used addresses. The pointer and index register files are further divided into the pointer sub-file (containing the Stack Pointer and the Base Pointer registers) and the index sub-file (containing the Source index and Destination index registers). The Pointer registers are used to access the current stack segment. The index registers are used to access the current data. (Stack segment and data segment are specific areas of memory. Their application will be explained in later chapters). Unless otherwise specified in the instruction, stack pointer registers refer to the current stack segment while index register refers to the current data segment. The BP and SP registers are both used to point to the stack, a linear array in the memory used for subroutine parameters, subroutine return addresses, and the data temporarily saved during execution of a program The implicit register usage is as follows: AX Register Word Multiplication Word Division and

AL Register

AH Register BX Register CX Register CL Register DX Register

Word I/O Operation. Byte Multiplication Byte Division Byte I/O Translate, and Decimal Arithmetic Byte Multiplication Byte Division. Base Register Translate String Operations Variable Shift and Rotate Word Multiplication, Word Division, Indirect I/O.
Fig. 1.5

Most microprocessors have a single stack pointer register called the SP. 8086 / 8088 has an additional pointer into the stack called the BP register. While the SP is used similar to the stack pointer in other machine (for pointing to subroutine and interrupt return addresses), the BP register is used to hold an old stack pointer value, or it can mark a place in the subroutine stack independent of the SP register. Using the BP register to mark the stack saves the juggling of a single stack pointer to reference subroutine parameters and addresses. SI and DI are both 16-bits wide and are used by string manipulation instructions and in building some of the more powerful 8086/8088 data structures and addressing modes. Both the SI and the DI registers have auto incrementing and auto-decrementing capabilities. Arithmetic Logic Unit (ALU) (i) (ii) ALU is 16-bits wide. It can do the following 16-bits arithmetic operations Addition Subtraction (iii) Multiplication (iv) Division

Arithmetic operations may be performed on four types of numbers Unsigned binary numbers Signed binary numbers (Integers) Unsigned packed decimal numbers Unsigned unpacked decimal numbers The ALU can also perform logical operations such as (i) NOT (ii) AND (iii) OR (iv) EXCLUSIVE OR (v) TEST

Flag Register The Execution Unit has a 16-bit flag register which indicates some conditions affected by the execution of an instruction. Some bits of the flag register control certain operations of the EU. The flag register in the EU contains nine active flags shown in fig.1.6
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

O D

AF

PF

CF

Fig, 1.6 Flag Register

Six of the nine flags are used to indicate some condition produced by an instruction. These condition flags are also called status flags of 8086/8088 microprocessor. These are the Carry flag, Parity flag, Auxiliary carry flag, Zero flag, and Sign flag. The other three Control flags are Trap Flag, Direction Flag and Interrupt flag. Condition Flags Carry Flag (CF)

This flag will be set to one if the addition of two 16-bit binary numbers produces a carry out of the most significant bit position or if there is a borrow to the MSB after subtraction. This flag is also affected when other arithmetic and logical instruction are executed.
Parity Flag (PF) This flag is set, if the result of the operation has an even number of 1's (in the lower 8 bits of the result). This flag can be used to check for data transmission error. Auxiliary Carry Flag (AF) This flag is set, when there is a carry out of the lower nibble to the higher nibble or a borrow from the higher nibble to the lower. The auxiliary carry flag is used for decimal adjust operation. The AF flag is of significance only for byte operations during which the lower order byte of the 16-bit word is used. Zero Flag (Z) This flag is set when the result of an operation is zero. The flag is reset when the result is not zero. Overflow Flag (O) This flag is set, when an arithmetic overflow occurres. Overflow means that the size of the result exceeded the storage capacity of the destination, and a significant digit has been lost. Sign flag (S) This flag is set, when an MSB bit of the result is high after an arithmetic operation. When this flag is set the data in assumed to be negative and when this flag is zero it is assumed to be positive.

Control Flags Control flags are used to control certain operations of the processor. The application of these flags are different from that of six conditional flags. The conditional flags are set or reset by the EU on the basis of the result of some arithmetic or logic operations. The control flags are deliberately set or reset with specific instructions included in the program. Trap flag (T) This is used for single stepping through a program. It is used for debugging the programs. (Discusses with interrupts). Interrupt Flag (I) It is used to allow / prohibit the interruption of a program. When the flag set, it enables the interrupt from INTR. When the flag is reset (0), it disables the interrupt. Direction Flag (D) It is used for string instructiion (Discussed with the specific instructions later in the book). If the direction flag is set, the pointers are decremented else the pointers are incremented. 1.5.2 Bus Interface Unit (BIU) The BIU sends out addresses, fetches instructions from memory, reads data from memory and ports, and writes data to ports and memory. In other words the BIU handles all transfers of data and addresses on the buses for the execution unit. The BIU has 1. An instruction queue 2. An Instruction pointer 3. Segment registers Instruction Queue To speed up program execution, the BIU fetches as many as 6 insturction bytes ahead of time from memory. The prefetched instruction bytes are held for the EU in a first-in-first-out group of register called a queue. The EU decodes an instruction or executes an instruction which does not require the buses. When the EU is ready for its next instruction, it simply reads the instruction from the queue in the BIU. Fetching the next instruction while the current instruction executes, is called pipelining. Note: The 8088 microprocessor has only a 4-byte queue. Instruction Pointer (IP) The Instruction Pointer is a 16-bit register. This register is always used as the effective memory address, and is added to the Code segment with a displacement of four bits to obtain the physical address of the opcode. The code segment cannot be changed by the move instruction. The instruction pointer is incremented after each opcode fetch to point to the next instruction. Segment Registers The 8086 / 8088 microprocessor has 20-bit address lines. All the registers in 8086 / 8088 are 16-bits in length. Hence to obtain 20-bit addresses from the available 16-bit registers, all 8086 / 8088 memory addresses are computed by summing the contents of a segment register and a effective memory address. The effective memory address is computed via a variety of addressing modes. The process of adding, to obtain 20-bit address is as follows:

The selected segment register contents are shifted-left four bits (i.e., the contents are multiplied by 16 decimal), and then added to the effective memory address to generate the actual physical address output.
Segment Register value ( CS, DS, ES or SS) Effective Memory Address Physical Address x x x x x x x x x x x x x x x xH y y y y y y y y y y y y y y y yH wwwwwwwwwwwwwwwwwwwwH Table 1.1

The table 1.1 shows 16-bits of the segment registers CS, DS, ES or SS displaced by 4-bits to the left. The effective address is calculated depending on the type of addressing mode. The effective address is shown as yyyyyyyyyyyyyyyy. The 20-bit physical address wwwwwwwwwwwwwwwwwwww is obtained after adding the segment register value and effective address. The physical address is 20-bits wide. To understand how the segmentation is used, it is required to know the memory structure of the 8086 / 8088 microprocessor. The memory in an 8086/8088 system is a sequence of up to 220 = one million bytes. A word is any two consecutive bytes in memory (word alignment is not required). Words are stored in memory with the most significant byte at the higher memory address. These bytes are stored sequentially from byte 00000 to byte FFFFF hex. Programs view memory space as a group of segments defined by the application. A segment is a logical unit of memory that may be up to 64K bytes long. Each segment is made up of contiguous memory locations and is an independent, separately addressable unit. Each segment is assigned a base address, which is its starting location in the memory space. All segments start on 16-bit memory boundaries. Segments may be adjacent, disjoint, partially overlapped, or fully overlapped. It is as shown in fig. 1.7 The segment registers point to the four immediately addressable segments. The four segment registers are Code Segment register [points to the instruction opcode] Data Segment register [points to the data memory] Stack Segment register [points to the Stack memory] Extra Segment register [points to the data memory]
0 1 0 0 0 0 h 2 0 0 0 0 h 3 0 0 0 0 h

g m

e Sn te Ag m

n t

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r la

p e

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o u

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o u

m p

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n t

C S e g m e n t E

o v e r la

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Fig 1.7

H A

B C C D S E S D S E S F S G H

J 0 0 0 0 0 H

Fig-1.8

Fig 1.8 shows the segment registers pointing to the various memory segments. Since logical addresses are 16-bits wide, up to 64K (65536) bytes in a given segment can be addressed. Each time the CPU need to generate a memory address, one of the segment registers is automatically chosen and its contents added to a logical address. For an instruction fetch, the code segment register is automatically added to the logical address (in this case, the contents of the instruction pointer) to compute the value of the instruction address. For stack referencing the stack segment register is automatically added to the logical address (the SP or BP register contents) to compute the value of the stack address. For data reference operations, where either the data or extra segment register is chosen as the base, the logical address can be made up of many different types of values: it can be simply the immediate data value contained in the instruction, or it can be the sum of an immediate data value and a base register, plus an index register. Generally, the selection of the DS or ES register is made automatically, though provisions do exist to override this selection. Thus any memory location may be addressed without changing the value of the segment base register. In systems that use 64K or fewer bytes of memory for each memory area (code, stack, data and extra), the segment registers can be initialized to zero at the beginning of the program and then ignored, since zero plus a 16-bit offset yields a 16-bit address. In a system where the total amount of memory is 64K bytes or less, it is possible to set all segments equal and have fully overlapping segments. Segment registers are also very useful for large programming tasks, which require isolation of program code from the data area, or isolation of module data from the stack information etc. Segmentation makes it easy to build re-locatable and reentrant programs. In many cases, the task of relocating a program (relocation means having the ability to run the same program in several different areas of memory without changing addresses in the program itself) simply requires moving the program code and then adjusting the code segment register to point to the base of the new code area. Since programs can be written for the 8086 / 8088 in which all branches and jumps are relative to the instruction pointer, it does not matter what value is kept in the code segment register. Every application will define and use segments differently. The currently addressable segment override provide, a generous workspace: 64K bytes for code, 64K bytes stack and 128K bytes of data

storage. Solved Problems 1. If a physical branch address is 5A230 H when (CS) = 5200 H, what will it be if the (CS) are changed to 7800 H. CS: 52 0 0 Offset: XXXX Physical add. 5A2 3 0 H Hence Offset = Physical add - (Segment address displaced by 4-bits) Offset = 5A230 - 52000 = 8230 H If the CS is changed to 7800 H the Physical address will be 2. 78000 + 8230 = 80230 Given that the EA of a datum is 2359 H and the DS = 490B H, what is the physical address of the datum? DS: 490B0 H EA: 2359 H Physical add. 4B409

8086 Memory Addressing The 8086 memory address space can be viewed as a sequence of one million bytes in which any byte may contain an 8-bit data element and any two consecutive bytes may contain a 16-bit data element. There is no constraint on byte or word address boundaries. The address space is physically connected to a 16-bit data bus by dividing the address space into two 8-bit banks of up to 512K bytes each. One bank is connected to the lower half of the 16-bit data bus (D0 D7) and contains even address bytes. i.e., when A0 bit is low, the bank is selected. The other bank is connected to the upper half of the data bus (D8 - D15) and contains odd address bytes. i.e., when A0 is high and BHE (Bus High Enable) is low, the odd bank is selected. A specific byte within each bank is selected by address lines A1-A19.

e r r e s s B a n k ( 5 1 2 K B x H 8 E) O D D A d d A A 1 d - A 1 9 d r e s s D a t a B D 8 - D 1 5

ig

o w d B a n ( 5 1 2 E V E A d D

e r r e s s k K Ax 0 8 N 0 - D 7

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Fig. 5
Data can be accessed from the memory in four different ways. They are: 8 - bit data from Lower (Even) address Bank. 8 - bit data from Higher (Odd) address Bank. 16 - bit data starting from Even Address. 16 - bit data starting from Odd Address. 8-bit data from Even address Bank
O d d B a n k E v e n B a n k

x x x

+ + +

1 3 5 x

x + + 2 4 x

B A 1 - A 1 9 D 8 - D

H = E 1 5

1 D 0 - D

A 7

- D

1 5

Fig. 6 8-bit Data Access from Even Address

To access memory bytes from Even address, information is transferred over the lower half of the data bus (D0 - D7). The A0 is output LOW and BHE is output HIGH enabling only the even address bank. It is illustrated in fig. 6.

Example: Consider loading a byte of data into CH register (higher order 8-bits of CX register) from the memory location with an even address. The data will be accessed from the even bank via the (D0 - D7) DATA BUS. Although this data is transferred into the 8086 over the lower 8-bit lines, the 8086 automatically redirects the data to the higher 8-bits of its internal 16bit data path and hence to the CH-register. This capability allows bytes input - output transfer via the AL register to access I/O device connected to either the upper half of the data bus or the lower half of the 16-bit data bus. 8-bit Data from Odd Address Bank To access memory byte from an odd address information, is transferred over the higher half of the data bus (D8 - D15). The BHE output low enables the upper memory bank. A0 is output high to disable the lower memory bank. It is illustrated in fig. 7
O d d B a n k E v e n B a n k

x x

+ +

1 3

x x

B A 1 - A 1 9 D D 0 - D 1 5 8 - D 1 5

E= 0 D 0 - D 7

Fig. 7
16-bit Data Access starting from Even - Address
O d d B a n k E v e n B a n k

x x

+ +

1 3

x x

1 - A

1 9

8 - D

B H =E 0 1 5 D 0 - D

A 7

- D

1 5

Fig. 8
16-bit data from an even address is accessed in a single bus cycle. Address lines A1 A19 select the appropriate byte within each bank. A0 low and BHE low enables both banks simultaneously. This is illustrated in fig. 8. 16-bit Data Access starting from Odd Address A 16-bits word located at an odd address (two consecutive bytes with the least significant byte at an odd byte address) is accessed using two bus cycles. During the first bus cycle the lower byte (with the odd address 0005 as shown in fig. 9 (a)) is accessed.

10

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a n

E 0 0 4 0 0 6 0 0 8

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d d

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v e n

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0 0 0 5 0 0 0 7 0 0 0 9

0 0 0

0 0 0 0 0 0 0 0 0

1 - A

1 9 A D 8 - D 1 5 1 - A 9 D 0 - D 7

1 - A

9 A D 8 - D 1 5 1 - A 9 D 0 - D 7

( a )

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Fig.

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During the second bus cycle, the upper byte (with the even address 0006H as in fig. 9 (b)) is accessed. During the first bus cycle, A1 - A19 address bus specifies the address and A0 as 1 and BHE is low. Therefore the even memory bank is disabled and odd memory bank is enabled. During the second bus cycle, the address is incremented. Therefore A0 is zero and BHE is made high. The even memory bank is enabled and the odd memory bank is disabled. 8086 Basic System Concepts 8086 can be used either in a minimum mode system or a maximum mode system. The fig. 10 and fig. 11 shows minimum and maximum modes with groups of ICs to generate address bus, data bus and control bus signals. Using these buses, the CPU can be connected to ROM, RAM, PORTS and other devices to form a complete system. BASIC 8086 Minimum mode System 8282 I/O ports are used to latch the addresses from the 8086 Microprocessor Data/Address bus. By using three 8282, A0-A15, BHE , A16-A19 lines are latched during T1 state. OE (Output Enable) input of the 8288 I/O ports are grounded; the bus will therefore, never be floated. ALE signal from 8286 is used to strobe the addresses into the 8282 I/O latches.

Since the Data Bus is bi-directional, 8286 bi-directional bus transceivers are used, in order to create a separate Data Bus from the 8086 Address/data Bus. The DT/ R and DEN outputs from 8086 are used for 8286 "T" signal and OE inputs respectively.
Maximum Mode Configuration When MN/ MX pin is strapped to GND, the 8086 treats pin 24 through 31 to be in maximum mode. An 8288 bus controller interprets status information coded into S0, S1 and S2 to generate bus timing and control signals compatible. DEN, DT/ R and ALE control outputs, are now generated by the 8288 bus controller. The DEN from 8288 is inverted and given to 8286 transceiver to enable the output. The output enable of 8282 latch is grounded. As in minimum mode the address-data lines are latched through 8282 latch. The ALE signal from the 8288 bus controller latches the address during the T1 state of the microprocessor. The DEN signal is used to enable the transceiver either to transmit or receive data from I/O devices and memory. The DT/ R signal is used to transmit or receive the data as the need may be.

11

L K

+ 5 V R E S
C lo c k g e n e r a t o r
A A E N E N F C / 2 1

C R R

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M I/O I N T A R D W R M NM / X + 5 V

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A A

D 0 - A D 1 5 1 6 - A 1 9 B H E

8 2 8 2 L a t c h

d d r e s s

D 8 2 8 6 D TR/ D E N T O E

0 1 6

1 5

Fig. 10 8086 Minimum Mode System

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C L E E K A S D E Y T D D E N M G n d S S S 0 1 2 C L K

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A A

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D 0 - A D 1 5 1 6 - A 1 9

8 2 8 2 L a t c h

d d r e s s B H E

T O E D
r

T A

8 2 8 6 T r a n s c e i v e

Fig. 11 8086 Maximum Mode Configuration

5 Bus Read Machine Cycle Fig- 12 shows the timing diagram of 8086 read machine cycle with WAIT state. The clock (CLK) signal is obtained from the clock-generator 8284. Each cycle of the clock is referred to as a state. Minimum number of states to access a data is four. They are T1, T2, T3, and T4 states. During T1 state of a read machine cycle an 8086 first asserts the M/ IO signal. It will assert this signal high if it is going to read from memory during memory read cycle and it will assert M/ IO low if it is going to do a read from an Input port during its read cycle. The timing diagram in fig. 12 shows two lines for the M/ IO signal, because the signal may be going LOW or going HIGH for a read cycle. The point where the two lines cross indicate the time at which the signal becomes valid for this machine cycle. After asserting M/ IO , the 8086 sends out a high on the address latch enable signal, ALE. The microprocessor sends out on AD0-AD15, A16 through A19 and BHE lines, the address of

12

the memory location that it wants to read. Since the latches are enabled by ALE being high, this address information passes through the latches to their outputs. The 8086 then makes the ALE output low. This disables the latches (8282) and holds the address information latched on the latch outputs. The address information latched on the latch outputs can now be used to select the desired memory or port location. In the timing diagram, the first point at which the two (AD 0 AD15) cross represents the time at which the 8086 has put a valid address on these lines. Two lines DO NOT indicate that all 16 lines are going high or going low at this point. The crossed lines indicate the time at which a valid address is on the bus.
T C L K 1 T 2 T 3 T w a i t T 4

A B

D H

0 - A E

1 5

S -2

M I O / R R D D W D E T R E R A / N D Y

Fig. 12 Read Timing Diagram

Since the address information is now held on the latch, the 8086 does not need to send it out any more. As shown in fig. 12 the 8086 floats the AD0 - AD15 lines so that they can be used to input data from memory or from a port. At about the same time the 8086 also remove the BHE and A16-A19 information from the upper lines and sends out some status information on these lines. The 8086 is now ready to read data from the addressed memory locations or port. During T2-state the 8086 asserts its RD signal low. This signal is used to enable the addressed memory device or port device. At the end of T3 state the microprocessor makes the RD signal high and reads the data available on the data bus, provided the READY input signal is high. It is the duty of the external circuit to see that valid data is made available on the data bus. If the READY input pin is not high at the sampled time in a machine cycle, the 8086 will insert one or more WAIT states between T3 and T4 states in that machine cycle. An external hardware device is set up to pulse READY low before the rising edge of the clock in T2 state. After the 8086 finishes T3 of the machine cycle, it enters a WAIT state. If the READY input is still low at the end of a WAIT state, then the 8086 will insert another WAIT state. The 8086 will continue inserting WAIT states until the READY input is sampled high again. If the READY input is sampled high again during T3 or during the WAIT state, the microprocessor comes out of the WAIT state and will initiate T4 of the machine cycle.

13

The DEN signal is used to enable bi-directional buffers on the data bus. The data enable signal, DEN, from the 8086 will enable the data buffer when it is asserted LOW. The data transmit / receive signal DT/ R from the 8086 is used to specify the direction in which the buffers are enabled. When DT/ R is asserted high, the buffers will, if enabled by DEN, transmit data from the 8086 to Memory or I/O ports. When DT/ R is asserted low, the buffers, if enabled by DEN, will allow data to be received from Memory or I/O ports of the 8086. DT/ R is asserted during T1 of the machine cycle. The DEN is asserted after the 8086 finishes using the data bus to send the lower 16 address bits. BUS Write Machine Cycle The 8086 write operation is very similar to the read cycle. During T1 of a write machine cycle the 8086 asserts M/ IO low if the write is going to a port and it asserts M/ IO high if the write is going to memory. At about the same time the 8086 raises ALE high to enable the address latches. The 8086 then assert BHE and on the lines AD0 - AD19, it output the address that it will be writing to. When writing to a port, line A16 - A19 will always be low, because the 8086 only sends out 16-bits port addresses. The 8086 brings ALE low again to latch the address on the outputs of the latches. In addition to holding the address, the latches also function as buffers for the address lines. After the address information is latched, the 8086 remove the address information from AD0 - AD15 and outputs the desired data on these lines.

Fig 13 Write Timing Diagram

If the READY input is sampled LOW by the 8086 before or during T2 of the machine cycle, the 8086 will insert a WAIT state after T3. If the READY input is sampled high before the end of the WAIT state, the 8086 will go on with state T4 as soon as it completes the WAIT state. The 8086 will continue to insect wait states for as long as the READY is sampled low just before the end of each WAIT state.

14

Comparison of 8086 with the 8088 Microprocessor The 8088 CPU is an 8-bit processor designed around the 8086 internal structure. Most internal functions of the 8088 are identical to the equivalent 8086 functions. The 8088 handles the external bus the same way the 8086 does, one difference being hat the 8088 handles only 8-bits at a time. 16-bit operands are fetched or written in two
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7 ( 8 ) 8 - A 1 5 ( 8 ) 3 ( 4 ) 6 T e s t R R e a d y e s e t

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Fig . 14 Pin Configuration of 8088 Microprocessor

consecutive bus cycles. To an assembly language programmer both processors will appear identical with the exception of execution times. The internal register structure is identical and all instructions produce the same end result. The pin configuration of 8088 is illustrated in fig. 14. The major differences between 8088 and 8086 are outlined below: The queue length is 4 bytes in the 8088, where as the 8086 queue comprises of 6 bytes. The 8088 BIU will fetch a new instruction to load into the queue as soon as it finds a byte hole (space available) in the queue. The 8086 waits until a 2 byte space is available. The internal execution time of the instruction set is affected by the 8-bit interface. All 16-bit fetches and writes from / to memory take an additional four clock cycles. The CPU is also limited by the speed of instruction fetch. When the more sophisticated instructions of the 8088 are being used, the queue has time to fill and the execution proceeds as fast as the execution unit will allow. The hardware interface of the 8088 has some major differences as compared to the 8086. The pin assignments are nearly identical, however, with the following functional changes. A8-A15: These pins are only address outputs on the 8088. These address lines are latched internally and remain valid throughout a bus cycle in a manner similar to the 8085 upper address lines. SS0 provides the S0 status information in the minimum mode. This output occurs on pin 34 in minimum mode only. DT/ R , IO/ M and SS0 provide the complete bus status in minimum mode. This is shown in table 5

IO/M DT/R
0 0 0 0 0 0 1 1

SSO
0 1 0 1

CHARACTERISTICS
Code Access Read Memory Write Memory Passive

15

1 1 1 1

0 0 1 1

0 1 0 1

Interrupt Acknowledge Read I/O port Write I/O port Halt

Table 5 BHE has no meaning on the 8088 and has been eliminated. IO/ M has been inverted. i.e., (In 8086, this pin as IO /M)
ALE is delayed by one clock cycle in the minimum mode when entering HALT to allow the status to be latched with ALE. Fig 15 illustrates the 8088 microprocessor system configuration. The Address-Data lines AD0-AD7 are connected to the 74LS373 latch. The address from the multiplexed bus is latched into the 74LS373 when an ALE (Address latch enable) is active during T1 state of the microprocessor. The address A0-A7 is available on the output of 74LS373 and can be used for memory (along with A16-A19), and I/O devices. The address lines A8-A15 are not multiplexed with data lines or status lines, hence there is no need to latch these address lines. The data bus is connected to the 74LS245 transceiver. The 74LS245 is controlled by DT/ R and DEN to transmit and receive and Data respectively. Since 74LS373 and 74LS245 are also buffered chips, it is not required to add buffers to these chips. The address lines A8-A15 need to be buffered and hence the 74LS 244 buffer is used for these lines. The output of 74LS244 is always enabled.

1 9 / S

1 6 / S

O
3

A 3 7 3

1 9

1 6

7 4 L S A L E
A 1 5 A 8

G 7 4 L S 2 4 4 O G O E E

8 0 8 8
A D 0 A D 7

7 4 L S

A 0 3 7 3

TR /

N D 0 D 7 7 4 L S G D R/ 2 4 4

Fig. 15

1. Compare 8086 and 8088 microprocessors. In what ways are they similar? In what ways do they differ? 2. What is the purpose of the ALE signal in an 8086 system? 3. What is the major difference between an 8086 operating in minimum mode and an 8086 operating in maximum mode? 4. Describe the response of an 8086 when its RESET input is asserted high.

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5. Why are buffers often needed on the address, data and control buses in a microprocessor system? 6. What are the function of the 8086 DT/ R and DEN signals? 7. Explain the difference between a memory read cycle and an I/O read cycle. 8. What are the main functions provided by the 8288 bus controller when used with the 8086/8088 maximum mode operation? 9. Explain the operation of the LOCK pin. 10. What conditions do the QS1 and QS0 pins indicate about the 8086/8088? 11. What three house keeping chores are provided by the 8284 clock generators? 12. Explain the operation of the TEST pin and the WAIT instruction. 13. What is the function of QS0 and QS1 signals? 14. With a timing diagram explain I/O read machine cycle. 15. With a timing diagram explain I /O Output-Write machine cycle with two wait states. 16. Mention an affiliation of the OSC signal in 8284? 17. What is the application of the PCLK signal? 18. Briefly describe the purpose of each of the T-states T1, T2, T3 and T4. 19. What is the purpose of the status bits S3 and S4?

Objective Type Questions

1. State true or false (a) Both the address and data bus are unidirectional. (b) Both the 8086 and 8088 microprocessors address 64 K bytes of memory. (c) No difference exits between the memory maps of 8086 and 8088. (d) The string source (SI) is located in the Data Segment (DS) and the string destination is located in the Extra segment (ES) for string instructions. 2. The INTR input is -- sensitive. 3.. The 8286 microprocessor has a 1-bit data bus. Its memory is organized into -- banks, each--bit wide. 4. A microprocessor with a 24-bit address bus could access --- MB of memory. 5. A bus cycle is equal to clocking --- periods. 6. If the ready pin is grounded, it will introduce ---state into the bus cycle. 7. The PCLK output of the 8284A is --- MHz if the crystal frequency is 14 MHz. 8. The RES input to the 8284A is placed at a logic --- level in order to reset the 8086/8088. 9. The 8086 and 8088 processor can be operated in either the minimum or maximum mode. The maximum mode is so named because the maximum mode (a) Let you execute the maximum number of instructions. (b) Let you address the maximum number of memory locations (IMB) (c) Requires more support hardware than the minimum mode. (d) All of the above. 10. The 8086/8088 use a multiplexed address and data bus because (a) 40 pins is a good size for the IC. (b) Multiplexing is supported by 8085 Microprocessor.

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(c) Multiplexing reduces the number of lines between the microprocessor and the auxiliary Ics. (d) All of the above. The DEN signal is active ------- output from 8288 bus controller. 12. An 8086/8088 microprocessor requires -------- and ------- chips is maximum mode systems configuration. 13.The 8288 bus controller must be used in the ------ mode to provide ------ signals to the memory and I/O. 14. 8088 microprocessor does not required latch for a A8 A15 lines because ---------. 15. SSO of 8088 microprocessor indicates -------.

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Pin Configuration G A A A A A A A A A A A A A A A N I N C G N D D D D D D D D D D D D D D D M T L N
1D 12 13 14 15 16 79 88 97 16 15 14 13 12 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

4 3 2 1 0

0 1 2 3 4

8 0 8 6

11 5 10 6 1 I7 1R 8 1K 9 2D 0

V c c A D 1 5 A 1 6 / S 3 A 1 7 / S 4 A 1 8 / S 5 A 1 9 / S 6 B H/ S E 7 M M N X/ R D R / G G T ( 0H O L D R / Q G T ( 1H L D A L O (C K )W R S 2( M / I) 0 S 1( D T / )R S 0( D E )N Q S 0 ( A L E ) Q SI N 1 T ( A ) T E S T R E A D Y R E S E T

) )

Fig. .1 Pin Configuration

The following pin function descriptions are for the microprocessor 8086 in either minimum or maximum mode. The 8086 pins signals are TTL compatible. AD0 - AD15 (I/O): Address Data Bus These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1) and data during T2, T3 and T4 clock cycles. A0 is analogous to BHE for the lower byte of the data bus, pins D0-D7. A0 bit is Low during T1 state when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. 8-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions. These lines are active high and float to tri-state during interrupt acknowledge and local bus "Hold acknowledge". Fig. 2 shows the timing of AD0 AD15 lines to access data and address.
T 4 T 1 T 2 T 3 T 4

1 5

d d r e s s

a t a

Fig. .2
A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status During T1 state these lines are the four most significant address lines for memory operations. During I/O operations these lines are low. During memory and I/O operations, status information is available on these lines during T2, T3, and T4 states.

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S5: The status of the interrupt enable flag bit is updated at the beginning of each cycle. The status of the flag is indicated through this bus. S6: When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock period, the 8086 tri-states the S6 pin and thus allows another bus master to take control of the status bus. S3 & S4: Lines are decoded as follows:

A17/S4
0 0 1 1

A16/S3
0 1 0 1

Function
Extra segment access Stack segment access Code segment access Data segment access

Table 1
After the first clock cycle of an instruction execution, the A17/S4 and A16/S3 pins specify which segment register generates the segment portion of the 8086 address. Thus by decoding these lines and using the decoder outputs as chip selects for memory chips, up to 4 Megabytes (one Mega per segment) of memory can be accesses. This feature also provides a degree of protection by preventing write operations to one segment from erroneously overlapping into another segment and destroying information in that segment.

BHE /S7 (O): Bus High Enable/Status

During T1 state the BHE should be used to enable data onto the most significant half of the data bus, pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to control chip select functions. BHE is Low during T1 state of read, write and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status information is available during T2, T3 and T4 states. The signal is active Low and floats to 3-state during "hold" state. This pin is Low during T1 state for the first interrupt acknowledge cycle. RD (O): READ The Read strobe indicates that the processor is performing a memory or I/O read cycle. This signal is active low during T2 and T3 states and the Tw states of any read cycle. This signal floats to tri-state in "hold acknowledge cycle".

TEST (I) TEST pin is examined by the "WAIT" instruction. If the TEST pin is Low, execution
continues. Otherwise the processor waits in an "idle" state. This input is synchronized internally during each clock cycle on the leading edge of CLK. INTR (I): Interrupt Request It is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector look up table located in system memory. It can be internally masked by software resetting the interrupt enable bit INTR is internally synchronized. This signal is active HIGH.

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NMI (I): Non-Muskable Interrupt An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt vector look up table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH on this pin initiates the interrupt at the end of the current instruction. This input is internally synchronized. Reset (I) Reset causes the processor to immediately terminate its present activity. To be recognised, the signal must be active high for at least four clock cycles, except after power-on which requires a 50 Micro Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros. It also initializes CS to FFFF H. Upon removal of the RESET signal from the RESET pin, the 8086 will fetch its next instruction from the 20 bit physical address FFFF0H. The reset signal to 8086 can be generated by the 8284. (Clock generation chip). To guarantee reset from power-up, the reset input must remain below 1.5 volts for 50 Micro sec. after Vcc has reached the minimum supply voltage of 4.5V. The RES input of the 8284 can be driven by a simple RC circuit as shown in fig.3.
X X F C/ + 5 V N R R R o e r m s e a l C e y S Y S T E M R E S E T E S R E S E T 1 2 C L K C L K

8 2

4
R E

8
S

0 8
E T

Fig. .3
The value of R and C can be selected as follows: Vc (t) = V (1 - e -t /RC) t = 50 Micro sec. V = 4.5 volts, Vc = 1.05V and RC = 188 Micro sec. C = 0.1 Micro F; R = 1.88 K ohms.

Contents Flags Cleared Instruction Pointer 0000H CS register FFFFH DS register 0000H SS register 0000H ES register 0000H Queue Empty Table .2 System Registers after Reset
8086/88 RESET line provide an orderly way to start an executing system. When the processor detects the positive-going edge of a pulse on RESET, it terminates all activities until the signal goes low, at which time it initializes the system as shown in

CPU component

table .2.

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Ready (I) Ready is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The READY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met. CLK (I): Clock Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33% duty cycle to provide optimized internal timing. Minimum frequency of 2 MHz is required, since the design of 8086 processors incorporates dynamic cells. The maximum clock frequencies of the 8086-4, 8086 and 8086-2 are
X X F C/ 1 2 R C E E L K A S D E Y T

8284

C R A A V c c R R

s y n c D E E D Y N N Y 1 1 2 2

8 0 8 6

L K S Y S T E M R E S E T

Fig..4
4MHz, 5MHz and 8MHz respectively. Since the 8086 does not have on-chip clock generation circuitry, and 8284 clock generator chip must be connected to the 8086 clock pin. The crystal connected to 8284 must have a frequency 3 times the 8086 internal frequency. The 8284 clock generation chip is used to generate READY, RESET and CLK. It is as shown in fig..4 MN/ MX (I): Maximum / Minimum This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself generates all bus control signals. In maximum mode the three status signals are to be decoded to generate all the bus control signals. Minimum Mode Pins The following 8 pins function descriptions are for the 8086 in minimum mode; MN/ MX = 1. The corresponding 8 pins function descriptions for maximum mode is explained later. M/ IO (O): Status line This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it accesses I/O and when high it access memory. M / IO becomes valid in the T4 state preceding a bus cycle and remains valid until the final T4 of the cycle. M/ IO floats to 3 - state OFF during local bus "hold acknowledge".

WR (O): Write

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Indicates that the processor is performing a write memory or write IO cycle, depending on the state of the M / IO signal. WR is active for T2, T3 and Tw of any write cycle. It is active LOW, and floats to 3-state OFF during local bus "hold acknowledge ".

INTA (O): Interrupt Acknowledge

It is used as a read strobe for interrupt acknowledge cycles. during T2, T3, and T4 of each interrupt acknowledge cycle. It is active LOW

ALE (O): Address Latch Enable ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an active high pulse during T1 of any bus cycle. ALE signal is never floated. DT/ R (O): DATA Transmit/Receive In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the direction of data flow through the transceiver. This signal floats to tri-state off during local bus "hold acknowledge". DEN (O): Data Enable It is provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. DEN is active LOW during each memory and IO access. It will be low beginning with T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until the middle of T4. It floats to tri-state off during local bus "hold acknowledge". HOLD & HLDA (I/O): Hold and Hold Acknowledge Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged, HOLD must be active HIGH. The processor receiving the "HOLD " request will issue HLDA (HIGH) as an acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue of HLDA, the processor will float the local bus and control lines. After "HOLD" is detected as being Low, the processor will lower the HLDA and when the processor needs to run another cycle, it will again drive the local bus and control lines. Maximum Mode The following pins function descriptions are for the 8086/8088 systems in maximum mode (i.e.. MN/ MX = 0). Only the pins which are unique to maximum mode are described below.

.
S2, S1, S0 (O): Status Pins These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller to generate all memory and I/O operation) access control signals. Any change by S2, S1, S0 during T4 is used to indicate the beginning of a bus cycle. These status lines are encoded as shown in table 3. S2 0 0 S1 0 0 S0 0 1 Characteristics Interrupt acknowledge Read I/O port

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0 0 1 1 1 1

1 1 0 0 1 1

0 1 0 1 0 1

Write I/O port Halt Code access Read memory Write memory Passive State

Table 3
QS0, QS1 (O): Queue Status Queue Status is valid during the clock cycle after which the queue operation is performed. QS0, QS1 provide status to allow external tracking of the internal 8086 instruction queue. The condition of queue status is shown in table 4. Queue status allows external devices like In-circuit Emulators or special instruction set extension co-processors to track the CPU instruction execution. Since instructions are executed from the 8086 internal queue, the queue status is presented each CPU clock cycle and is not related to the bus cycle activity. This mechanism allows (1) A processor to detect execution of a ESCAPE instruction which directs the coprocessor to perform a specific task and (2) An in-circuit Emulator to trap execution of a specific memory location.

QS1
0 0 1 1

QS1
0 1 0 1

Characteristics
No operation First byte of opcode from queue Empty the queue Subsequent byte from queue

Table 4 LOCK (O)

It indicates to another system bus master, not to gain control of the system bus while LOCK is active Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active until the completion of the instruction. This signal is active Low and floats to tri-state OFF during 'hold acknowledge". Example: LOCK XCHG reg., Memory ; Register is any register and memory GT0 ; is the address of the semaphore.

RQ / GT0 and RQ / GT1 (I/O): Request/Grant

These pins are used by other processors in a multi processor organization. Local bus masters of other processors force the processor to release the local bus at the end of the processors current bus cycle. Each pin is bi-directional and has an internal pull up resistors. Hence they may be left un-connected.

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