10/24/2024

FACULTY OF ENGINEERING AND NATURAL SCIENCES

ELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT (EEED)

DIGITAL LOGIC DESIGN

EEE 201

PROF. Dr. Indrit Myderrizi

IV

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OUTLINE
➢ Logic Gates
➢ Basic Logic Gates
➢ Universal Logic Gates
➢ Universal Set of Operations
➢ Level of Gates in Logic Circuits
➢ Logic Circuits
➢ Operator Precedence
➢ Examples of Logic Circuit Implementations
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TYPES OF GATES

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Basic Logic Gates

1 X Y F=XY
AND gate x
0 0 0 0
1
y 0 1 0
X 0
F=XY 1 1 0 0
F
Y 0 1 1 1
time

OR gate
X Y F=X+Y
1
x
0 0 0 0
X 1
y 0 1 1
F=X+Y 0
Y F
1
1 0 1
0
t ime
1 1 1
NOT gate - Inverter
X X’ (X’)’
NOT X Y 0 1 0
X Y X X’ (X’)’=X 1 0 1
0 1
1 3 0 3
Y = X’ Buffer

Universal Logic Gates

NAND gate
X Y W Z=(XY)’
X 0 0 0 1
Z=(XY)’
Y NOT-AND 0 1 0 1
1 0 0 1
X W 1 1 1 0
Z=(XY)’
Y

NOR gate

X
X Y W Z=(X+Y)’
Z=(X+Y)’
Y 0 0 0 1
NOT-OR
0 1 1 0
X W 1 0 1 0
Z=(X+Y)’ 1 1 1 0
Y 4

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Exclusive Gates
XOR/Exclusive-OR gate
X Y XY
0 0 0
X
Z=XY 0 1 1
Y 1 0 1
1 1 0
Z=X’Y+XY’

XNOR/Exclusive-NOR gate
X Y (XY)’
0 0 1
X 0 1 0
Z=(XY)’
Y 1 0 0
1 1 1
Z=(X’Y+XY’)’=XY+X’Y’

• The number of inputs to a gate is referred as its fan-in.

• The number of gate inputs driven by, or loading, the output of a single gate is called the fan-out of the 5
driving gate.

Alternative Forms of NAND and NOR Gates

De Morgan’s law (ii)

De Morgan’s law (i)

Alternative Structures for XOR Gate

xy=xy’+x’y=(x+y)(x’+y’)
=(xy+x’y’)’=[(x+y’)(x’+y)]’

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UNIVERSAL SET OF OPERATIONS

Switching algebra was introduced in terms of two binary operations (AND and OR) and one unary operation
(NOT). Every switching expression is made up of variables connected by various combinations of these three
operators.
A set of operations is called universal or functionally complete if every switching function can be expressed
exclusively in terms of operations from this set.

➢The set of operations {AND, OR, NOT} is universal

x NAND y: (xy)' = x' + y'
x NOR y: (x + y)' = x'y‘
AND operation, xy. By De Morgan’s law:
xy = (x' + y')'
AND can be expressed in terms of OR and NOT ➔ the set {AND, OR, NOT} can be expressed in terms of
the set {OR, NOT}.
➢The set {OR, NOT} is a universal set.
➢The set {AND, NOT} is a universal set.
NOT operation x’. By idempotency and De Morgan’s laws: x' = x' + x' = (xx)'
AND operation, xy. By involution and idempotency laws: xy = ((xy)')' = [(xy)' (xy)']‘
➢The set {NAND} is a universal set.
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➢The set {NOR} is a universal set.

➢ Complete sets

{AND, OR, NOT} Not a minimal complete set

{AND, NOT}

{OR, NOT}
Minimal complete sets
{NAND}

{NOR}

➢ Minimal complete set

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➢ A complete set with no redundant elements

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• Any switching function can be expressed exclusively in terms of NAND operations.

• Any switching function can be expressed exclusively in terms of NOR operations.

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LEVEL OF GATES IN LOGIC CIRCUITS

⚫ The maximum number of gates cascaded in series between a circuit input and the output
⚫ Usually, all variables and their complements are available as circuit inputs

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Four-Level Realization of Z

Example: Show the number of levels for the following circuit.

This is an example of a two-level circuit. The number of levels is the maximum number of gates
through which a signal must pass from the input to the output. In this example, all signals go first
through an AND gate and then through an OR.
When inputs are available both uncomplemented and complemented, implementations of both SOP 12
and POS expressions result in two-level circuits.

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LOGIC CIRCUITS
⚫ Gates are interconnected together to form circuits that perform more complex functions → Logic Circuits

Example: Logic diagram for function a + b’c

Example: Logic diagram for function ((ab + bc’)a)’

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Operator Precedence
✓ Inversions of single terms
✓ All operations with parentheses
✓ AND operation before an OR operation unless parentheses indicate otherwise
✓ If an expression has a prime sign (or bar over it), perform the operations inside the expression
first and then invert the result

Example: Show logic diagram for F= A’BC(A+D)’

F= A’BC(A+D)’

NOR gate can be used

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Example: Implement the following Boolean function using a logic circuit.

Let’s begin inside the parentheses and build an AND gate with inputs x and z. The output of that goes
to an OR gate, the other input of which is w’. That is ANDed with v, which is ORed with the input z’
and the output of the AND gate, producing wx’y, which results in the circuit below.

This is a four-level circuit because the signals x and z pass first through an AND gate, then an OR,
then an AND, and finally through an OR—a total of four gates. 15

Example: Implement a three-input OR gate (or AND) by using only two-input gates.

Example: Implement a two-input AND gate (or OR) by using only three-input gates.
We can connect the same signal to two of the inputs (since aa = a, and a + a = a)

Also, we could connect a logic 1 (5 V) to one of the inputs of an AND or a logic 0 (ground) to one of
the inputs of an OR:

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Example: Using AND, OR and NOT gates implement the function given
with the truth table. If possible implement a minimal-cost realization for
this logic circuit.
From the truth table the function can be written in canonical SOP form,

(idempotence)
(commutativity)

(distributivity)

(identity element)

Canonical SOP realization

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Minimal-cost realization

Only NAND Gates Implementation

Example: Implement the following Boolean function using a) AND, OR gates, b) only NAND gates.

a) Circuit with only uncomplemented inputs Circuit with complemented inputs

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b) Only NAND gate implementation Minimal-cost NAND gate implementation

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Only NOR Gates Implementation

Example: Implement the following Boolean function using a) NOT, OR, and AND gates, b) only NOR
gates.

Instead of using the minterms, we can specify this function as a product of maxterms

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a) POS implementation (NOT, OR, AND gates) b) Only NOR gates implementation

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