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BEE213051

Asic design and fpga assingment created by Saad Ahmed

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Saad Ahmed
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10 views6 pages

BEE213051

Asic design and fpga assingment created by Saad Ahmed

Uploaded by

Saad Ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Capital University of Science and Technology, Islamabad

Department of Electrical & Computer Engineering

SAAD AHMED
BEE213051
Assignment # 1
ASIC DESIGN & FPGA
SUBMITTED TO
Dr. Imtiaz Ahmed Taj
DATE
14-OCT-2024
HALF ADDER MODULE

module HA(sum,cout,a,b);

input a,b;
output sum, cout;

xor g1(sum,a,b);
and g2(cout,a,b);

endmodule

Saad Ahmed 2|Page


BEE213051 Capital University of Science & Technology
FULL ADDER MODULE

module FA(sum,cout,a,b,cin);

input a,b,cin;
output sum,cout;
wire w1, w2, w3;
HA FA1(.a(a), .b(b), .sum(w1),.cout(w2));

HA FA2(.a(w1), .b(cin), .sum(sum),.cout(w3));

or g3(cout,w3,cin);

endmodule

Saad Ahmed 3|Page


BEE213051 Capital University of Science & Technology
4-BIT FULL ADDER MODULE

module 4BFA (sum,cout,a,b,cin);

input [3:0]a,b;
input cin;

output [3:0]sum;
output cout;

wire c1, c2, c3;

FA 4bfa0(.a(a[0]), .b(b[0]), .sum(sum[0]), .cin(cin), .cout(c0) );

FA 4bfa1(.a(a[1]), .b(b[1]), .sum(sum[1]), .cin(c0), .cout(c1) );

FA 4bfa2(.a(a[2]), .b(b[2]), .sum(sum[2]), .cin(c1), .cout(c2) );

FA 4bfa3(.a(a[3]), .b(b[3]), .sum(sum[3]), .cin(c2), Cout(cout));

endmodule

Saad Ahmed 4|Page


BEE213051 Capital University of Science & Technology
16-BIT FULL ADDER

module 16BFA(sum,cout,a,b,cin);

input [15:0]a,b;
input cin;

output [15:0]sum;
output cout;
wire c0, c1, c2;
FA 16bfa0(.a(a[3:0]), .b(b[3:0]), .sum(sum[3:0]), .cin(cin), .cout(c0) );

FA 16bfa1(.a(a[7:4]), .b(b[7:4]), .sum(sum[7:4]), .cin(c0), .cout(c1) );

FA 16bfa2(.a(a[11:8]), .b(b[11:8]), .sum(sum[11:8]), .cin(c1), .cout(c2) );

FA 16bfa3(.a(a[15:12]), .b(b[15:12]), .sum(sum[15:12]), .cin(c2), .cout(cout));

endmodule

Saad Ahmed 5|Page


BEE213051 Capital University of Science & Technology
TEST BENCH FOR 16-BIT FULL ADDER

module 16-BITFA_TB

reg clk;
reg [15:0] a, b;
reg cin;
wire [15:0] sum;
wire cout;

16-BITFA FA_16-BIT( .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout) );

initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
for (int i = 0; i < 2**16; i++) begin
a = i;
for (int j = 0; j < 2**8; j++) begin
b = j;
cin = 0;
@(posedge clk);
$display("a = %h, b = %h, cin = %h, sum = %h, cout = %h", a, b, cin, sum, cout);
cin = 1;
@(posedge clk);
$display("a = %h, b = %h, cin = %h, sum = %h, cout = %h", a, b, cin, sum, cout);
end
end
$finish;
end

endmodule

Saad Ahmed 6|Page


BEE213051 Capital University of Science & Technology

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