UA3302 Fairchild Semiconductor
UA3302 Fairchild Semiconductor
MA2901 • MA3302
LOW-POWER, LOW-OFFSET VOLTAGE QUAD COMPARATORS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The I"A 139 series consists of four independent precision
voltage comparators designed specifically to operate from a single power supply. CONNECTION DIAGRAM
Operation from split power supplies is also possible and the low power supply current 14-PIN DIP
drain is independent of the supply voltage range. Darlington connected PNP input
PACKAGE OUTLINES 6A 9A
stage allows the input common-mode voltage to include ground.
PACKAGE CODES D P
INPUT 1- 4
v,
ORDER INFORMATION
6-13
ELECTRICAL CHARACTERISTICS IV+ ~ 5 V, Note 4)
Input Offset Current liNI') - I,N(-) ±100 ±150 ±100 ±150 50 200 300 nA ~
Input Bias Current IIN{+) or IIN(-) with Output in 300 400 300 400 200 500 1000 nA •
1::
Linear Range
l>
Input Common-Mode 0 V+-2.0 0 V+-2.0 0 V+-2.0 0 V'-2.0 0 N
V'-2.0 0 V'-2.0 V CO
Voltage Range o.....
Saturation Voltage V'N(-) > 1.0 V, V'N(') = 0,
Islnk:::; 4 mA
700 700 700 700 400 700 700 mV •
1::
l>
Output Leakage V'N(') ? 1.0 V, V'N(-) = 0, 1.0 1.0 1.0 1.0 1.0 1.0 Co)
Il A Co)
Current Vo ~ 30 V o
N
Differential Input Keep all V,N's:> 0 V (or V-, V, V, 36 36 0 V, Vee V
Voltage if used), (Note 8)
FAIRCHILD. J,lA139/239/339. J,lA139A/239A/339A. J,lA2901· J,lA3302
NOTES:
e
1. For operating at high temperatures, the ~A339/~A339A, "A2901 ~A3302 must be derated based on a 125° maximum junction temperature and a thermal
resistance of 125°C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The ~A13g and ~A139A~
must be derated based on a 1500 C maximum junction temperature. The low bias dissipation and the "ON-OFF" characteristic of the outputs keeps the-
•
chip dissipation very small (Po:5 100 mWl, provided the output transistors are allowed to saturate.
2. Short circuits from the output to V+ can cause excessive heating and eventual destruction. The maximum output current is approximately 20 rnA inde-
pendent of the magnitude of V+.
3. This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP
transistors becoming forward biased and thereby acting as input diode clamps. In addition tiode action, there is also lateral NPN parasitic transistor
action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage levellorto ground for a large over-
drive) for the time duration that an input is driven negative. This is not destructive and normal output states will reestablish when the input voltage, which
negative, again returns to a value greater than -0.3 V.
4. These specifications apply for V+ = 5.0 V and -55°C:::; TA:::; +125°C, unless otherwise stated. With the .uA239/.uA239A,all temperature specifications
are limited to -25° e:s TA:S +85° e, the ~A339/ ~A339A temperature specifications are limited to 0° e:s TA:S +70 0 e, and the :,A290t, ~A3302temperature
range is _40° C :::; T A :::; +85° C.
5. The direction of the input current is out of the Ie due to the Pr<JP input stage. This current is essentially constant, independent olthe state olthe output so
no loading change exists on the reference or input lines.
6. The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-
mode voltalge range is V, -t.5 V, but either or both inputs can go to +30 V without damage.
7. The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be obtained; see typical performance
characteristics section.
8. Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, com-
parator will provide a proper output state. The low input voltage state must not be less than -0.3 V or 0.3 V below the magnitude of the negative power
supply, if used.
9. At output switch point, Va" 1.4 V, As = all with V' from 5 V; and over the full input common-mode range 10 V to V' -1.5 VI.
to. For input signals that exceed Vee, only the overdriven comparator is affected. With a 5 V supply, VIN should be limited to 25V max,and a limiting resistor
should be used on all inputs that might exceed the positive supply.
6-15
FAIRCHILD. MA139/239/339. MA139A/239A1339A. MA2901· MA3302
~ V"\A-
~
-55"C
0.4
~ ~
t '".. TA
II
+125"C ;!;
I 20 :!"
'" ~V
" 0.2
en T\ +1re
I".Tj TA ~ +2~f- I
0.0 1
'l; V " TA ~ +125oe
00
RL . I
I
I
I 0
== -:[OOC ;
0.00 ,~
10 20 30 40 10 20 30 40 0.01 0.1 1.0 10 100
SUPPLY VOLTAGE - V y. - SUPPLY VOLTAGE - V '0 - OUTPUT SINK CURRENT - rnA
.0
20mY z>
:> I 3.0 .1 I 15mY
.0 + Your-
Iw
~~ 2. 0
1 20mV II I
.0
10DmY
- ~~ 1. 0
I I I I +5.0 V _
T
~~ 10;
"~IT'
0 0
I I I ::l~
I I I 0." -
Your
i!:o SO f-
Yi -- 50e
0
0.5 1.0
++~-
1.5 2.0
0
I
0.5 1.0
T
1.5 2.0
TIME -J..<s TIME-~s
V '"TA'" -400C
~ TA j-40 C_ r - f--
0 >
--+
I
~ V 1
I
~60
w I/.
I ,/ -.1000 1: a: 1 ~" A~
~1.0
.....- a:
".. 40
u
TA ooe a
>
TA == +85"C
TA;' +25°C ........ ~ ~
ita: L ~ o.1
"~ 0.8 '" .....- .....- TA +25°C
" ~~
iii
T A L 1 = f-- - ~
-
~
,/
I "'" ~ ~ 'TFooe
I .0.6
.... ~+85°C
~ 20
- TA 1'85°le
~ 0.0 1
;
I ./ ~ 7
Tf . _,ooe.
V 1 I ~7
o 0.00 1
0 10 20 3 40 o 10 20 30 40 .0.01 0.1 10 100
V' - SUPPLY VOLTAGE - V V' - SUPPLY VOLTAGE - V '0 - OUTPUT SINK CURRENT - rnA
I I-'" » l IT
~'~
.0 S'";;" 4 .0
.0
20 mY z>
:> I 3 .0
I 15mv
I Iw 120mv III
.0
100 mV
+. VOUT-
~~ 2
.0
I II T+ 5.0V _
0 - ~5 1.0
r "~IT'
\. 11 I J
0 g~ 0
I I I· ~I!: 100
0 I I I 0."
!:o 50 f- TI~ e f-f-
+ VOUT
-
-100
J~A-125~-
_I 0 1 0
I I I
0.5 1.0 1.5 2.0 0.5 1.0 1.5 2.0
TIME-J,.<s TlME-J,.<5
6-16
FAIRCHILD. p,A139/239/339. p,A139A/239A/339A. p,A2901. p,A3302
APPLICATION HINTS
The fJ.A 139 series are high-gain, wide-bandwidth devices which, like most comparators, can easily
oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via
stray capacitance. This shows up only during the output voltage transition intervals as the compar-
ator changes states. Power supply bypassing is not required to solve this problem. Standard PC
board layout is helpful as it reduces stray input-output coupling. Reducing the input resistors to
< 10 kn reduces the feedback signal levels and finally, adding even a small amount (1.0to 10 mVI of
positive feedback (hysteresis I causes such a rapid transition that oscillations due to stray feedback
are not possible. Simply socketing the IC and attaching resistors to the pins will cause
input-output oscillations during the small transition intervals unless hysteresis is used. If the
input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required.
The bias network of the fJ.A 139 series establishes a drain current which is independent of the mag-
nitude of the power supply voltage over the range of from 2 V to 30 V.
It is usually unnecessary to use a bypass capacitor across the power supply line.
The differential input voltage may be larger than V+ without damaging the device. Protection
should be provided to prevent the input voltages from going negative more than -0.3 V lat 25° CI.
An input clamp diode can be used as shown in the applications section.
The output of the fJ.A139 series is the uncommitted collector of a grounded-emitter npn output
transistor. Many collectors can be tied together to provide an output ORing function. An output
pull-up resistor can be connected to any available power supply voltage within the permitted
supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage
•
which is applied to the V+ terminal of the fJ.A139 package. The output can also be used as a simple
SPSTswitch to ground (when a pull-up resistor is not used I. The amount of current which the out-
put device can sink is limited by the drive available (which is independent of V+I and the f3 of this
device. When the maximum current limit is reached (approximately 16 mAl, the output transistor
will come out of saturation and the output voltage will rise very rapidly. The output saturation
voltage is limited by the approximately 60 n saturation resistance of the output transistor. The
low offset voltage of the output transistor (1 mVI allows the output to clamp essentially to ground
level for small load currents.
39 k 3.0 k
ol t
100pF
~~~__~~;
tok
lOOk v"
lN914
lOOk
100k
Co-"""",..--'
0.001 F
v~:r
"0" "1"
1.0M
OR GATE
200k 3.0k
lOOk 15k
51k
V>=rL lOOk
o Ro-¥A........- - - ;
6-17
FAIRCHILD· IlA139/239/339. IlA139A/239A/339A. IlA2901. IlA3302
ONE-SHOT MUL TIVIBRATOR WITH INPUT LOCK OUT LARGE FAN-IN AND GATE
V+ V+
--IE ..
1",
V 40",S~-+
to I,
240k
c
62. D
'0'
V,
v;=r I" 13
3.0 k
51. 10 M
INPUT GATING
SIGNAL
V~:rl..
10 14
3.0k
51 k 10 M
y+ ----------,.-;a-
t V,
V"
I
51.
1.0 M
*FOR LARGE RATIOS OF R1/R2.
D1 CAN BE OMITTED
6-18
FAIRCHILD. MA139/239/339. MA139A/239A1339A. MA2901. MA3302
·yINo----i
1.0 M
v+O-"M.......-t vo
1.0M
1.0M
STROBE
INPUT
·v,
lOOk
TWO-DECADE HIGH-FREQUENCY VCO
v+
3.0k
•
FREQUENCY ..I1.I"
CONTROL
VOLTAGE 0.1 IJF OUTPUT 1
INPUT
20 k OUTPUT 2
~-----------------+-o
50 k
y+ +30 V
+250mV' Yc +50V
700 Hz' f o ' 100 kHz
200 k 2.0 k
10 k 100 k
6-19
FAIRCHILD- MA139/239/339- MA139A/239A/339A- MA2901- MA3302
15k
10k 3.0k
>_......ov"
MAGNETICii
PICKUP
1.0k
v,
1.".0.5 ",F
1.0k Av 100
Av 100
10k
LOW FREQUENCY OP AMP WITH OFFSET ADJUST ZERO CROSSING DETECTOR (SINGLE POWER SUPPLY)
Y+ Y+
v"
+---_IW---__+_-ov,
10k
R.
1.0k
v+
50 pF
v-
6-20