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Coa Bcs352 Lab-10

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185 views3 pages

Coa Bcs352 Lab-10

Uploaded by

paramjeetsingh16346
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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[Approved by AICTE, Govt. of India & Affiliated to Dr.

APJ
GL BAJAJ
Institute of Technology & Management
Abdul Kalam Technical University, Lucknow, U.P., India]
Department of Computer Sc. & Engineering (AI)
Greater Noida

Experiment No.:10

Object: - Design the data path of a computer from its register transfer language description.

Software Used: Logisim

Theory:

The data path of a computer is a network of data-processing elements, including registers, ALUs
(Arithmetic Logic Units), multiplexers, and buses. The data path enables data movement and computation
within the CPU based on an RTL description. RTL represents the micro-operations (operations on bits at
the register level) necessary for the execution of instructions.
The RTL description provides an abstract view of the operations that a computer can perform, specifying:
 Operations on data (addition, shifting, etc.)
 Transfers of data between registers or memory

A digital system composed of many registers, and paths must be provided to transfer information from
one register to another. The number of wires connecting all the registers will be excessive if separate
lines are used between each register and all other registers in the system. A bus structure, on the other
hand, is more efficient for transferring information between registers in a multi-register configuration
system. A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected by the bus
during a particular register transfer.

Sample RTL Operations:

1. Load Operation: R1 ← M[Address]


 Fetch data from memory and store it in register R1.
2. Addition: R2 ← R1 + R3
 Pass R1 and R3 to the ALU for addition, store the result in R2.
3. Conditional Operation: if (R1 == 0) then R2 ← R2 + 1
 Check if R1 is zero; if true, increment R2 by one.

Algorithm:

The following block diagram shows a Bus system for four registers. It is constructed with the help
of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1
and S2).
We have used labels to make it more convenient for you to understand the input-output
configuration of a Bus system for four registers. For instance, output 1 of register A is connected
to input 0 of MUX1.

Bus System for 4 Registers:


[Approved by AICTE, Govt. of India & Affiliated to Dr. APJ
GL BAJAJ
Institute of Technology & Management
Abdul Kalam Technical University, Lucknow, U.P., India]
Department of Computer Sc. & Engineering (AI)
Greater Noida

The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line common
bus.
When both select lines are at low logic, i.e., S1S0 = 00, the 0 data inputs of all four multiplexers
are selected and applied to the outputs that form the bus. This, in turn, causes the bus lines to
receive the content of register A since the outputs of this register are connected to the 0 data inputs
of the multiplexers.

OUTPUT:

S1 S0 Register Selected
0 0 A
0 1 B
1 0 C
1 1 D
[Approved by AICTE, Govt. of India & Affiliated to Dr. APJ
GL BAJAJ
Institute of Technology & Management
Abdul Kalam Technical University, Lucknow, U.P., India]
Department of Computer Sc. & Engineering (AI)
Greater Noida

RESULT: Data path of a computer from its register transfer language description is
designed/implemented, and its outputs are verified.

VIVA QUESTIONS

1. Explain the concept of register transfer.


2. How do registers perform the computation task?
3. Explain the role of each component (registers, ALU, multiplexers) in the data path.
4. Describe an example RTL instruction and explain how it executes in your designed data path.

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