‭MODULE : 05‬

‭3. Explain the basic steps for fetching a word from memory‬

‭●‬ T ‭ o fetch instruction/data from memory, the processor transfers the required‬
‭address to MAR. At the same time, the processor issues Read signal on‬
‭control-lines of memory-bus.‬
‭●‬ ‭When requested-data are received from memory, they are stored in MDR.‬
‭From MDR, they are transferred to other registers.‬
‭●‬ ‭The response time of each memory access varies (based on cache miss,‬
‭memory-mapped I/O). To accommodate this, MFC is used. (MFC->Memory‬
‭Function Completed).‬
‭●‬ ‭MFC is a signal sent from an addressed-device to the processor. MFC‬
‭informs the processor that the requested operation has been completed by‬
‭addressed-device.‬
‭●‬ ‭Consider the instruction Move (R1),R2. The sequence of steps is (Figure 7.5):‬
‭1.‬ ‭R1out, MARin, Read ;desired address is loaded into MAR & Read‬
‭command is issued‬
‭2.‬ ‭MDRin, WMFC ;load MDR from memory-bus & Wait for MFC response‬
‭from memory.‬
‭3.‬ ‭MDRout, R2in ;load R2 from MDR. (where WMFC=control-signal that‬
‭causes processor's control. circuitry to wait for the MFC signal.)‬
‭15. With a neat Timing Diagram, explain memory read operation‬

‭●‬ T ‭ o fetch instruction/data from memory, the processor transfers the required‬
‭address to MAR. At the same time, the processor issues Read signal on‬
‭control-lines of memory-bus.‬
‭●‬ ‭When requested-data are received from memory, they are stored in MDR.‬
‭From MDR, they are transferred to other registers.‬
‭●‬ ‭The response time of each memory access varies (based on cache miss,‬
‭memory-mapped I/O). To accommodate this, MFC is used. (MFC->Memory‬
‭Function Completed).‬
‭●‬ ‭MFC is a signal sent from an addressed-device to the processor. MFC‬
‭informs the processor that the requested operation has been completed by‬
‭addressed-device.‬
‭●‬ ‭Consider the instruction Move (R1),R2. The sequence of steps is (Figure 7.5):‬
‭4.‬ ‭R1out, MARin, Read ;desired address is loaded into MAR & Read‬
‭command is issued‬
‭5.‬ ‭MDRin, WMFC ;load MDR from memory-bus & Wait for MFC response‬
‭from memory.‬
‭6.‬ ‭MDRout, R2in ;load R2 from MDR. (where WMFC=control-signal that‬
‭causes processor's control. circuitry to wait for the MFC signal.)‬

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1‭ 1. Make use of a simple processor model and illustrate the implementation of‬
‭basic operations for execution of an instruction‬

‭●‬ P ‭ rocessor has separate processing-units to deal with integer data and‬
‭floating-point data.‬
‭1.‬ ‭Integer Unit -> To process integer data. (Figure 7.14).‬
‭2.‬ ‭Floating Unit -> To process floating –point data.‬
‭●‬ ‭Data-Cache is inserted between these processing-units & main-memory.‬
‭The integer and floating unit gets data from data cache‬
‭●‬ ‭Instruction-Unit fetches instructions‬
‭1.‬ ‭from an instruction-cache or‬
‭2.‬ ‭from main-memory when desired instructions are not already in‬
‭cache.‬
‭●‬ ‭Processor is connected to system-bus & hence to the rest of the computer‬
‭by means of a Bus Interface.‬
‭●‬ ‭Using separate caches for instructions & data is common practice in many‬
‭processors today.‬
‭●‬ ‭A processor may include several units of each type to increase the potential‬
‭for concurrent operations‬
‭●‬ ‭The 80486 processor has an 8-kbytes single cache for both instruction and‬
‭data. Whereas the Pentium processor has two separate 8 kbytes caches for‬
‭instruction and data.‬
‭●‬ ‭To execute instructions, the processor must have some means of generating‬
‭the control-signals. There are two approaches for this purpose: 1) Hardwired‬
‭control and 2) Microprogrammed control.‬
1‭ 2. Illustrate the organization of ALU and all the interconnected registers via a‬
‭single common bus in a processing unit‬

‭●‬ A ‭ LU and all the registers are interconnected via a Single Common Bus‬
‭(Figure 7.1).‬
‭●‬ ‭Data & address lines of the external memory-bus are connected to the‬
‭internal processor-bus via MDR & MAR respectively. (MDR Memory Data‬
‭Register, MAR Memory Address Register).‬
‭●‬ ‭MDR has 2 inputs and 2 outputs. Data may be loaded‬
‭→ into MDR either from memory-bus (external) or‬
‭→ from processor-bus (internal).‬
‭●‬ ‭MAR‟s input is connected to internal-bus; MAR‟s output is connected to‬
‭external- bus.‬
‭●‬ ‭Instruction Decoder & Control Unit is responsible for → issuing the‬
‭control-signals to all the units inside the processor. → implementing the‬
‭actions specified by the instruction (loaded in the IR).‬
‭●‬ ‭Register R0 through R(n-1) are the Processor Registers. The programmer‬
‭can access these registers for general-purpose use.‬
‭●‬ ‭Only the processor can access 3 registers Y, Z & Temp for temporary storage‬
‭during program-execution. The programmer cannot access these 3‬
‭registers.‬
‭●‬ ‭In ALU,‬
‭1) „A‟ input gets the operand from the output of the multiplexer‬
‭(MUX).‬
‭2) „B‟ input gets the operand directly from the processor-bus.‬
‭●‬ ‭There are 2 options provided for „A‟ input of the ALU.‬
‭●‬ ‭MUX is used to select one of the 2 inputs.‬
‭●‬ ‭MUX selects either → output of Y or → constant-value 4( which is used to‬
‭increment PC content).‬
‭●‬ ‭An instruction is executed by performing one or more of the following‬
‭operations:‬
‭1) Transfer a word of data from one register to another or to the ALU.‬
‭2) Perform arithmetic or a logic operation and store the result in a‬
‭register.‬
‭3) Fetch the contents of a given memory-location and load them into‬
‭a register.‬
‭4) Store a word of data from a register into a given memory-location.‬
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‭ . Illustrate the actions required to execute the instruction: Add(R3),R1 and‬

5
‭explain the steps in detail‬

‭Instruction execution proceeds as follows:‬

‭●‬ ‭Step1--> The instruction-fetch operation is initiated by‬
‭→ loading contents of PC into MAR &‬
‭→ sending a Read request to memory. The Select signal is set‬
‭to Select4, which causes the Mux to select constant 4. This‬
‭value is added to operand at input B (PC‟s content), and the‬
‭result is stored in Z.‬
‭●‬ ‭Step2--> Updated value in Z is moved to PC. This completes the PC‬
‭increment operation and the PC will now point to the next‬
‭instruction.‬
‭●‬ ‭Step3--> Fetched instruction is moved into MDR and then to IR. The‬
‭step 1 through 3 constitutes the Fetch Phase. At the beginning of‬
‭step 4, the instruction decoder interprets the contents of the IR.‬
‭This enables the control circuitry to activate the control-signals for‬
‭steps 4 through 7. The step 4 through 7 constitutes the Execution‬
‭Phase.‬
‭●‬ ‭Step4--> Contents of R3 are loaded into MAR & a memory read‬
‭signal is issued.‬
‭●‬ ‭Step5--> Contents of R1 are transferred to Y to prepare for addition.‬
‭●‬ ‭Step6--> When Read operation is completed, memory-operand is‬
‭available in MDR, and the addition is performed.‬
 ‭●‬ S
‭ tep7--> Sum is stored in Z, then transferred to R1.The End signal‬
‭causes a new instruction fetch cycle to begin by returning to step1.‬

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