DATA HANDLING CIRCUITS

Combinational circuit is a circuit in which we combine the different gates in the circuit, for
example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of
combinational circuits are following −
 The output of combinational circuit at any instant of time, depends only on the levels
present at input terminals.
 The combinational circuit do not use any memory. The previous state of input does
not have any effect on the present state of the circuit.
 A combinational circuit can have an n number of inputs and m number of outputs.
Block diagram

Multiplexers
Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and
m select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs and
routes it to the output. The selection of one of the n inputs is done by the selected inputs.
Depending on the digital code applied at the selected inputs, one out of n data sources is
selected and transmitted to the single output Y. E is called the strobe or enable input which is
useful for the cascading. It is generally an active low terminal that means it will perform the
required operation when it is low.
Block diagram

Multiplexers come in multiple variations

 2 : 1 multiplexer
 4 : 1 multiplexer
 16 : 1 multiplexer
 32 : 1 multiplexer
Block Diagram Truth Table

2-input Multiplexer Design

The input A of this simple 2-1line multiplexer circuit constructed from standard NAND gates
acts to control which input (I0 or I1) gets passed to the output at Q.
When the data select input, A is LOW at logic 0, input I1 passes its data through the NAND
gate multiplexer circuit to the output, while input I0 is blocked. When the data select A is
HIGH at logic 1, the reverse happens and now input I0 passes data to the output Q while input
I1 is blocked.
By the application of either a logic “0” or a logic “1” at A we can select the appropriate input,
I0 or I1 with the circuit acting a bit like a single pole double throw (SPDT) switch.
Because of one control line, (A) then we can only switch 21 inputs and in this simple
example, the 2-input multiplexer connects one of two 1-bit sources to a common output,
producing a 2-to-1-line multiplexer. Boolean expression.
Q = A.I0.I1 + A.I0.I1 + A.I0.I1 + A.I0.I1 and for our 2-input multiplexer circuit above, this can
be simplified too: Q = A.I1 + A.I0
We can increase the number of data inputs to be selected further simply by following the
same procedure and larger multiplexer circuits can be implemented using smaller 2-to-1
multiplexers as their basic building blocks.
4-to-1 Multiplexer:
The 4-to-1 multiplexer has 4 input bit, 2 control bits, and 1 output bit. The four input bits are
D0, D1,D2 and D3. only one of this is transmitted to the output y. The output depends on the
value of AB which is the control input. The control input determines which of the input data
bit is transmitted to the output.
For instance, when AB = 00, the upper AND gate is enabled while all other AND gates are
disabled. Therefore, data bit D0 is transmitted to the output, giving Y = Do. It follows suit for
the others.
a 4-input multiplexer we would therefore require two data select lines as 4-inputs represents
22 data control lines give a circuit with four inputs, I0, I1, I2, I3 and two data select lines A and
B as shown.
Applications of Multiplexer:
Multiplexer are used in various fields where multiple data need to be transmitted using a
single line. Following are some of the applications of multiplexers –
1. Communication system – Communication system is a set of system that enable
communication like transmission system, relay and tributary station, and communication
network. The efficiency of communication system can be increased considerably using
multiplexer. Multiplexer allow the process of transmitting different type of data such as
audio, video at the same time using a single transmission line.
2. Telephone network – In telephone network, multiple audio signals are integrated on a
single line for transmission with the help of multiplexers. In this way, multiple audio
signals can be isolated and eventually, the desire audio signals reach the intended
recipients.
3. Computer memory – Multiplexers are used to implement huge amount of memory into
the computer, at the same time reduces the number of copper lines required to connect the
memory to other parts of the computer circuit.
4. Transmission from the computer system of a satellite – Multiplexer can be used for
the transmission of data signals from the computer system of a satellite or spacecraft to
the ground system using the GPS (Global Positioning System) satellite
ASSIGNMENT
Design a 16- 1 multiplexer and 32- 1 multiplexer and implement using basic gates
Demultiplexer
The process of getting information from one input and transmitting the same over one of
many outputs is called demultiplexing. A demultiplexer is a combinational logic circuit that
receives the information on a single input and transmits the same information over one of 2n
possible output lines.
The bit combinations of the select lines control the selection of specific output line to be
connected to the input at given instant. The below figure illustrates the basic idea of
demultiplexer , in which the switching of the input to any one of the four outputs is possible
at a given instant.

Demultiplexers are also called as data distributors, since they transmit the same data which is
received at the input to different destinations.
Thus, a demultiplexer is a 1-to-N device whereas the multiplexer is an N-to-1 device. The
figure below shows the block diagram of a demultiplexer or simply a DEMUX.
There are several types of demultiplexers based on the output configurations such as 1-4, 1-8
and 1-16.
1-to-2 Demultiplexer
A 1-to-2 demultiplexer consists of one input line, two output lines and one select line. The
signal on the select line helps to switch the input to one of the two outputs. The figure below
shows the block diagram of a 1-to-2 demultiplexer with additional enable input.
In the figure, there are only two possible ways to connect the input to output lines, thus only
one select signal is enough to do the demultiplexing operation. When the select input is low,
then the input will be passed to Y0 and if the select input is high then the input will be passed
to Y1.

The truth table of a 1-to-2 demultiplexer is shown below in which the input is routed to Y0
and Y1 depends on the value of select input S. In the table output Y1 is active when the
combination of select line and input line are active high, i.e., S F = 11.
Therefore, the output Y1 = SF and similarly the output Y0 is equal to S ̅ F.

From the above truth table, the logic diagram of this demultiplexer can be designed by using
two AND gates and one NOT gate as shown in below figure. When the select lines S=0,
AND gate A1 is enabled while A2 is disabled.
Then, the data from the input flows to the output line Y1. Similarly, when S=1, AND gate A2
is enabled and AND gate A1 is disabled, thus data is passed to the Y0 output.

1-to-4 Demultiplexer
A 1-to-4 demultiplexer has a single input (D), two selection lines (S1 and S0) and four
outputs (Y0 to Y3). The input data goes to any one of the four outputs at a given time for a
particular combination of select lines.
This demultiplexer is also called as a 2-to-4 demultiplexer which means that two select lines
and 4 output lines. The block diagram of 1:4 DEMUX is shown below.
The truth table of this type of demultiplexer is given below. From the truth table it is clear
that, when S1=0 and S0= 0, the data input is connected to output Y0 and when S1= 0 and
s0=1, then the data input is connected to output Y1.
Similarly, other outputs are connected to the input for other two combinations of select lines.

From the table, the output logic can be expressed as min terms and are given below.

Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are select lines.
From the above Boolean expressions, a 1-to-4 demultiplexer can be implemented by using
four 3-input AND gates and two NOT gates as shown in figure below. The two selection
lines enable the particular gate at a time.
So depends on the combination of select inputs, input data is passed through the selected gate
to the associated output.

This type of demultiplexer is available in IC form and a typical IC 74139 is most commonly
used dual 1-to-4 demultiplexer. It has two independent demultiplexers and each DEMUX
accepts two binary inputs as select lines and four mutually exclusive active-low outputs.
1-to-8 Demultiplexer
The below figure shows the block diagram of a 1-to-8 demultiplexer that consists of single
input D, three select inputs S2, S1 and S0 and eight outputs from Y0 to Y7.
It is also called as 3-to-8 demultiplexer due to three select input lines. It distributes one input
line to one of 8 output lines depending on the combination of select inputs.
The truth table for this type of demultiplexer is shown below. The input D is connected with
one of the eight outputs from Y0 to Y7 based on the select lines S2, S1 and S0.
For example, if S2S1S0=000, then the input D is connected to the output Y0 and so on.

From this truth table, the Boolean expressions for all the outputs can be written as follows.
Y0 = D S2’ S1’ SO’
Y1 = D S2’ S1’ SO
Y2 = D S2’ S1 SO’
Y3 = D S2’ S1 SO
Y4 =D S2 S1’ SO’
Y5 =D S2 S1’ SO
Y6 =D S2 S1 SO’
Y7 =D S2 S1 SO

Applications of Demultiplexer:
1. Demultiplexer is used to connect a single source to multiple destinations. The main
application area of demultiplexer is communication system where multiplexer are used.
Most of the communication system are bidirectional i.e. they function in both ways
(transmitting and receiving signals). Hence, for most of the applications, the multiplexer
and demultiplexer work in sync. Demultiplexer are also used for reconstruction of
parallel data and ALU circuits.
2. Communication System – Communication system use multiplexer to carry multiple data
like audio, video and other form of data using a single line for transmission. This process
make the transmission easier. The demultiplexer receive the output signals of the
multiplexer and converts them back to the original form of the data at the receiving end.
 The multiplexer and demultiplexer work together to carry out the process of transmission
and reception of data in communication system.
3. ALU (Arithmetic Logic Unit) – In an ALU circuit, the output of ALU can be stored in
multiple registers or storage units with the help of demultiplexer. The output of ALU is
fed as the data input to the demultiplexer. Each output of demultiplexer is connected to
multiple register which can be stored in the registers.
4. Serial to parallel converter – A serial to parallel converter is used for reconstructing
parallel data from incoming serial data stream. In this technique, serial data from the
incoming serial data stream is given as data input to the demultiplexer at the regular
intervals. A counter is attach to the control input of the demultiplexer. This counter
directs the data signal to the output of the demultiplexer where these data signals are
stored. When all data signals have been stored, the output of the demultiplexer can be
retrieved and read out in parallel.
Decoder
A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs.
Decoder is identical to a demultiplexer without any data input. It performs operations which
are exactly
Generally, decoders are provided with enable inputs so as to activate the decoded output

based
Depending on the number of input lines, the inputs of a binary code can be 2-bit or 3-bit or 4-
bit codes. Upon the availability of 2n lines, it activates the one of its output by deactivating
(making logic 0) all other input whenever it receives n inputs.
Usually the number of bits in output code is more than the bits in its input code. The most
commonly used practical binary decoders are 2-to-4 decoder, 3-to-8 decoder and 4-to-16 line
binary decoder.
Block diagram

Examples of Decoders are following.

 Code converters
 BCD to seven segment decoders
 Nixie tube decoders
 Relay actuator

2 to 4 Line Decoder
The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs
where D through D are the four outputs. Truth table explains the operations of a decoder. It
shows that each output is 1 for only a specific combination of inputs.
Block diagram Truth Table
Logic Circuit

or
The figure above shows the truth table for a 2-to-4 decoder. For a given input, the outputs Y0
through Y3 are active high if enable input EN is active high (EN = 1). When both inputs A
and B are low (or A= B= 0), the output Y0 will be active or High and all other outputs will be
low.
When A = 0 and B = 1, the output Y1 will be active and when A = 1 and B = 0, then the
output Y2 will be active. When both the inputs are high, then the output Y3 will be high. If
the enable bit is zero then all the outputs will be set to zero. This relationship between the
inputs and outputs are illustrated in below truth table clearly.

From the above truth table we can obtain Boolean expression for the each output as

These expressions can be implemented by using basic logic gates. Thus, the
logic circuit design of the 2-to-4 line decoder is given above which is implemented by using
NOT and AND gates.
A common enable line is connected to each AND gate such that when EN= 0 all the outputs
are zero and if EN=1, depends on the inputs A and B, outputs are produced. Each output
represents one of the minterms of the 2 input variables. It is also possible to design 2-to-4
decoder using NAND gates
3-to-8 Decoder
In a 3-to-8 decoder, three inputs are decoded into eight outputs. It has three inputs as A, B,
and C and eight output from Y0 through Y7. Based on the combinations of the three inputs,
only one of the eight outputs is selected.
The figure above shows the truth table of a 3-to-8 decoder. Enable input is provided to
activate the decoded output depends on the input combinations A, B and C. Suppose if A =
B=1 and C= 0, then the output Y6 is 1 and all other outputs are zero. So from the truth table,
minterms represents the each output equation and are given as

Using the above min term expressions for each output, the circuit of 3-to-8 decoder is can be
implemented by using three NOT gates and eight AND gates. Each NOT gate provides the
complement of the input and AND gates generates one of the minterms.

It is also possible represent the each output equation using max terms. In such case, inversion
operation is performed in the logic circuit than that of circuit with min terms. The figure
below shows the truth table of 3-to-8 line decoder using NAND gates. Each output in the
table gives a max term representation.
At a given time only one output is low and all other outputs will be high. For example, when
A=B= 1 and C=0, then the output Y6 is zero and all other outputs are high as shown in below
figure.
From the above table , a 3-to-8 line decoder is designed by using three NAND gates and three
NOT gates. NOT gates generate the complement of input while the NAND gates generate
max terms of each output as shown in figure.
Encoder
Encoder is a combinational circuit which is designed to perform the inverse operation of the
decoder. An encoder has n number of input lines and m number of output lines. An encoder
produces an m bit binary code corresponding to the digital input number. The encoder
accepts an n input digital word and converts it into an m bit another digital word.
Block diagram

Examples of Encoders are following.

 Priority encoders
 Decimal to BCD encoder
 Octal to binary encoder
 Hexadecimal to binary encoder
Binary Encoder
A binary encoder has 2n input lines and n output lines, hence it encodes the information from
2n inputs into an n-bit code. From all the input lines, only one of an input line is activated at a
time, and depending on the input line, it produces the n bit output code.
The figure below shows the block diagram of binary encoder which consists of 2n input lines
and n output lines. It translates decimal number to binary number.
The output lines of an encoder correspond to either true binary equivalent or in BCD coded
form of the binary for the input value. Some of these binary encoders include decimal to
binary encoders, decimal to octal, octal to binary encoders, decimal to BCD encoders, etc.
Depending on the number of input lines, digital or binary encoders produce the output codes
in the form of 2 or 3 or 4 bit codes.

4 – to – 2 Bit Binary Encoder

The block diagram and truth table of a 4 input encoder is shown in below figure. The
truth table consists of four rows , since , it is assumed that only one input is the value of 1
 then the corresponding binary code associated with that enabled input is displayed at the
outputs.
 It is to be observed from the table is the output Yo is 1 when either input w1 or w3 is
1, also the output Y1 is set to 1 when either input w2 or w3 is 1.

The output from 4-to-2 encoder is generated by the logic circuit implemented by a set of
OR gates as shown in below. In the figure a, the output of the encoder is same if the input
activated is the Io input (Io = 1) or if no input is activated i.e., all the inputs are zero.
This causes ambiguity in the encoding output. To avoid this ambiguity, a valid encode
output can be added as an additional output, so this output assumes a value 1 when Io is
equal to 1.

Decimal to BCD Encoder

This type of encoder usually consists of ten input lines and 4 output lines. Each input line
corresponds to the each decimal digit and 4 outputs correspond to the BCD code.
This encoder accepts the decoded decimal data as an input and encodes it to the BCD output
which is available on the output lines.
The figure below shows the basic logic symbol of decimal to BCD encoder along with its
truth table. The truth table represents the BCD code for each decimal digit.
From this we can formulate the relationship between the BCD bit and decimal digit. It is
important to note that there is no explicit input line for decimal zero. When this condition
occurs, i.e., decimal inputs 1 to 9 all are zero, then the BCD output is 0000.

From the above table, we get the expressions as

Y3 = D8 + D9
Y2 = D4 + D5 + D6 + D7
Y1 = D2 + D3 + D6 + D7
Y0 = D1 + D3 + D5 + D7 + D9
From the above expressions, the decimal to BCD encoder logic circuit can be
implemented by using set of OR gates as shown in below figure.
 Octal to Binary Encoder
An octal to binary encoder consists of eight input lines and three output lines. Each input line
corresponds to each octal digit and three outputs generate corresponding binary code.
In encoders, it is to be assumed that only one input is active or has a value 1 at any given time
otherwise the circuit has no meaning. The figure below shows the logic symbol of octal to
binary encoder along with its truth table.


From the above table, the output Y2 becomes 1 if any of the digits D4 or D5 or D6 or D7 is
one. Thus, we can write its expression as
Y2 = D4 + D5 + D6 + D7
Similarly, Y1 = D2 + D3 + D6 + D7 and
Y0 = D1 + D3 + D5 + D7
Also it is to be observed that D0 does not exist in any of the expressions so it is considered as
don’t care. From the above expressions, we can implement the octal to binary encoder using
set of OR gates as shown in figure below.


There is ambiguity in the octal to binary encoder that when all the inputs are zero, an
output with all 0’s is generated. Also, when Do is 1, the output generated is zero. This is a
major problem in this type of encoder. This can be resolved by specifying the condition
that none of the inputs are active with an additional output.
Digital Encoder Applications: , These are used to translate the decimal values to the
binary in order to perform the binary functions such as addition, subtraction, multiplication,
In case of pocket calculators etc.
They are also used to generate the digital signals in response to the movement which are
classified into shaft encoders and linear encoders.
Keyboard Encoder: This type of encoder function is to generate the binary code
corresponds to the alphanumeric character key depressed on a keyboard.
Priority Encoder
This is a special type of encoder. Priority is given to the input lines. If two or more input line
are 1 at the same time, then the input line with highest priority will be considered. There are
four input D0, D1, D2, D3 and two output Y0, Y1. Out of the four input D3 has the highest
priority and D0 has the lowest priority. That means if D3 = 1 then Y1 Y1 = 11 irrespective of
the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1 Y0 = 10 irrespective of the other
inputs.
Block diagram Truth Table

Sequential Circuits
The combinational circuit does not use any memory. Hence the previous
state of input does not have any effect on the present state of the circuit.
But sequential circuit has memory so output can vary based on input. This
type of circuits uses previous input, output, clock and a memory element.

Block diagram

Flip Flop
Flip flop is a sequential circuit which generally samples its inputs and changes its outputs
only at particular instants of time and not continuously. Flip flop is said to be edge sensitive
or edge triggered while latches are level triggered.
S-R Flip Flop
Block Diagram
SR Flip-Flop
This simple flip-flop is basically a one-bit memory bistable device that has two inputs, one
which will “SET” the device (meaning the output = “1”), and is labelled S and another which
will “RESET” the device (meaning the output = “0”), labelled R. The SR description stands
for “Set-Reset”. The reset input resets the flip-flop back to its original state with an output Q
that will be either at a logic level “1” or logic “0” depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its
opposing inputs and is commonly used in memory circuits to store a single data bit. The SR
flip-flop has three inputs, Set, Reset and its current output Q relating to it’s current state or
history. The term “Flip-flop” relates to the actual operation of the device, as it can be
“flipped” into one logic Set state or “flopped” back into the opposing logic Reset state.

The Basic SR Flip-flop Circuit Diagram and Truth Table

CLOCKED S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input.
It is also called as level triggered SR-FF. For this, circuit in output will take
place if and only if the enable input (E) is made active. In short this circuit
will operate as an S-R latch if E = 1 but there is no change in the output if
E = 0.

Block Diagram Circuit Diagram

Truth Table
Operation
S. Conditi Operation
N. on

1 S=R= If S = R = 0 then output of NAND gates 3

0 : No and 4 are forced to become 1.
change Hence R' and S' both will be equal to 1.
Since S' and R' are the input of the basic S-
R latch using NAND gates, there will be no
change in the state of outputs.

2 S = 0, R Since S = 0, output of NAND-3 i.e. R' = 1

= 1, E = and E = 1 the output of NAND-4 i.e. S' = 0.
1 Hence Qn+1 = 0 and Qn+1 bar = 1. This is
reset condition.

3 S = 1, R Output of NAND-3 i.e. R' = 0 and output of

= 0, E = NAND-4 i.e. S' = 1.
1 Hence output of S-R NAND latch is Q n+1 = 1
and Qn+1 bar = 0. This is the reset condition.

4 S = 1, R As S = 1, R = 1 and E = 1, the output of

= 1, E = NAND gates 3 and 4 both are 0 i.e. S' = R'
1 = 0.
Hence the Race condition will occur in the
basic NAND latch.

The JK Flip Flop

The basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic
circuits but it suffers from two basic switching problems.
Number one, the S = 1 and R = 1condition (S = R = 1) must always be avoided, and number
two, if S or R change state while the enable input is high the correct latching action may not
occur. Then to overcome these two fundamental design problems with the SR flip-flop
design, the JK flip Flop was developed.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
that prevents the illegal or invalid output condition that can occur when both inputs S and R
are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four
possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for
a JK flip flop is similar to that of an SR Bistable Latch as seen above
The Basic JK Flip-flop
Both the S and the R inputs of the previous SR bistable have now been replaced by two
inputs called the J and K inputs, respectively .Then this equates to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input
NAND gates with the third input of each gate connected to the outputs at Q and Q. This cross
coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R = “1”
state to be used to produce a “toggle action” as the two inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the lower
NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status of Q through
the upper NAND gate. As Q and Q are always different we can use them to control the input.
When both inputs J and K are equal to logic “1”, the JK flip flop toggles as shown in the
following truth table.
The Truth Table for the JK Function
Input Output
Description
J K Q Q
0 0 0 0 Memory
same as 0 0 0 1 no change
for the
SR Latch 0 1 1 0
Reset Q » 0
0 1 0 1
1 0 0 1
Set Q » 1
1 0 1 0
toggle 1 1 0 1
Toggle
action 1 1 1 0

Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its
two input terminals, either SET or RESET to be active at any one time thereby eliminating
the invalid condition seen previously in the SR flip flop circuit. Also when both the J and the
K inputs are at logic level “1” at the same time, and the clock input is pulsed either “HIGH”,
the circuit will “toggle” from its SET state to a RESET state, or visa-versa. This results in the
JK flip flop acting more like a T-type toggle flip-flop when both terminals are “HIGH”.
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from
timing problems called “race” if the output Q changes state before the timing pulse of the
clock input has time to go “OFF”. To avoid this the timing pulse period ( T ) must be kept as
short as possible (high frequency). As this is sometimes not possible with modern TTL IC’s
the much improved Master-Slave JK Flip-flop was developed.
The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration. One flip-flop acts as the “Master” circuit, which
triggers on the leading edge of the clock pulse while the other acts as the “Slave” circuit,
which triggers on the falling edge of the clock pulse. This results in the two sections, the
master section and the slave section being enabled during opposite half-cycles of the clock
signal.
The TTL 74LS73 is a Dual JK flip-flop IC, which contains two individual JK type bistable’s
within a single chip enabling single or master-slave toggle flip-flops to be made.
Dual JK Flip-flop 74LS73

The Master-Slave JK Flip-flop

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a
series configuration with the slave having an inverted clock pulse. The outputs from Q and Q
from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the
“Master” flip flop being connected to the two inputs of the “Slave” flip flop. This feedback
configuration from the slave’s output to the master’s input gives the characteristic toggle of
the JK flip flop as shown below.

Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the
output of second to input of first. Master is a positive level triggered. But
due to the presence of the inverter in the clock line, the slave will respond
to the negative level. Hence when the clock = 1 (positive level) the
master is active and the slave is inactive. Whereas when clock = 0 (low
level) the slave is active and master is inactive.

Circuit Diagram Truth Table

Operation
S. Conditio Operation
N. n

1 J=K=0 When clock = 0, the slave becomes active and

(No master is inactive. But since the S and R inputs
change) have not changed, the slave outputs will also
remain unchanged. Therefore outputs will not
change if J = K =0.

2 J = 0 and Clock = 1 − Master active, slave inactive.

K=1 Therefore outputs of the master become Q 1 = 0
(Reset) and Q1 bar = 1. That means S = 0 and R =1.
Clock = 0 − Slave active, master inactive.
Therefore outputs of the slave become Q = 0 and
Q bar = 1.
Again clock = 1 − Master active, slave inactive.
Therefore even with the changed outputs Q = 0
and Q bar = 1 fed back to master, its output will
be Q1 = 0 and Q1 bar = 1. That means S = 0 and
R = 1.
Hence with clock = 0 and slave becoming active
the outputs of slave will remain Q = 0 and Q bar
= 1. Thus we get a stable output from the Master
slave.

3 J = 1 and Clock = 1 − Master active, slave inactive.

K=0 Therefore outputs of the master become Q 1 = 1
(Set) and Q1 bar = 0. That means S = 1 and R =0.
Clock = 0 − Slave active, master inactive.
Therefore outputs of the slave become Q = 1 and
Q bar = 0.
Again clock = 1 − then it can be shown that the
outputs of the slave are stabilized to Q = 1 and Q
bar = 0.

4 J=K=1 Clock = 1 − Master active, slave inactive. Outputs

(Toggle) of master will toggle. So S and R also will be
inverted.
Clock = 0 − Slave active, master inactive. Outputs
of slave will toggle.
These changed output are returned back to the
master inputs. But since clock = 0, the master is
still inactive. So it does not respond to these
changed outputs. This avoids the multiple
toggling which leads to the race around condition.
The master slave flip flop will avoid the race
around condition.
Delay Flip Flop / D Flip Flop
The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that
ensures that inputs S and R are never equal to one at the same time. The D-type flip flop are
constructed from a gated SR flip-flop with an inverter added between the S and the R inputs
to allow for a single D (data) input

D-type Flip-Flop Circuit

Block Diagram
D Q Q+ Operation

0 0 0 Reset

0 1 0 Reset

1 0 1 Set
Circuit Diagram
1 1 1 Set

D Flip Flop Characteristic Table

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND
inverter connected between S and R inputs. It has only one input. This
complement avoids the ambiguity inherent in the SR latch when both inputs are LOW, since
that state is no longer possible. The input data is appearing at the output after
some time. Due to this data delay between i/p and o/p, it is called delay
flip flop. S and R will be the complements of each other due to NAND
inverter. Hence S = R = 0 or S = R = 1, these input condition will never
appear. This problem is avoid by SR = 00 and SR = 1 conditions. .
Operation
S. Condition Operation
N.

1 E=0 Latch is disabled. Hence no change in

output.

2 E = 1 and D If E = 1 and D = 0 then S = 0 and R = 1.

=0 Hence irrespective of the present state,
the next state is Qn+1 = 0 and Qn+1 bar = 1.
This is the reset condition.

3 E = 1 and D If E = 1 and D = 1, then S = 1 and R = 0.

=1 This will set the latch and Q n+1 = 1 and
Qn+1 bar = 0 irrespective of the present
state.

Then this single data input, labelled D, is used in place of the “set” signal, and the inverter is
used to generate the complementary “reset” input thereby making a level-sensitive D-type
flip-flop from a level-sensitive RS-latch as now S = D and R = not D as shown above.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently
connected together. It has only input denoted by T as shown in the
Symbol Diagram. The symbol for positive edge triggered T flip flop is
shown in the Block Diagram.
Symbol Diagram Block Diagram Truth
Table

Operation
S. Condition Operation
N.

1 T = 0, J = K The output Q and Q bar won't change

=0

2 T = 1, J = K Output will toggle corresponding to every

=1 leading edge of clock signal.

DIGITAL REGISTERS
Flip-flop is a 1 bit memory cell which can be used for storing the digital
data. To increase the storage capacity in terms of number of bits, we have
to use a group of flip-flop. Such a group of flip-flop is known as
a Register. The n-bit register will consist of n number of flip-flop and it
is capable of storing an n-bit word.
The binary data in a register can be moved within the register from one
flip-flop to another. The registers that allow such data transfers are called
as shift registers. There are four mode of operations of a shift register.

 Serial Input Serial Output

 Serial Input Parallel Output
 Parallel Input Serial Output
 Parallel Input Parallel Output
Serial Input Serial Output
Let all the flip-flop be initially in the reset condition i.e. Q 3 = Q2 = Q1 = Q0 =
0. If an entry of a four bit binary number 1 1 1 1 is made into the register,
this number should be applied to Din bit with the LSB bit applied first. The
D input of FF-3 i.e. D3 is connected to serial data input Din. Output of FF-3
i.e. Q3 is connected to the input of the next flip-flop i.e. D 2 and so on.

Block Diagram

Operation
Before application of clock signal, let Q 3 Q2 Q1 Q0 = 0000 and apply LSB bit
of the number to be entered to D in. So Din = D3 = 1. Apply the clock. On the
first falling edge of clock, the FF-3 is set, and stored word in the register is
Q3 Q2 Q1 Q0 = 1000.
Apply the next bit to Din. So Din = 1. As soon as the next negative edge of
the clock hits, FF-2 will set and the stored word change to Q 3 Q2 Q1 Q0 =
1100.
Apply the next bit to be stored i.e. 1 to D in. Apply the clock pulse. As soon
as the third negative clock edge hits, FF-1 will be set and output will be
modified to Q3 Q2 Q1 Q0 = 1110.
Similarly with Din = 1 and with the fourth negative clock edge arriving, the
stored word in the register is Q3 Q2 Q1 Q0 = 1111.
Truth Table Waveforms

Serial Input Parallel Output

 In such types of operations, the data is entered serially and
taken out in parallel fashion.
 Data is loaded bit by bit. The outputs are disabled as long as
the data is loading.
 As soon as the data loading gets completed, all the flip-flops
contain their required data, the outputs are enabled so that all
the loaded data is made available over all the output lines at
the same time.
 4 clock cycles are required to load a four bit word. Hence the
speed of operation of SIPO mode is same as that of SISO
mode.
Block Diagram

Parallel Input Serial Output (PISO)

 Data bits are entered in parallel fashion.
 The circuit shown below is a four bit parallel input serial output
register.
  Output of previous Flip Flop is connected to the input of the
next one via a combinational circuit.
 The binary input word B 0, B1, B2, B3 is applied though the same
combinational circuit.
 There are two modes in which this circuit can work namely -
shift mode or load mode.
Load mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become
active they will pass B1, B2, B3 bits to the corresponding flip-flops. On the
low going edge of clock, the binary input B 0, B1, B2, B3 will get loaded into
the corresponding flip-flops. Thus parallel loading takes place.

Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become
inactive. Hence the parallel loading of the data becomes impossible. But
the AND gate 1,3 and 5 become active. Therefore the shifting of data from
left to right bit by bit on application of clock pulses. Thus the parallel in
serial out operation takes place.

Block Diagram

Parallel Input Parallel Output (PIPO)

In this mode, the 4 bit binary input B 0, B1, B2, B3 is applied to the data
inputs D0, D1, D2, D3 respectively of the four flip-flops. As soon as a
negative clock edge is applied, the input binary bits will be loaded into the
flip-flops simultaneously. The loaded bits will appear simultaneously to the
output side. Only clock pulse is essential to load all the bits.

Block Diagram
Bidirectional Shift Register
 If a binary number is shifted left by one position then it is
equivalent to multiplying the original number by 2. Similarly if
a binary number is shifted right by one position then it is
equivalent to dividing the original number by 2.
 Hence if we want to use the shift register to multiply and
divide the given binary number, then we should be able to
move the data in either left or right direction.
 Such a register is called bi-directional register. A four bit bi-
directional shift register is shown in fig.
 There are two serial inputs namely the serial right shift data
input DR, and the serial left shift data input DL along with a
mode select input (M).
Block Diagram

Operation
S. Condition Operation
N.

1 With M = 1 − Shift
If M = 1, then the AND gates 1, 3, 5 and
right operation
7 are enabled whereas the remaining
AND gates 2, 4, 6 and 8 will be disabled.
The data at DR is shifted to right bit by
bit from FF-3 to FF-0 on the application
of clock pulses. Thus with M = 1 we get
the serial right shift operation.

2 With M = 0 − Shift
When the mode control M is connected
left operation
to 0 then the AND gates 2, 4, 6 and 8
are enabled while 1, 3, 5 and 7 are
disabled.
The data at DL is shifted left bit by bit
from FF-0 to FF-3 on the application of
clock pulses. Thus with M = 0 we get the
serial right shift operation.
Universal Shift Register
A shift register which can shift the data in only one direction is called a
uni-directional shift register. A shift register which can shift the data in
both directions is called a bi-directional shift register. Applying the same
logic, a shift register which can shift the data in both directions as well as
load it parallely, is known as a universal shift register. The shift register is
capable of performing the following operation −

 Parallel loading
 Left Shifting
 Right shifting
The mode control input is connected to logic 1 for parallel loading
operation whereas it is connected to 0 for serial shifting. With mode
control pin connected to ground, the universal shift register acts as a bi-
directional register. For serial left operation, the input is applied to the
serial input which goes to AND gate-1 shown in figure. Whereas for the
shift right operation, the serial input is applied to D input.

Block Diagram

Digital Counters
Counter is a sequential circuit. A digital circuit which is used for a counting
pulses is known counter. Counter is the widest application of flip-flops. It is
a group of flip-flops with a clock signal applied. Counters are of two types.

 Asynchronous or ripple counters.

 Synchronous counters.
Asynchronous or ripple counters
The logic diagram of a 2-bit ripple up counter is shown in figure. The
toggle (T) flip-flop are being used. But we can use the JK flip-flop also with
J and K connected permanently to logic 1. External clock is applied to the
clock input of flip-flop A and Q A output is applied to the clock input of the
next flip-flop i.e. FF-B.
Logical Diagram

Operation
S. Condition Operation
N.

1 Initially let both the FFs QBQA = 00 initially

be in the reset state

2 After 1st negative clock

As soon as the first negative clock edge is
edge
applied, FF-A will toggle and QA will be
equal to 1.
QA is connected to clock input of FF-B.
Since QA has changed from 0 to 1, it is
treated as the positive clock edge by FF-B.
There is no change in QB because FF-B is a
negative edge triggered FF.
QBQA = 01 after the first clock pulse.

3 After 2nd negative clock

On the arrival of second negative clock
edge
edge, FF-A toggles again and QA = 0.
The change in QA acts as a negative clock
edge for FF-B. So it will also toggle, and
QB will be 1.
QBQA = 10 after the second clock pulse.

4 After 3rd negative clock

On the arrival of 3rd negative clock edge,
edge
FF-A toggles again and QA become 1 from
0.
Since this is a positive going change, FF-B
does not respond to it and remains
inactive. So QB does not change and
continues to be equal to 1.
QBQA = 11 after the third clock pulse.

5 After 4th negative clock

On the arrival of 4th negative clock edge,
edge
FF-A toggles again and QA becomes 1 from
 0.
This negative change in QA acts as clock
pulse for FF-B. Hence it toggles to change
QB from 1 to 0.
QBQA = 00 after the fourth clock pulse.

Truth Table

Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter
simultaneously, then such a counter is called as synchronous counter.

2-bit Synchronous up counter

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle
flip-flop. The JB and KB inputs are connected to QA.

Logical Diagram

Operation
S. Condition Operation
N.

1 Initially let both the FFs QBQA = 00 initially.

be in the reset state

2 After 1st negative clock As soon as the first negative clock

edge edge is applied, FF-A will toggle and
 QA will change from 0 to 1.
But at the instant of application of
negative clock edge, QA , JB = KB = 0.
Hence FF-B will not change its state.
So QB will remain 0.
QBQA = 01 after the first clock pulse.

3 After 2nd negative clock On the arrival of second negative

edge clock edge, FF-A toggles again and
QA changes from 1 to 0.
But at this instant QA was 1. So JB =
KB= 1 and FF-B will toggle. Hence
QB changes from 0 to 1.
QBQA = 10 after the second clock
pulse.

4 After 3rd negative clock On application of the third falling

edge clock edge, FF-A will toggle from 0
to 1 but there is no change of state
for FF-B.
QBQA = 11 after the third clock
pulse.

5 After 4th negative clock On application of the next clock

edge pulse, QA will change from 1 to 0 as
QB will also change from 1 to 0.
QBQA = 00 after the fourth clock
pulse.

Classification of counters
Depending on the way in which the counting progresses, the synchronous
or asynchronous counters are classified as follows −

 Up counters
 Down counters
 Up/Down counters
UP/DOWN Counter
Up counter and down counter is combined together to obtain an UP/DOWN
counter. A mode control (M) input is also provided to select either up or
down mode. A combinational circuit is required to be designed and used
between each pair of flip-flop in order to achieve the up/down operation.

 Type of up/down counters

  UP/DOWN ripple counters
 UP/DOWN synchronous counter
UP/DOWN Ripple Counters
In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So
either T flip-flops or JK flip-flops are to be used. The LSB flip-flop receives
clock directly. But the clock to every other FF is obtained from (Q = Q bar)
output of the previous FF.
 UP counting mode (M=0) − The Q output of the preceding
FF is connected to the clock of the next stage if up counting is
to be achieved. For this mode, the mode select input M is at
logic 0 (M=0).
 DOWN counting mode (M=1) − If M = 1, then the Q bar
output of the preceding FF is connected to the next FF. This
will operate the counter in the counting mode.
Example
3-bit binary up/down ripple counter.
 3-bit − hence three FFs are required.
 UP/DOWN − So a mode control input is essential.
 For a ripple up counter, the Q output of preceding FF is
connected to the clock input of the next one.
 For a ripple up counter, the Q output of preceding FF is
connected to the clock input of the next one.
 For a ripple down counter, the Q bar output of preceding FF is
connected to the clock input of the next one.
 Let the selection of Q and Q bar output of the preceding FF be
controlled by the mode control input M such that, If M = 0, UP
counting. So connect Q to CLK. If M = 1, DOWN counting. So
connect Q bar to CLK.
Block Diagram Truth Table

Operation
S. Condition Operation
N.
 1 Case 1 − With M =
If M = 0 and M bar = 1, then the AND gates
0 (Up counting
1 and 3 in fig. will be enabled whereas the
mode)
AND gates 2 and 4 will be disabled.
Hence QA gets connected to the clock input
of FF-B and QB gets connected to the clock
input of FF-C.
These connections are same as those for
the normal up counter. Thus with M = 0 the
circuit work as an up counter.

2 Case 2: With M =
If M = 1, then AND gates 2 and 4 in fig. are
1 (Down counting
enabled whereas the AND gates 1 and 3 are
mode)
disabled.
Hence QA bar gets connected to the clock
input of FF-B and QB bar gets connected to
the clock input of FF-C.
These connections will produce a down
counter. Thus with M = 1 the circuit works
as a down counter.

Modulus Counter (MOD-N Counter)

The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple
counter is called as MOD-8 counter. So in general, an n-bit ripple counter
is called as modulo-N counter. Where, MOD number = 2 n.

Type of modulus
 2-bit up or down (MOD-4)
 3-bit up or down (MOD-8)
 4-bit up or down (MOD-16)
Application of counters
 Frequency counters
 Digital clock
 Time measurement
 A to D converter
 Frequency divider circuits
 Digital triangular wave generator.