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7 views2 pages

Document COOS

Coosbtbrbrb

Uploaded by

Akhila Akula
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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CODE: 2205ES03 R22 SET - 1

MALLA REDDY ENGINEERING COLLEGE FOR WOMEN


(Autonomous Institution – UGC, Govt. of India)
(Affiliated to JNTU, Hyderabad, Approved by AICTE - - ISO 9001:2015 Certified)
Accredited by NBA & NAAC – ‘A’ Grade
NIRF India Ranking, Accepted by MHRD, Govt. of India
B.TECH II YEAR I SEMESTER REGULAR EXAMINATIONS, JAN/FEB-2024
COMPUTER ORGANIZATION AND OPERATING SYSTEMS
(ECE)

[Time: 3 Hours] [Max. Marks: 60]


PART – A
(10x 1 = 10M)
Note: 1. This Part consists of 10 QUESTIONS
2. Answer All Questions. Each question carries 1 Mark.

1 A State the use of address bus 1M BTL2


B Mention the purpose of instruction cycle 1M BTL2
C What does addressing mode mean? 1M BTL1
D Name the two types of RAM 1M BTL1
E Indicate whether a CPU ad monitor are connected parallel or serially 1M BTL2
F Present the function of USB in two points 1M BTL2
G Define demand paging 1M BTL2
H Give the meaning of deadlock 1M BTL2
I Represent the benefit of DMA 1M BTL2
J Write the micro operation to show addition of two registers and 1M BTL2
storing sum in any one the registers
PART – B
(5 x 10 = 50M)

Note: 1. This Part consists of 10 QUESTIONS


2. Answer any 1 question from each Section. Each question carries 10 Marks.
3. Illustrate your answers with NEAT sketches wherever necessary.

SECTION - I
2.A Feature the functional units of a basic computer 5M BTL 2
2.B Deliver a note on memory- reference instructions 5M BTL2
(OR)
3.A Emphasize on Logic and Shift micro operations 5M BTL 2
3.B Depict the instruction cycle flow diagram 5M BTL2

SECTION - II
4.A Highlight the memory operations in cache and virtual memories 5M BTL2
4.B Focus on the presentation of Control memory functions 5M BTL2
(OR)
5.A Illustrate the micro programmed control unit with a design 5M BTL2
5.B Explain the various memories and their specialties 5M BTL2
CODE: 2205ES03 R22 SET - 1
SECTION - III
6.A Analyze the priority interrupt procedures in I-O processing 5M BTL4
6.B Justify the types of data transfer modes in I-O processing 5M BTL4
(OR)
7.A Interpret the peripheral interface and their interconnection 5M BTL4
7.B Compare the Standard Serial communication protocols 5M BTL4

SECTION – IV
8.A Determine the various processes and their states 5M BTL2
8.B Detail the styles of various memory management schemes 5M BTL2
(OR)
9.A Conceptualize the Process Management and Scheduling 5M BTL2
9.B Elaborate the memory page replacement algorithms 5M BTL2

SECTION – V
10.A Using an example of data file sharing, justify the deadlock avoidance 5M BTL4
10.B Interpret the directory structure and issues in it 5M BTL4
(OR)
11.A Contrast the terms detection, prevention, avoidance processes in deadlock 5M BTL4
management
11.B Specify the analysis carried out in file system interface 5M BTL4

----***----

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