DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

LABORATORYLAB MANUAL

ANALOG & DIGITAL ELECTRONICS

LABORATORY
ESC 391

SEMESTER III

Baruipur, Mouza Beralia, Balarampur, Kolkata, West Bengal 700144

 Analog & Digital Electronics Lab, ESC391
GMIT, ECE DEPT
Analog & Digital Electronics Lab
Code: ESC-391
Contacts: 4P

COURSE OUTCOMES:

General Information

All assigned experiments must be performed in order to pass the class. Most of the work
for an experiment should be done during class time in the laboratory. In order to allow
for further analysis and graphing, the notebooks are due at the start of the laboratory the
following week. Submit your completed notebook to the instructors Evaluation of
laboratory performance is based on the instructor’s observations of you while you are
performing the experiments. Among the factors considered are your ability to construct
circuits, your competency in using test equipment, your preparation prior to starting the
experiment, answers given to any questions asked during the laboratory, as well as
attendance, tardiness, and attitude. Keep in mind that your behavior influences your
grade; act professionally at all times.
The following guidelines should be followed when using your notebook:

 The first page should contain a table of contents.

 All pages in the notebook must bound, numbered and dated.
 Use a pen or permanent marker, never pencil.
 Write legibly and coherently. Extreme neatness is not required but anyone should
be ableto read and understand what you have written.
 Never erase errors or remove pages. Simply draw a line through any mistakes.
 The notebook should be a complete record of your work, i.e. what you actually do in
the laboratory, and sufficiently detailed that a knowledgeable person could
reconstruct what you did.
 All measurements, notes, and calculations should be directly recorded in the
notebook.Never write information on scraps of paper for later transcription into
the notebook.
 Do not paste the laboratory manual into your notebook
 Any graphs or printouts relevant to the experiment should be pasted into your notebook.
 Be sure to label all diagrams, schematics, graphs, and waveform printouts.
 All numbers should include appropriate units.
 Include an equipment list.
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

ELECTRONICS & COMMUNICATION ENGINEERING LABORATORY REGULATIONS

General

Students working in the communication laboratories should be very cautious during the lab
work. Food and drinks are not permitted in the laboratories. Daily Group details and
experiment details must be updated in the laboratory maintenance register.

Equipment

All equipment must be returned to its proper storage location at the end of the lab period.
Instruments and equipment are delicate and expensive. Improper use of equipment can result
in instantaneous damage; check with you instructor or the equipment’s manual if you are in
doubt.
Damaged or faulty equipment should be given to the technicians/instructor along with a
description of the problem.

TRUN OFF your Trainer Kit after completion of

LAB Work.

Place properly your Chair after completion of LAB

Work.
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

INDEX

Sl no Experiment name Submission date Signature

Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Experiment No.:-1

Title: Design a Class A amplifier

Objectives:
1) Measure the quiescent operating point.

2) Measure the maximum input signal for undistorted output.

3) Determine the efficiency of the amplifier.

Apparatus required:
1) CRO, Function generator, Variable voltage power supply, Multimeter.

2) Bread board, connecting wire

3) a)Transistors-2N3904(1 pc.), b)Resistors-3.3KΩ(1 pc), 470Ω(1 pc), 2.2KΩ(1 pc), 330Ω(1 pc), 1KΩ(1 pc), 100Ω(1
pc), c) Capacitors-100μF(3 pcs),.

Brief theory:
In almost all electronic system, the power amplifier is the final stage. It converts dc power obtained
from the battery into useful ac power. The transistor used in a power amplifier has power dissipation more than 0.5W.
Under quiescent conditions, the dc collector current is ICQ. Then dc voltage available between the collector and emitter
of the transistor is VCEQ = VCC – ICQ(RC + RE). The dc power that goes into the transistor is PD = VCEQ* ICQ. This represent the
effective dc input power to the amplifier. The total dc power drain from the supply is VCC* ICQ. Out of this, only VCEQ* ICQ
is the effective dc input power to the amplifier because, at best, that is the power that could be converted into useful
ac power. The difference of power is VCC* ICQ - VCEQ* ICQ = ICQ(VCC - VCEQ) ICQ ICQ(RC + RE) = I2CQ(RC + RE). This much power
goes waste in unnecessarily heating resistors. The resistor RE has to there in the circuit, because it is a part of the
biasing network. If RE is absent, the stabilization of the operating point becomes poor. This may ultimately lead to the
thermal runway of the transistor.

2
Vout ( p  p)
Pdc  I CQ  VCC and Pout 
8  RC

Pac
Efficiency, η =
Pdc
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Circuit diagram:

Figure 1: Class A power amplifier.

Procedure:
(1) Look at the circuits of the class power A amplifier circuit. Trace the circuit. Note the type, number of the transistor
and the value of the resistor and capacitor.
(2) Make the circuit suitably on the bread board according to the connection diagram in figure 1.
(3) Connect the dc voltage source from the regulated power supply. Select a voltage 12V.
(4) Measure the values of RC, Re, VCQ and VE (Voltage across the emitter resistor, Re) using multimeter. Calculate the
quiescent point current, ICQ = VE/ Re.[N.B: VCQ, VE should be measured under zero signal condition]
(5) Set the function generator to get sin wave output with amplitude of 40mV-60mV and frequency of 1KHz. Connect
the function generator to the input of the circuit (at point A w.r.t. B). Connect one probe of the CRO (say Channel
No.-1) to the input point, A and the other probe to the output point, X. Adjust different knobs of the CRO so that the
good and stable wave shape is visible on its screen. Increase the amplitude of the sin wave input voltage till output
wave shape starts distortion. Measure the amplitude of the input signal. This gives the maximum signal handling
capacity of the circuit.
(6) From the CRO measure the peak to peak voltage, Vout(P-P) of the output waveform. Calculate the efficiency of the
amplifier.
(7) Replace the resistors RC and Re with the values of 1KΩ and 100Ω respectively. Repeat the procedure from 4 to 6.
Calculate the efficiency of second case and compared this value with the first case.
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Observations:
VCC = ____________Volts.

SL RC Re VCQ VE ICQ = Pdc = Vout ( p p) Vout2 ( p  p) Pac

Pac= %η = x 100
8  RC Pdc
No. VE/ Re VCC * ICQ

Discussion:
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Experiment No.:-3

Title: Design of a Schmitt Trigger using 555 timer

Objectives:
1) Measure the quiescent operating point.

2) Measure the maximum input signal for undistorted output.

3) Determine the efficiency of the amplifier.

Apparatus required:
1) CRO, Function generator, Variable voltage power supply, Multimeter.

2) Bread board, connecting wire

3) a) IC NE555, b)Resistors-100KΩ(2 pcs), c) Capacitors-0.01μF(2 pcs),.

Brief theory:
In Schmitt Trigger two internal comparators are tied together and externally biased at VCC/2 through
R1 & R2. Since the upper comparator will trip at (2/3) VCC and lower comparator at (2/3) VCC the bias provided by R1
& R2 is centered within these two thresholds. Thus a sine wave of sufficient amplitude (>VCC/6 = 2/3 VCC – VCC/2) to
exceed the reference levels causes the internal flip –flop to alternately set and reset providing a square wave output.

Circuit diagram:
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Procedure:
i. Connect the circuit as shown in fig (1).

ii. Switch ON the power supply to the trainer.

iii. Apply the input sine wave 5V (P-P) using function generator at 1KHZ frequency.

iv. Observe the output waveform at Pin No: 3.

v. Calculate the duty cycle using formula.

D = [ R2 / R1+R2]

= [100K / 100K + 100K]

= 50%

Observations:
VCC = ____________Volts.

Time period of Time period of Waveform of Waveform of Time constant

Input Signal Output Signal Input Signal Output Signal

Discussion:
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Experiment No.: 4

Title: Design a Full Adder using basic gates and verify its output / Design a Full Subtractor circuit using basic gates
and verify its output.

Instrument & Component Required

Sl. No. Instrument & Component Quantity

Theory:

Full adder:

A half-adder has only two inputs and there is no provision to add a carry from the lower bits when multi bit
addition is performed. For this purpose a full adder is designed. A full adder is combinational circuit that performs the
arithmetic sum of three input bits and produces a sum output and a carry.

Full Subtractor:

A full subtractor is a combinational circuit that performs subtraction involving three bits namely minued bit(X)
subtrahend bit (Y) and the borrow from the previous stage (Bin) and produce two outputs difference (D) and borrow out
(Bout).

Observation Table

Input Data Output Data

A B Cin Sum Cout

Circuit Diagram of Full Adder using Logic Gates

 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Observation Table

Input Data Output Data

X Y Bin D Bout

Circuit Diagram of Full Subtractor using Logic Gates

 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Experiment No.: 5

Title: Construction of simple Decoder & Multiplexer circuits using logic gates.

Instrument & Component Required

Sl. No. Instrument & Component Quantity

Theory:

Multiplexer:

A multiplexer (or data selector) is a logic circuit that gates one out of several inputs to a single output. The
output selected is controlled by a set of select inputs. For a multiplexer with n input lines and one output line m select
m
lines are required, where 2 = n. Depending upon the digital code applied at the select inputs one out of n data sources is
selected and transmitted to a single output channel. A strobe (or enable) input G is incorporated which helps in cascading
and it is generally active low.

Application of multiplexer:- Data routing, Logic function generator, control sequencer, Parallel to serial
converter.

Decoder:
n
A Decoder is a logic circuit that converts an n-bit binary input code (data) into 2 output lines, such that each
output line will be activated for only one the possible combinations of inputs. A Decoder is similar to demultiplexer but
without any data input.
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Observation Table

Select Input Data Input Output Bit

S1 S0 D3 D2 D1 D0 Y

Circuit Diagram of 4:1 MUX

Observation Table

Input Data Output Parity Bit

S1 S0 D3 D2 D1 D0

Circuit Diagram of 2:4 Decoder

 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Experiment No.: 6

Title: Realization of RS / JK / D flip flop using logic gates

Instrument & Component Required

Sl. No. Instrument & Component Quantity

Theory:

S-R Flip-flop:

This Flip-flop has two inputs. Namely Set (S) and reset (R) and two outputs Q and Compliment of Q.

D Flip-flop:

This is called delay Flip-flop because a transfer of data from the input to the output is delayed. The D
Flip-flop is either use as a delay device or a latch to store 1 bit of binary information.

J-K Flip-flop:

A J-K Flip-flop has characteristics similar to S-R Flip-flop. In addition, the indeterminate condition of S-
R Flip-flop is permitted in it. Inputs J & K behave like Input S & R to set & reset the Flip-flop, respectively.

Truth Table of S-R Flip-flop

Qn S R Qn+1 Action

Circuit Diagram of NAND based S-R Flip-flop

 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Truth Table of D Flip-flop

Qn D Qn+1 Action

Circuit Diagram of NAND based D Flip-flop

Verification of J-K Flip-flop Using J-K Flip-flop IC 7476

Truth Table of J-K Flip-flop

Qn S R Qn+1 Action

Circuit Diagram of J-K Flip-flop

 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Experiment No.: 7

Title: Design of Shift Register using J-K / D Flip Flop

AIM: Familiarization with Shift Register

a. Realization of 4bit Serial in Serial out & Serial in Parallel out Right shift Register
b. Realization of 4bit Serial in Serial out & Serial in Parallel out Left shift Register
using D Flip-flop (IC 7474)

Instrument & Component Required

Sl. No. Instrument & Component Quantity

Theory:

Register:

A register is a sequential circuit consisting of a group of Flip-flops suitable for storing binary
information. Each Flip-flop is a binary cell capable of storing one bit of information. A register capable of
shifting binary information is Shift Register.

According to its input and output property there are four types of Shit Register, namely

1. SISO (Serial In Serial Out)

2. SIPO (Serial In Parallel Out)

3. PISO (Parallel In Serial Out)

4. PIPO (Parallel In Parallel Out)

According to sifting property there are two types of Shit Register, namely

1. Left Sift Register

2. Right Sift Register

 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Block Diagram of 4bit Serial in Serial out Serial in Parallel out Right shift Register using D Flip-flop

Observation Table of Serial in Serial out & Serial in Parallel out Right shift Register

State QD QC QB QA
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Block Diagram of 4bit Serial in Serial out Serial in Parallel out Left shift Register using D Flip-flop

Observation Table Serial in Serial out & Serial in Parallel out Left shift Register

State QD QC QB QA
 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Experiment No.: 9

Title: Design of MOD- N Counter

Realization of Synchronous Mod-3 Up & Down counter using D Flip-flop (IC 7474)

Instrument & Component Required

Sl. No. Instrument & Component Quantity

Theory:

In Synchronous counters, clock pulses are applied simultaneously to all the flip-flops which leads to the settling time of
the counter being equal to the propagation delay of a single flip-flop. Hence Synchronous counters are also called parallel
counters. In a parallel counter, all the flip-flops change their states simultaneously. It starts counting from 0 for Mod-3 UP Counter
& starts counting from 2 for Mod-3 DOWN Counter

Block Diagram of Mod-3 Down Counter using D Flip-flop

 Analog & Digital Electronics Lab, ESC391
ECE dept, GMIT

Observation Table of Mod-3 Down Counter

State QB QA

Block Diagram of Mod-3 Up Counter using D Flip-flop

Observation Table of Mod-3 Up Counter

State QB QA