Integrated Circuit 2

ECE 430

Lecture 4: MOS Inverter ( Dynamic characteristics)

Dr. Emad Badry

 Delay Definitions

The delay of the CMOS inverter is a performance metric for how fast the circuit is. This delay is dependent upon the
charging and discharging of the RC load capacitor by the PMOS or NMOS devices

The edge rate (𝑡𝑟𝑓 ) can be defined as:

𝑡𝑟 + 𝑡𝑓
𝑡𝑟𝑓 =
2

The output voltage at 10% and 90% can be calculated as:

𝑉10% = 𝑉𝑂𝐿 + 0.1(𝑉𝑂𝐻 − 𝑉𝑂𝐿 )

𝑉90% = 𝑉𝑂𝐿 + 0.9(𝑉𝑂𝐻 − 𝑉𝑂𝐿 ) 1

𝑓𝑚𝑎𝑥 =
Maximum frequency 𝑡𝑟 + 𝑡𝑓
Propagation delay (𝑡𝑑 ) can be defined as

𝑡𝑃𝐻𝐿 + 𝑡𝑃𝐿𝐻
𝑡𝑑 =
2
Cint is due to metal or polysilicon connections between the two inverters. It is assumed that a pulse waveform is
applied to the input of the first stage inverter. The capacitances seen at the output are lumped into CL.

𝐶𝐿 = 𝐶𝐺𝐷𝑛 + 𝐶𝐺𝐷𝑝 + 𝐶𝐷𝐵𝑛 + 𝐶𝐷𝐵𝑝 + 𝐶𝑖𝑛𝑡 + 𝐶𝐺

 Calculation of Delay Times

Average current method

The simplest approach for calculating the propagation delay times 𝑡𝑃𝐿𝐻 and 𝑡𝑃𝐻𝐿 is based on estimating the average
capacitance current during charge down and charge up. The constant average current Iavg is found as

𝐶𝐿 . 𝛥𝑉𝐻𝐿 𝐶𝐿 (𝑉𝑂𝐻 − 𝑉50% )

𝑡𝑃𝐻𝐿 = =
𝐼𝑎𝑣𝑔,𝐻𝐿 𝐼𝑎𝑣𝑔,𝐻𝐿

𝐶𝐿 . 𝛥𝑉𝐿𝐻 𝐶𝐿 (𝑉50% − 𝑉𝑂𝐿 )

𝑡𝑃𝐿𝐻 = =
𝐼𝑎𝑣𝑔,𝐿𝐻 𝐼𝑎𝑣𝑔,𝐿𝐻

1
𝐼𝑎𝑣𝑔,𝐻𝐿 = [𝐼𝐶 𝑉𝑖𝑛 = 𝑉𝑂𝐻 , 𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐻 + 𝐼𝐶 (𝑉𝑖𝑛 = 𝑉𝑂𝐻 , 𝑉𝑜𝑢𝑡 = 𝑉50% )]
2
1
𝐼𝑎𝑣𝑔,𝐿𝐻 = 𝐼 𝑉 = 𝑉𝑂𝐿 , 𝑉𝑜𝑢𝑡 = 𝑉50% + 𝐼𝐶 𝑉𝑖𝑛 = 𝑉𝑂𝐿 , 𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐿
2 𝐶 𝑖𝑛
 Differential equation approach.

The propagation delay times can be found more accurately by solving the state equation of the output node in the time
domain.

𝑑𝑉𝑜𝑢𝑡
𝐶𝐿 = 𝐼𝐶 = 𝐼𝐷𝑝 − 𝐼𝐷𝑛
𝑑𝑡

Initially, the output voltage is assumed to be equal to VOH. When the input voltage switches from low (VOL) to high
(VOH), the NMOS transistor is turned on and it starts to discharge the CL. At the same time, the PMOS transistor is
switched off; thus,

𝐼𝐷𝑝 ≈ 0

The differential equation describing the discharge event is then

𝑑𝑉𝑜𝑢𝑡
𝐶𝐿 = −𝐼𝐷𝑛
𝑑𝑡
Initially, the NMOS transistor operates in saturation region. When
the output voltage falls below 𝑉𝐷𝐷 − 𝑉𝑡𝑛 , NMOS starts to work in
triode region.

When 𝑉𝐷𝐷 ≥ 𝑉𝑜𝑢𝑡 > 𝑉𝐷𝐷 − 𝑉𝑡𝑛

𝐾𝑛 𝐾𝑛
𝐼𝐷𝑛 = (𝑉𝑖𝑛 − 𝑉𝑡𝑛 )2 = (𝑉𝑂𝐻 − 𝑉𝑡𝑛 )2
2 2

𝑡1 𝑉𝑜𝑢𝑡 =𝑉𝑂𝐻 −𝑉𝑡𝑛

1
න 𝑑𝑡 = −𝐶𝐿 න ( )𝑑𝑉𝑜𝑢𝑡
𝑡0 𝑉𝑜𝑢𝑡 =𝑉𝑂𝐻 𝐼𝐷𝑛

𝑉𝑜𝑢𝑡 =𝑉𝑂𝐻 −𝑉𝑡𝑛

2𝐶𝐿
=− න 𝑑𝑉𝑜𝑢𝑡
𝐾𝑛 (𝑉𝑂𝐻 − 𝑉𝑡𝑛 )2 𝑉𝑜𝑢𝑡 =𝑉𝑂𝐻

2𝐶𝐿 𝑉𝑡𝑛 𝑑𝑉𝑜𝑢𝑡

𝑡1 − 𝑡0 = 𝐶𝐿 = −𝐼𝐷𝑛
𝐾𝑛 (𝑉𝑂𝐻 − 𝑉𝑡𝑛 )2 𝑑𝑡
At t=𝑡1 , 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝑉𝑡𝑛 and the transistor at the saturation-
triode region boundary. Consider NMOS operates in triode
region.
𝐾𝑛
𝐼𝐷𝑛 = (2 𝑉𝑖𝑛 − 𝑉𝑡𝑛 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2 )
2
For 𝑉𝑜𝑢𝑡 ≤ 𝑉𝐷𝐷 − 𝑉𝑡𝑛
𝐾𝑛
= (2 𝑉𝑂𝐻 − 𝑉𝑡𝑛 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2 )
2

The solution in the time between 𝑡1 and 𝑡2

𝑡2 𝑉𝑜𝑢𝑡 =𝑉50%
1
න 𝑑𝑡 = −𝐶𝐿 න ( )𝑑𝑉𝑜𝑢𝑡
𝑡1 𝑉𝑜𝑢𝑡 =𝑉𝑂𝐻 −𝑉𝑡𝑛 𝐼𝐷𝑛

𝑉𝑜𝑢𝑡 =𝑉50%
𝑑𝑉𝑜𝑢𝑡 𝑑𝑉𝑜𝑢𝑡
= −2𝐶𝐿 න 𝐶𝐿 = −𝐼𝐷𝑛
𝑉𝑜𝑢𝑡 =𝑉𝑂𝐻 −𝑉𝑡𝑛 𝐾𝑛 2 𝑉𝑂𝐻 − 𝑉𝑡𝑛 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2 𝑑𝑡
Evaluating the integral using the formula

𝑉𝑜𝑢𝑡 =𝑉50%
𝑑𝑉𝑜𝑢𝑡 𝑑𝑥 1 𝑥𝑛
= −2𝐶𝐿 න න = ln( )
𝑉𝑜𝑢𝑡 =𝑉𝑂𝐻 −𝑉𝑡𝑛 𝐾𝑛 2 𝑉𝑂𝐻 − 𝑉𝑡𝑛 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2 𝑥(𝑎 + 𝑏𝑥 𝑛 ) 𝑎𝑛 𝑎 + 𝑏𝑥 𝑛

𝒃=-1 𝒙= 𝑽𝒐𝒖𝒕 a= 2 𝑽𝑶𝑯 − 𝑽𝒕𝒏 n=1

The 𝑡𝑃𝐻𝐿 can be found by combining

2𝐶𝐿 𝑉𝑡𝑛 𝐶𝐿 2(𝑉𝑂𝐻 − 𝑉𝑡𝑛 ) − 𝑉50%

𝑡𝑃𝐻𝐿 = − 2
+ ln⁡( )
𝐾𝑛 (𝑉𝑂𝐻 − 𝑉𝑡𝑛 ) 𝐾𝑛 ( 𝑉𝑂𝐻 − 𝑉𝑡𝑛 ) 𝑉50%
𝐶𝐿 2𝑉𝑡𝑛 4(𝑉𝑂𝐻 − 𝑉𝑡𝑛 )
𝑡𝑃𝐻𝐿 = [ + ln⁡( − 1)]
𝐾𝑛 (𝑉𝑂𝐻 − 𝑉𝑡𝑛 ) 𝑉𝑂𝐻 − 𝑉𝑡𝑛 𝑉𝑂𝐻 + 𝑉𝑂𝐿

For 𝑉𝑂𝐻 = 𝑉𝐷𝐷 and 𝑉𝑂𝐿 = 0

𝐶𝐿 2𝑉𝑡𝑛 4(𝑉𝐷𝐷 − 𝑉𝑡𝑛 )

𝑡𝑃𝐻𝐿 = [ + ln⁡( − 1)]
𝐾𝑛 (𝑉𝐷𝐷 − 𝑉𝑡𝑛 ) 𝑉𝐷𝐷 − 𝑉𝑡𝑛 𝑉𝐷𝐷
Similarly, the propagation delay time 𝒕𝑷𝑳𝑯

𝐶𝐿 2𝑉𝑡𝑛 4(𝑉𝐷𝐷 − 𝑉𝑡𝑛 )

𝑡𝑃𝐻𝐿 = [ + ln⁡( − 1)]
𝐾𝑛 (𝑉𝐷𝐷 − 𝑉𝑡𝑛 ) 𝑉𝐷𝐷 − 𝑉𝑡𝑛 𝑉𝐷𝐷

In order to achieve balanced propagation delays 𝑡𝑃𝐻𝐿 and 𝑡𝑃𝐿𝐻 , these conditions must be satisfied:

Vtn=|Vtp|
Kn=Kp
Inverter design with Delay constraints

In most cases, the delay constraints should be considered together with other design constraints such as noise
margins, logic (inversion) threshold, silicon area, and power dissipation.
Given the target delay value of 𝑡𝑃𝐻𝐿 , the W/L ratio of NMOS transistors can be found as

𝑊 𝐶𝐿 2𝑉𝑡𝑛 4(𝑉𝐷𝐷 − 𝑉𝑡𝑛 )

( )𝑛 = [ + ln⁡( − 1)]
𝐿 𝐾𝑛 μn Cox 𝑡𝑃𝐻𝐿 (𝑉𝐷𝐷 − 𝑉𝑡𝑛 ) 𝑉𝐷𝐷 − 𝑉𝑡𝑛 𝑉𝐷𝐷

For PMOS, the W/L at a given 𝑡𝑃𝐿𝐻

𝑊 𝐶𝐿 2|𝑉𝑡𝑝 | 4 𝑉𝐷𝐷 − |𝑉𝑡𝑝 |

( )𝑃 = [ + ln⁡( − 1)]
𝐿 𝐾𝑝 μp Cox 𝑡𝑃𝐿𝐻 (𝑉𝐷𝐷 − |𝑉𝑡𝑝 |) 𝑉𝐷𝐷 − |𝑉𝑡𝑝 | 𝑉𝐷𝐷
 Example

A company has access to a CMOS fabrication process with the device parameters listed below.

μn Cox = 120 μA/V 2

μp Cox = 60 μA/V 2
L=0.6 μm for NMOS and PMOS transistors
Vtn=0.8 V
Vtp=-1 V
Wmin=1.2 μm

Design a CMOS inverter by determining the channel widths Wn and Wp of the NMOS and PMOS transistors, to meet
the following performance specifications.
Vth = 1.5 V for VDD = 3 V
Propagation delay times t PHL < 0.2 ns and t PLH < 0.15 ns,
A falling delay of 0.35 ns for an output transition from 2 V to 0.5 V,
assuming a CL of 300 fF and ideal step input.
First, we find the minimum W/L ratios of NMOS and PMOS.

𝑊 𝐶𝐿 2𝑉𝑡𝑛 4 𝑉𝐷𝐷 − 𝑉𝑡𝑛

( )𝑛 = [ + ln( − 1)]
𝐿 μn Cox 𝑡𝑃𝐻𝐿 (𝑉𝐷𝐷 − 𝑉𝑡𝑛 ) 𝑉𝐷𝐷 − 𝑉𝑡𝑛 𝑉𝐷𝐷

300𝑥10−15 2𝑥0.8 4 3 − 0.8

= + ln −1 = 7.9
0.2𝑥10−9 𝑥120𝑥10−6 3 − 0.8 3 − 0.8 3

𝑊 𝐶𝐿 2|𝑉𝑡𝑝 | 4 𝑉𝐷𝐷 − |𝑉𝑡𝑝 |

( )𝑃 = [ + ln( − 1)]
𝐿 μp Cox 𝑡𝑃𝐿𝐻 (𝑉𝐷𝐷 − |𝑉𝑡𝑝 |) 𝑉𝐷𝐷 − |𝑉𝑡𝑝 | 𝑉𝐷𝐷

300𝑥10−15 2 4 3−1
= + ln −1 = 25.2
0.15𝑥10−9 𝑥60𝑥10−6 3 − 1 3 − 1 3
During the output transition from 2 V to 0.5 V, NMOS operates in triode region. The current in this region can be
estimated as

𝑑𝑉𝑜𝑢𝑡 1 𝑊
𝐶𝐿 = − μn Cox 2 𝑉𝑂𝐻 − 𝑉𝑡𝑛 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2
𝑑𝑡 2 𝐿 𝑛

By integration

𝑉𝑜𝑢𝑡 =0.5
−9
𝑑𝑉𝑜𝑢𝑡
𝑡𝑑𝑒𝑙𝑎𝑦 = 0.35𝑥10 = −2𝐶𝐿 න ( )
𝑊 2
𝑉𝑜𝑢𝑡 =2 μn Cox ( )𝑛 (2 𝑉𝑂𝐻 − 𝑉𝑡𝑛 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 )
𝐿

𝑉𝑜𝑢𝑡 = 0.5
−𝐶𝐿 1 𝑉𝑜𝑢𝑡
𝑡𝑑𝑒𝑙𝑎𝑦 = ln⁡( ) |
𝑊 ( 𝑉𝑂𝐻 − 𝑉𝑡𝑛 ) 2(𝑉𝑂𝐻 − 𝑉𝑡𝑛 ) − 𝑉𝑜𝑢𝑡
μn Cox ( )𝑛 𝑉𝑜𝑢𝑡 = 2
𝐿

−𝐶𝐿 1 0.5 2
𝑡𝑑𝑒𝑙𝑎𝑦 = ln − ln
𝑊 3 − 0.8 2 3 − 0.8 − 0.5 2 3 − 0.8 − 2
μn Cox
𝐿 𝑛
 −9
−300𝑥10−15
0.35𝑥10 = −2.054 + 0.182
𝑊
120 𝑥 10−6 𝑥 2.2
𝐿 𝑛

𝑊
( ) = 6.1
𝐿 𝑛

We take the larger value found from the propagation delay, 𝑊𝑛 = 4.7 𝜇𝑚

By using the given Vth=1.5

1 𝑊
𝑉𝑡𝑛 + 𝑉 + 𝑉𝑡𝑝 μn Cox ()𝑛 120𝑥10−6 𝑥7.9
𝐾𝑅 𝐷𝐷 𝐾𝑅 = 0.51 = 𝐿 =
𝑉𝑡ℎ = 𝑊 −6 𝑥 (𝑊 )
1 μp Cox ( )𝑝 60𝑥10
1+ 𝐿 𝐿 𝑝
𝐾𝑅

𝑊
( ) = 31
This value satisfies the timing requirement and Vth for the given Lp=0.6 𝜇𝑚 𝐿 𝑝
 Calculation of Interconnect Delay

RC Delay Models
The simplest model to represent the resistive and capacitive parasitic of the interconnect line consists of one lumped
resistance and one lumped capacitance. If the capacitance is initially discharged and the input signal is a rising step
pulse at t=0, at RC model
−𝑡
𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 1 − 𝑒 𝑅𝐶

At 𝑡𝑃𝐿𝐻
−𝑡𝑃𝐿𝐻
𝑉50% = 𝑉𝐷𝐷 1 − 𝑒 𝑅𝐶

−𝑡𝑃𝐿𝐻 −𝑡𝑃𝐿𝐻
0.5 𝑉𝐷𝐷 = 𝑉𝐷𝐷 1 − 𝑒 𝑅𝐶 𝑒 𝑅𝐶 = 0.5

𝑡𝑃𝐿𝐻 ≈ 0.69 𝑅𝐶 in RC delay model

 Elmore Delay Models
𝑁

𝑡𝐷𝑖 = ෍ 𝐶𝑗 ෍ 𝑅𝑘
This method gives a higher accuracy more than RC delay model. 𝑗=1 𝑓𝑜𝑟 𝑎𝑙𝑙
𝑘 ∈ 𝑃𝑖𝑗

𝒕𝑫5
= 𝑅1 𝐶1 + 𝑅1 + 𝑅2 𝐶2 + 𝑅1 + 𝑅2 𝐶3 + 𝑅1 + 𝑅2 𝐶4 + 𝑅1 + 𝑅2 + 𝑅5 𝐶5
+ 𝑅1 + 𝑅2 + 𝑅5 𝐶6 + 𝑅1 𝐶7 + 𝑅1 𝐶8 + 𝑅1 𝐶9

𝒕𝑫8
= 𝑅1 𝐶1 + 𝑅1 𝐶2 + 𝑅1 𝐶3 + 𝑅1 𝐶4 + 𝑅1 𝐶5 + 𝑅1 𝐶6 + 𝑅1 + 𝑅7 𝐶7 + 𝑅1 + 𝑅7 + 𝑅8 𝐶8
+ 𝑅1 + 𝑅7 + 𝑅8 𝐶9
 Power

The power dissipation of a CMOS circuit is instead dominated by the dynamic dissipation resulting from charging and
discharging capacitances.

Dynamic Power Consumption

❑ The output load capacitor 𝐶𝐿 is charged through PMOS from 0 to VDD and discharged
through NMOS from VDD to 0
❑ The values of the energy EVDD, taken from the supply during the transition, as well
as the energy EC, stored on the capacitor at the end of the transition can be derived
by integrating the instantaneous power over the period of interest.

∞ ∞ 𝑑𝑉𝑜𝑢𝑡 𝑉𝐷𝐷
𝐸𝑉𝐷𝐷 = ‫׬‬0 𝑖𝑉𝐷𝐷 𝑡 𝑉𝐷𝐷 𝑑𝑡 = 𝑉𝐷𝐷 ‫׬‬0 𝐶𝐿 𝑑𝑡 = 𝐶𝐿 𝑉𝐷𝐷 ‫׬‬0 𝑑𝑉𝑜𝑢𝑡 =𝐶𝐿 𝑉𝐷𝐷 2
𝑑𝑡

∞ ∞ 𝑑𝑉𝑜𝑢𝑡 𝑉𝐷𝐷 𝐶𝐿 𝑉𝐷𝐷 2

𝐸𝐶 = ‫׬‬0 𝑖𝑉𝐷𝐷 𝑡 𝑣𝑜𝑢𝑡 𝑑𝑡 = ‫׬‬0 𝐿 𝑜𝑢𝑡 𝑑𝑡 𝑑𝑡
𝐶 𝑣 = 𝐶𝐿 ‫׬‬0 𝑣𝑜𝑢𝑡 𝑑𝑉𝑜𝑢𝑡 =
2
 ❑ This means that only half of the energy supplied by the power source is stored on CL. The other half has been
dissipated by the PMOS transistor.

❑ During the discharge phase, the charge is removed from the capacitor, and its energy is dissipated in the
NMOS device.

❑ In order to compute the power consumption, we have to take into account how often the device is switched. If the
gate is switched on and off 𝑓0→1 times per second, the power consumption equals

𝑷𝒅𝒚𝒏 = 𝑪𝑳 𝑽𝑫𝑫 𝟐 𝒇𝟎→𝟏

𝑓0→1 represents the frequency of energy-consuming transitions, this is 0→1 transitions for static CMOS. 𝑃0→1
factor, also called the switching activity.

𝑷𝒅𝒚𝒏 = 𝑪𝑳 𝑽𝑫𝑫 𝟐 𝒇𝟎→𝟏 = 𝑪𝑳 𝑽𝑫𝑫 𝟐 𝑷𝟎→𝟏 𝒇

Maximum possible
event rate.
The probability that a clock event results in a 0→ 1
❑ Power consuming transitions occur 2 out of 8 times, which
is equivalent to a transition probability of 0.25 (or 25%).

Dissipation Due to Direct-Path Currents

The finite slope of the input signal causes a

direct current path between VDD and GND
for a short period of time during switching,
while the NMOS and the PMOS transistors
are conducting simultaneously.
The energy consumed per switching period.

𝐼𝑝𝑒𝑎𝑘 𝑡𝑠𝑐 𝐼𝑝𝑒𝑎𝑘 𝑡𝑠𝑐

𝐸𝑑𝑝 = 𝑉𝐷𝐷 + 𝑉𝐷𝐷 = 𝑡𝑠𝑐 𝑉𝐷𝐷 𝐼𝑝𝑒𝑎𝑘
2 2

as well as the average power consumption

𝑃𝑑𝑝 = 𝑡𝑠𝑐 𝑉𝐷𝐷 𝐼𝑝𝑒𝑎𝑘 𝑓

Static Consumption

The static (or steady-state) power dissipation of a circuit

is expressed by

𝑃𝑠𝑡𝑎𝑡 = 𝐼𝑠𝑡𝑎𝑡 𝑉𝐷𝐷

where Istat is the current that flows between the supply rails in the absence of switching activity. A leakage current
flowing through the reverse-biased diode junctions of the transistors, located between the source or drain and the
substrate.

Total Power Consumption

𝑃𝑡𝑜𝑡 = 𝑃𝑑𝑦𝑛 + 𝑃𝑑𝑝 + 𝑃𝑠𝑡𝑎𝑡 = 𝐶𝐿 𝑉𝐷𝐷 2 + 𝑉𝐷𝐷 𝐼𝑝𝑒𝑎𝑘 𝑡𝑠 𝑓0→1 + 𝑉𝐷𝐷 𝐼𝑠𝑡𝑎𝑡
End of Lecture