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LS1028A

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37 views184 pages

LS1028A

Uploaded by

santhosha rk

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Data Sheet: Technical Data Document identifier: LS1028A/LS1018A

Rev. 0 — 12/2019

QorIQ LS1028A/LS1018A Data LS1028A

Sheet

• LS1028A has two cores and LS1018A has a single core. • Graphics processing unit
• Two 32/64-bit ARM® Cortex®-A72 cores with the — Supports Geometry rate 100 Mtri/sec, Pixel rate
following capabilities: 650 Mpixel/sec, GFLOPS(32-bit high precision) =
10.4
— Up to 1.5 GHz operation
— Supports OpenGL ES 3.0, 2.0, 1.1
— Single-threaded cores with 48KB L1 instruction
cache and 32KB L1 data cache — Supports OpenCL 1.1, 1.2
— Single cluster of two cores sharing 1MB L2 cache • TSN-capable Ethernet Switch with four external ports
• Cache Coherent Interconnect (CCI-400) • Ethernet Controller (ENETC) with TSN functionality
— Up to 400 MHz operation — One RGMII interface
• One 32-bit DDR3L/DDR4 SDRAM memory controller — One 1G/2.5G SerDes-based interface with TSN
with ECC support support
— Up to 1.6 GT/s • Additional peripheral interfaces
• Four SerDes lanes for high-speed peripheral interfaces — Two high-speed USB 2.0/3.0 controllers with
integrated PHY
— Two PCI Express 3.0 controllers
— Two Enhanced Secure Digital Host Controllers
— One Serial ATA (SATA 6 Gbit/s) controller
(eSDHC) supporting SD 3.0, eMMC 4.4 and eMMC
— Up to four SGMII interfaces supporting four switch 4.5 and eMMC 5.1
ports at 1000 Mbps
— Two Controller Area Network (CAN) modules,
— Up to one 2.5G-SGMII, supporting one Ethernet optionally supporting Flexible Data-rate
controller
— Three Serial Peripheral Interface (SPI) controllers
— Up to four 2.5G-SGMII supporting four switch ports
— Eight I2C controllers
at 2.5 Gbps
— One 16550-compliant DUART
— Up to one QSGMII interface, supporting four switch
ports — Six LPUARTs
— Supports 1000Base-KX — One FlexSPI controller
— Up to one 10G-SXGMII, supporting one Ethernet — General Purpose IO (GPIO)
controller at 2.5 Gbps, 1000 Mbps, 100 Mbps, and
— Eight FlexTimers/PWM controllers
10 Mbps
— Six Synchronous Audio Interface (SAI)
— Up to one 10G-QXGMII, supporting four switch
ports with independent rates of 2.5 Gbps, 1000 • One Queue Direct Memory Access Controller (qDMA)
Mbps, 100 Mbps, and 10 Mbps • One Enhanced Direct Memory Access Controller (eDMA)
• One LCD controller and Display port/eDP interface • Generic Interrupt Controller (GIC)
— Supports Display port 1.3 and eDP 1.4 • Thermal Monitor Unit (TMU)
— Supports link transfer rates up to HBR2 (5.4Gbit/s) • FC-PBGA package, 17 mm x 17 mm
and display resolution upto 4Kp60

NXP reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products.
Contents

1 Introduction........................................................................4 3.15 Display Port/eDP interface (DP/eDP)................... 114

2 Pin assignments................................................................ 5 3.15.1 eDP/DP DC electrical characteristics.......... 114
2.1 448 ball layout diagrams.............................................5 3.15.2 eDP/DP AC timing specifications.................120
2.2 Pinout list.................................................................. 11 3.16 High-speed serial interfaces (HSSI)..................... 123
3.16.1 Signal terms definitions................................124
3 Electrical characteristics................................................ 60 3.16.2 SerDes reference clocks..............................125
3.1 Overall DC electrical characteristics......................... 60 3.16.3 SerDes transmitter and receiver reference
3.1.1 Absolute maximum ratings.............................. 60 circuits.................................................................132
3.1.2 Recommended Operating Conditions..............62 3.16.4 PCI Express.................................................132
3.1.3 Output drive capabilities.................................. 67 3.16.5 Serial ATA (SATA).......................................143
3.2 Power sequencing.................................................... 68 3.16.6 SGMII interface............................................148
3.3 Power-down requirements........................................70 3.16.7 Quad serial media-independent interface
3.4 Power characteristics................................................71 (QSGMII)............................................................ 154
3.5 Power-on ramp rate.................................................. 72 3.16.8 1000Base-KX...............................................156
3.6 Input clocks...............................................................73 3.16.9 USXGMII interface (10G-SXGMII and
3.6.1 Differential system clock 10G-QXGMII)......................................................158
(DIFF_SYSCLK_P/DIFF_SYSCLK_N) timing 3.17 I2C........................................................................ 160
specifications........................................................ 73 3.17.1 I2C DC electrical characteristics.................. 160
3.6.2 USB reference clock specifications................. 74 3.17.2 I2C AC timing specifications........................ 161
3.6.3 Gigabit Ethernet reference clock timing...........74 3.18 JTAG.....................................................................163
3.6.4 Other input clocks............................................ 75 3.18.1 JTAG DC electrical characteristics.............. 163
3.7 Reset initialization timing specifications....................75 3.18.2 JTAG AC timing specifications.................... 163
3.8 Controller Automatic Network interface (CAN)......... 76 3.19 Synchronous Audio Interface (SAI) ..................... 166
3.8.1 CAN DC electrical chracteristics...................... 76 3.19.1 SAI DC electrical characteristics..................166
3.8.2 CAN AC electrical characteristics.................... 77 3.19.2 SAI AC timing specifications........................166
3.9 DDR3L and DDR4 SDRAM controller...................... 77 3.20 Serial peripheral interface (SPI)............................167
3.9.1 DDR3L and DDR4 SDRAM controller DC 3.20.1 SPI DC electrical characteristics..................167
electrical characteristics........................................77 3.20.2 SPI AC timing specifications........................168
3.9.2 DDR3L and DDR4 SDRAM controller AC 3.21 Universal asynchronous receiver/transmitter
timing specifications..............................................79 (UART)......................................................................172
3.10 Enhanced secure digital host controller (eSDHC).. 84 3.21.1 UART DC electrical characteristics..............172
3.10.1 eSDHC DC electrical characteristics............. 84 3.21.2 UART AC timing specifications....................173
3.10.2 eSDHC AC timing specifications................... 84 3.22 Low power Universal asynchronous receiver/
3.11 Ethernet interface (EMI, RGMII and IEEE Std transmitter (LPUART)............................................... 173
™
1588 )........................................................................ 99 3.22.1 LPUART DC electrical characteristics......... 173
3.11.1 Ethernet management interface (EMI)...........99 3.22.2 LPUART AC timing specifications............... 174
3.11.2 Reduced media-independent interface 3.23 Universal serial bus 3.0 (USB)..............................174
(RGMII)............................................................... 101 3.23.1 USB 3.0 DC electrical characteristics.......... 174
3.11.3 IEEE 1588....................................................103 3.23.2 USB 3.0 AC timing specifications................ 175
3.11.4 TSN SWITCH 1588..................................... 105
3.11.5 IEEE 1722....................................................106 4 Hardware design considerations................................. 176
3.12 Flex serial peripheral interface (FlexSPI)..............107 4.1 Clock ranges...........................................................177
3.12.1 FlexSPI DC electrical characteristics........... 107 5 Thermal...........................................................................177
3.12.2 FlexSPI AC timing specifications................. 107 5.1 Recommended thermal model................................178
3.13 Flextimer interface................................................ 112 5.2 Temperature diode................................................. 178
3.13.1 FlexTimer DC electrical characteristics....... 112 5.3 Thermal management information..........................178
3.13.2 FlexTimer AC timing specifications..............112
6 Package information..................................................... 178
3.14 General purpose input/output (GPIO)...................113
6.1 Package parameters for the FC-PBGA.................. 179
3.14.1 GPIO DC electrical characteristics.............. 113
6.2 Mechanical dimensions of the FC-PBGA............... 179
3.14.2 GPIO AC timing specifications.....................114

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

NXP Semiconductors 2
7 Security fuse processor................................................181 8.1.1 Part marking ................................................. 182
8 Ordering information.....................................................181 9 Revision history.............................................................183
8.1 Part numbering nomenclature................................ 181

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

NXP Semiconductors 3
NXP Semiconductors
Introduction

1 Introduction
LS1028A is a cost-effective, power-efficient, and highly integrated system-on-chip (SoC) design that extends the reach of the
NXP value-performance line of QorIQ communications processors. Featuring extremely power-efficient 64-bit Arm® Cortex®-
A72 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.5 GHz.
This chip can be used for networking and wireless access points, industrial gateways, industrial automation, printing, imaging,
and M2M for enterprise and consumer networking and router applications.
This figure shown below represents the block diagram of the chip.

Security Core Complex Memory Controller

Security Engine
Arm TrustZone® Arm® Arm®
Secure Boot Cortex-A72 Cortex-A72
16/32-bit DDR3L/4
Power Management 48KB L1-I 48KB L1-I (w/ECC)
32KB L1-D (w/ ECC) 32KB L1-D (w/ ECC)
Standard Interfaces
1 MB L2 Cache (w/ECC)
2x SD/SDIO/eMMC
3x SPI Coherent Interconnect (CCI-400)
2x UART, 6x LPUART
Accelerators and Memory High Speed Interfaces Networking Elements
8x I2C, GPIO
6x SAI, 2x CAN-FD 256KB On-Chip SRAM 2.5 GbE
SATA 3

TSN Switch
FlexSPI PCle 3.0 2.5 GbE
8x Flex Timer
USB 3.0 2.5 GbE
w/PHY
2.5 GbE
Multimedia Interfaces 3D GPU
EDP/DP PHY PCle 3.0 USB 3.0 2.5 TSN GbE
4K LCD Controller w/PHY 1 GbE

Figure 1. LS1028A block diagram

Security Core Complex Memory Controller

Security Engine
Arm TrustZone® Arm®
Secure Boot Cortex-A72
16/32-bit DDR3L/4
Power Management 48KB L1-I (w/ECC)
32KB L1-D (w/ ECC)
Standard Interfaces
1 MB L2 Cache (w/ECC)
2x SD/SDIO/eMMC
3x SPI Coherent Interconnect (CCI-400)
2x UART, 6x LPUART
Accelerators and Memory High Speed Interfaces Networking Elements
8x I2C, GPIO
6x SAI, 2x CAN-FD 256KB On-Chip SRAM 2.5 GbE
SATA 3
TSN Switch

FlexSPI PCle 3.0 2.5 GbE

8x Flex Timer
USB 3.0 2.5 GbE
w/PHY
2.5 GbE
Multimedia Interfaces 3D GPU
EDP/DP PHY PCle 3.0 USB 3.0 2.5 TSN GbE
4K LCD Controller w/PHY 1 GbE

Figure 2. LS1018A block diagram

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 4 / 184
NXP Semiconductors
Pin assignments

2 Pin assignments

2.1 448 ball layout diagrams

This figure shows the complete view of the LS1028A BGA ball map diagram. Figure 4. on page 7, Figure 5. on page 8,
Figure 6. on page 9, and Figure 7. on page 10 show quadrant views.

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 5 / 184
NXP Semiconductors
Pin assignments

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

A A

B B

C C

D D

E E

F F
SEE DETAIL A SEE DETAIL B
G G

H H

J J

K K

L L

M M

N N

P P

R R

T T

U U

V V

W W

Y Y

AA AA
SEE DETAIL C SEE DETAIL D
AB AB

AC AC

AD AD

AE AE

AF AF

AG AG

AH AH

AJ AJ

AK AK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

DDRC1 I2C1 I2C2 I2C3 I2C4

I2C5 I2C6 XSPI1 ESDHC1 ESDHC2

UART1 UART2 SNVS System Control Clocking

EPU DFT JTAG Analog Signals Serdes 1

EC1 Ethernet MI 1 SPI3 USB1 DP_PHY1

Power Ground

Figure 3. Complete BGA Map for the LS1028A

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 6 / 184
NXP Semiconductors
Pin assignments

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
USB2_ USB2_ USB2_ DP_ DP_ DP_
A RX_
M
TX_
P
D_
P
GND001 LANE0_
N
LANE1_
N
LANE2_
N
A

USB2_ USB2_ USB2_ DP_ DP_ DP_

B RX_
P
GND004 TX_
M
D_
M
LANE0_
P
LANE1_
P
LANE2_
P
B

C GND006 GND007 GND008 GND009 GND010 GND011 GND012 GND013 C

USB1_ DP_ XSPI1_ XSPI1_

D D_
M
USB1_
ID
USB2_
VBUS
DP_
REXT REFCLK_
N
A_
CS1_B
_A_DATA D

USB1_ DP_ XSPI1_

E D_
P
GND018
USB2_
ID GND019 REFCLK_
P
GND020 _A_DATA GND021 E

XSPI1_ XSPI1_ XSPI1_

F GND026
USB1_
RESREF
USB2_
RESREF
DP_
HPD
A_
DQS
_A_DATA _A_DATA F

USB1_ USB_ XSPI1_ XSPI1_

G TX_
M
GND027 GND028 DRVVBUS GND029 _A_DATA GND030 _A_DATA G

USB1_ USB_ XSPI1_ XSPI1_ XSPI1_

H TX_
P
USB1_
VBUS
SPI3_
PCS0
PWRFAULT A_
SCK
A_
CS0_B
_A_DATA H

TA_
J GND034 GND035 SPI3_
SOUT
USB_
SDVDD1
USB_
HVDD1
USB_
HVDD2
PROG_
MTR PROG_
SFP
J

USB1_
K RX_
M
SPI3_
SIN
SPI3_
SCK
USB_
SDVDD2
USB_
SVDD1
USB_
SVDD2
VDD01 K

USB1_
L RX_
P
GND040
SDHC1_
DAT3 GND041 GND042 GND043 VDD02 GND044 L

M GND047
SDHC1_
VSEL
SDHC1_
CLK VDD06 VDD07 VDD08 GND048 M

N SDHC1_
DAT2
SDHC1_
DAT0 GND051
SDHC1_
CMD GND052 VDD10 GND053 VDD11 N

FA_
P IIC5_
SCL
SDHC1_
DAT1 ANALOG_
PIN
EVDD VDD14 GND057 VDD15 P

R IIC5_
SDA GND061
IIC1_
SCL
TH_
VDD VDD17 GND062 VDD18 GND063 R

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DDRC1 I2C1 I2C2 I2C3 I2C4

I2C5 I2C6 XSPI1 ESDHC1 ESDHC2

UART1 UART2 SNVS System Control Clocking

EPU DFT JTAG Analog Signals Serdes 1

EC1 Ethernet MI 1 SPI3 USB1 DP_PHY1

Power Ground

Figure 4. Detail A

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 7 / 184
NXP Semiconductors
Pin assignments

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DP_ DP_
A LANE3_
N
AUX_
N
GND002 D1_
MDM8
GND003
D1_
MDQ20
FA_
VL A

DP_ DP_
B LANE3_
P
AUX_
P
SDHC2_
DS
D1_
MECC1
D1_
MDQS8
D1_
MECC3
D1_
MDQ16 GND005 B

C GND014 GND015
D1_
MECC0 GND016
D1_
MDQS8_B GND017
D1_
MDQ21 C

XSPI1_
D _A_DATA SDHC2_
DAT1
SDHC2_
DAT5
D1_
MDQ28
D1_
MDQ29
D1_
MECC2
D1_
MDQ17
D1_
MDM2 D

E SDHC2_
DAT0
GND022 GND023
D1_
MDQ24 GND024
D1_
MDQS3 GND025 E

F IIC6_
SCL
SDHC2_
DAT3
SDHC2_
CLK
D1_
MDQ25
D1_
MDM3
D1_
MDQS3_B
D1_
MDQ30
D1_
MDQS2 F

G GND031 SDHC2_
DAT4
SDHC2_
CMD
GND032
D1_
MDQ26
GND033
D1_
MDQS2_B G

H IIC6_
SDA
SDHC2_
DAT2
SDHC2_
DAT6
SDHC2_
DAT7
D1_
MDQ27
D1_
MDQ31
D1_
MDQ22
D1_
MDQ18 H

J OVDD1 DP_
OVDD GND036 D1_
MDQ08 GND037 D1_
MDQ12 GND038 J

K GND039 OVDD2 DP_

AVDD
DP_
SVDD
G1VDD01 D1_
MDQ13
D1_
MDQ23
D1_
MDQ19 K

L VDD03 GND045 VDD04 VDD05 D1_

MDQ09
GND046
D1_
MDQ04 L

M VDD09 GND049
PIXEL_
DVDD GND050 G1VDD02
D1_
MDM1
D1_
MDQ00
D1_
MDQ05 M

N GND054 VDD12 VDD13 G1VDD03 GND055 D1_

MDQ01
GND056 N

Power Ground

Figure 7. Detail D

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 10 / 184
NXP Semiconductors
Pin assignments

2.2 Pinout list

This table provides the pinout listing for the LS1028A by bus. Primary functions are bolded in the table.

Table 1. Pinout list by bus

Signal Signal Description Package Pin Power Supply Notes

pin type
number

DDR SDRAM Memory Interface 1

D1_MA00 Address AB26 O G1V DD ---

D1_MA01 Address AK26 O G1V DD ---

D1_MA02 Address AA27 O G1V DD ---

D1_MA03 Address AF30 O G1V DD ---

D1_MA04 Address AG25 O G1V DD ---

D1_MA05 Address AH26 O G1V DD ---

D1_MA06 Address AD30 O G1V DD ---

D1_MA07 Address AD24 O G1V DD ---

D1_MA08 Address AB24 O G1V DD ---

D1_MA09 Address Y26 O G1V DD ---

D1_MA10 Address AC25 O G1V DD ---

D1_MA11 Address AF26 O G1V DD ---

D1_MA12 Address AF24 O G1V DD ---

D1_MA13 Address AJ29 O G1V DD ---

D1_MACT_B Activate AH28 O G1V DD ---

D1_MALERT_B Alert AC23 I G1V DD 1, 6

D1_MBA0 Bank Select AD28 O G1V DD ---

D1_MBA1 Bank Select AD26 O G1V DD ---

D1_MBG0 Bank Group Y24 O G1V DD ---

D1_MBG1 Bank Group AB30 O G1V DD ---

D1_MCAS_B Column Address Strobe / AF22 O G1V DD ---

MA[15]

D1_MCK0 Clock AF28 O G1V DD ---

D1_MCK0_B Clock Complement AG29 O G1V DD ---

D1_MCK1 Clock AB28 O G1V DD ---

D1_MCK1_B Clock Complement AC29 O G1V DD ---

D1_MCKE0 Clock Enable AJ23 O G1V DD 2

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 11 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D1_MCKE1 Clock Enable AH22 O G1V DD 2

D1_MCS0_B Chip Select AE23 O G1V DD ---

D1_MCS1_B Chip Select AK24 O G1V DD ---

D1_MCS2_B Chip Select / MCID[0] AG21 O G1V DD ---

D1_MCS3_B Chip Select / MCID[1] AK22 O G1V DD ---

D1_MDIC0 Driver Impedence Calibration Y28 IO G1V DD 3

D1_MDIC1 Driver Impedence Calibration R25 IO G1V DD 3

D1_MDM0 Data Mask P30 O G1V DD ---

D1_MDM1 Data Mask M26 O G1V DD ---

D1_MDM2 Data Mask D30 O G1V DD ---

D1_MDM3 Data Mask F24 O G1V DD ---

D1_MDM8 Data Mask A23 O G1V DD ---

D1_MDQ00 Data M28 IO G1V DD ---

D1_MDQ01 Data N27 IO G1V DD ---

D1_MDQ02 Data V30 IO G1V DD ---

D1_MDQ03 Data W29 IO G1V DD ---

D1_MDQ04 Data L29 IO G1V DD ---

D1_MDQ05 Data M30 IO G1V DD ---

D1_MDQ06 Data T30 IO G1V DD ---

D1_MDQ07 Data V28 IO G1V DD ---

D1_MDQ08 Data J23 IO G1V DD ---

D1_MDQ09 Data L25 IO G1V DD ---

D1_MDQ10 Data U27 IO G1V DD ---

D1_MDQ11 Data W25 IO G1V DD ---

D1_MDQ12 Data J27 IO G1V DD ---

D1_MDQ13 Data K26 IO G1V DD ---

D1_MDQ14 Data T28 IO G1V DD ---

D1_MDQ15 Data V26 IO G1V DD ---

D1_MDQ16 Data B28 IO G1V DD ---

D1_MDQ17 Data D28 IO G1V DD ---

D1_MDQ18 Data H30 IO G1V DD ---

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 12 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D1_MDQ19 Data K30 IO G1V DD ---

D1_MDQ20 Data A27 IO G1V DD ---

D1_MDQ21 Data C29 IO G1V DD ---

D1_MDQ22 Data H28 IO G1V DD ---

D1_MDQ23 Data K28 IO G1V DD ---

D1_MDQ24 Data E23 IO G1V DD ---

D1_MDQ25 Data F22 IO G1V DD ---

D1_MDQ26 Data G25 IO G1V DD ---

D1_MDQ27 Data H24 IO G1V DD ---

D1_MDQ28 Data D22 IO G1V DD ---

D1_MDQ29 Data D24 IO G1V DD ---

D1_MDQ30 Data F28 IO G1V DD ---

D1_MDQ31 Data H26 IO G1V DD ---

D1_MDQS0 Data Strobe P28 IO G1V DD ---

D1_MDQS0_B Data Strobe R29 IO G1V DD ---

D1_MDQS1 Data Strobe P26 IO G1V DD ---

D1_MDQS1_B Data Strobe T26 IO G1V DD ---

D1_MDQS2 Data Strobe F30 IO G1V DD ---

D1_MDQS2_B Data Strobe G29 IO G1V DD ---

D1_MDQS3 Data Strobe E27 IO G1V DD ---

D1_MDQS3_B Data Strobe F26 IO G1V DD ---

D1_MDQS8 Data Strobe B24 IO G1V DD ---

D1_MDQS8_B Data Strobe C25 IO G1V DD ---

D1_MECC0 Error Correcting Code C21 IO G1V DD ---

D1_MECC1 Error Correcting Code B22 IO G1V DD ---

D1_MECC2 Error Correcting Code D26 IO G1V DD ---

D1_MECC3 Error Correcting Code B26 IO G1V DD ---

D1_MODT0 On Die Termination AE27 O G1V DD 2

D1_MODT1 On Die Termination / MCID[2] AA23 O G1V DD 2

D1_MPAR Address Parity Out AH24 O G1V DD ---

D1_MRAS_B Row Address Strobe / MA[16] AJ27 O G1V DD ---

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 13 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D1_MWE_B Write Enable / MA[14] AD22 O G1V DD ---

I2C1

IIC1_SCL /GPIO1_DAT03 Serial Clock R5 IO OV DD 7, 8

IIC1_SDA /GPIO1_DAT02 Serial Data T4 IO OV DD 7, 8

I2C2

IIC2_SCL /GPIO1_DAT31 / Serial Clock U1 IO OV DD 7, 8

FTM1_CH0 /SDHC1_CD_B

IIC2_SDA /GPIO1_DAT30 / Serial Data T2 IO OV DD 7, 8

FTM2_CH0 /SDHC1_WP

I2C3

IIC3_SCL /GPIO1_DAT29 / Serial Clock V2 IO OV DD 7, 8

CAN1_TX /LPUART1_SOUT /
FTM7_CH0 /EVT5_B

IIC3_SDA /GPIO1_DAT28 / Serial Data U3 IO OV DD 7, 8

CAN1_RX /LPUART1_SIN /
FTM7_EXTCLK /EVT6_B

I2C4

IIC4_SCL /GPIO1_DAT27 / Serial Clock U7 IO OV DD 7, 8

CAN2_TX /
LPUART1_CTS_B /
FTM7_CH2 /EVT7_B

IIC4_SDA /GPIO1_DAT26 / Serial Data T6 IO OV DD 7, 8

CAN2_RX /
LPUART1_RTS_B /
FTM7_CH1 /EVT8_B

I2C5

IIC5_SCL /GPIO1_DAT25 / Serial Clock P2 IO OV DD 7, 8

SDHC1_CLK_SYNC_OUT /
EVT1_B

IIC5_SDA /GPIO1_DAT24 / Serial Data R1 IO OV DD 7, 8

SDHC1_CLK_SYNC_IN /
EVT2_B

I2C6

IIC6_SCL /GPIO1_DAT23 / Serial Clock F16 IO OV DD 7, 8

SDHC2_CLK_SYNC_OUT /
USB2_PWRFAULT /EVT3_B

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 14 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

IIC6_SDA /GPIO1_DAT22 / Serial Data H16 IO OV DD 7, 8

SDHC2_CLK_SYNC_IN /
USB2_DRVVBUS /EVT0_B

I2C7

IIC7_SCL/ SDHC2_DAT5 / Serial Clock D20 IO OV DD 7, 8

GPIO2_DAT16 /
LPUART4_CTS_B /
FTM4_CH2 /XSPI1_B_DATA5

IIC7_SDA/ SDHC2_DAT4 / Serial Data G19 IO OV DD 7, 8

GPIO2_DAT15 /
LPUART4_RTS_B /
FTM4_CH1 /XSPI1_B_DATA4

I2C8

IIC8_SCL/ SDHC2_DAT7 / Serial Clock H22 IO OV DD 7, 8

GPIO2_DAT18 /
LPUART4_SOUT /
FTM4_CH0 /XSPI1_B_DATA7

IIC8_SDA/ SDHC2_DAT6 / Serial Data H20 IO OV DD 7, 8

GPIO2_DAT17 /
LPUART4_SIN /
FTM4_EXTCLK /
XSPI1_B_DATA6

XSPI1

XSPI1_A_CS0_B / Chip Select H12 O OV DD 1, 4

GPIO2_DAT21 /FTM8_CH1 /
cfg_svr0

XSPI1_A_CS1_B / Chip Select D12 O OV DD 1, 5

GPIO2_DAT20 /FTM8_CH0 /
cfg_svr1

XSPI1_A_DATA0 / Data G11 IO OV DD ---

GPIO2_DAT24 /
LPUART3_RTS_B /
FTM3_CH1

XSPI1_A_DATA1 / Data F12 IO OV DD ---

GPIO2_DAT25 /
LPUART3_CTS_B /
FTM3_CH2

XSPI1_A_DATA2 / Data H14 IO OV DD ---

GPIO2_DAT26 /
LPUART3_SIN /
FTM3_EXTCLK

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 15 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

XSPI1_A_DATA3 / Data E13 IO OV DD ---

GPIO2_DAT27 /
LPUART3_SOUT /FTM3_CH0

XSPI1_A_DATA4 / Data F14 IO OV DD ---

GPIO2_DAT28 /
LPUART2_RTS_B /
FTM2_CH1

XSPI1_A_DATA5 / Data D14 IO OV DD ---

GPIO2_DAT29 /
LPUART2_CTS_B /
FTM2_CH2

XSPI1_A_DATA6 / Data D16 IO OV DD ---

GPIO2_DAT30 /
LPUART2_SIN /
FTM2_EXTCLK

XSPI1_A_DATA7 / Data G15 IO OV DD ---

GPIO2_DAT31 /
LPUART2_SOUT

XSPI1_A_DQS / Data Strobe F10 IO OV DD ---

GPIO2_DAT23 /
FTM8_EXTCLK

XSPI1_A_SCK / Clock H10 O OV DD 1, 5

GPIO2_DAT22 /FTM8_CH2 /
cfg_eng_use0

XSPI1_B_CS1_B/ Chip Select G21 O OV DD 1

SDHC2_CMD /
GPIO2_DAT19 /SPI2_SOUT

XSPI1_B_DATA0/ Data E17 IO OV DD 4

SDHC2_DAT0 /
GPIO2_DAT11 /SPI2_SIN /
LPUART5_RTS_B /
FTM5_CH1 /cfg_gpinput4

XSPI1_B_DATA1/ Data D18 IO OV DD 4

SDHC2_DAT1 /
GPIO2_DAT12 /SPI2_PCS2 /
LPUART5_CTS_B /
FTM5_CH2 /cfg_gpinput5

XSPI1_B_DATA2/ Data H18 IO OV DD 4

SDHC2_DAT2 /
GPIO2_DAT13 /SPI2_PCS1 /
LPUART5_SIN /
FTM5_EXTCLK /cfg_gpinput6

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 16 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

XSPI1_B_DATA3/ Data F18 IO OV DD 4

SDHC2_DAT3 /
GPIO2_DAT14 /SPI2_PCS0 /
LPUART5_SOUT /
FTM5_CH0 /cfg_gpinput7

XSPI1_B_DATA4/ Data G19 IO OV DD ---

SDHC2_DAT4 /
GPIO2_DAT15 /IIC7_SDA /
LPUART4_RTS_B /
FTM4_CH1

XSPI1_B_DATA5/ Data D20 IO OV DD ---

SDHC2_DAT5 /
GPIO2_DAT16 /IIC7_SCL /
LPUART4_CTS_B /
FTM4_CH2

XSPI1_B_DATA6/ Data H20 IO OV DD ---

SDHC2_DAT6 /
GPIO2_DAT17 /IIC8_SDA /
LPUART4_SIN /
FTM4_EXTCLK

XSPI1_B_DATA7/ Data H22 IO OV DD ---

SDHC2_DAT7 /
GPIO2_DAT18 /IIC8_SCL /
LPUART4_SOUT /FTM4_CH0

XSPI1_B_DQS/ SDHC2_DS / Data Strobe B20 IO OV DD ---

GPIO2_DAT10 /SPI2_PCS3

XSPI1_B_SCK/ Clock F20 O OV DD 1

SDHC2_CLK /
GPIO2_DAT09 /SPI2_SCK

eSDHC 1

SDHC1_CD_B/ IIC2_SCL / Card Detect U1 I OV DD 1

GPIO1_DAT31 /FTM1_CH0

SDHC1_CLK / Host to Card Clock M6 O EV DD 1

GPIO1_DAT16 /SPI1_SCK /
SAI2_TX_SYNC /
SAI2_RX_SYNC

SDHC1_CLK_SYNC_IN/ Input Synchronous Clock R1 I OV DD 1

IIC5_SDA /GPIO1_DAT24 /
EVT2_B

SDHC1_CLK_SYNC_OUT/ Output Synchronuous Clock P2 O OV DD 1

IIC5_SCL /GPIO1_DAT25 /
EVT1_B

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 17 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SDHC1_CMD / Command/Response N7 IO EV DD 26
GPIO1_DAT21 /SPI1_SOUT /
SAI1_TX_BCLK /
SAI1_RX_BCLK

SDHC1_DAT0 / Data N3 IO EV DD 4, 26
GPIO1_DAT17 /SPI1_SIN /
SAI2_TX_DATA /
SAI2_RX_DATA /cfg_gpinput0

SDHC1_DAT1 / Data P4 IO EV DD 4, 26
GPIO1_DAT18 /SPI1_PCS2 /
SAI2_TX_BCLK /
SAI2_RX_BCLK /cfg_gpinput1

SDHC1_DAT2 / Data N1 IO EV DD 4, 26
GPIO1_DAT19 /SPI1_PCS1 /
SAI1_TX_SYNC /
SAI1_RX_SYNC /
cfg_gpinput2

SDHC1_DAT3 / Data L5 IO EV DD 4, 26
GPIO1_DAT20 /SPI1_PCS0 /
SAI1_TX_DATA /
SAI1_RX_DATA /cfg_gpinput3

SDHC1_VSEL / SDHC Voltage Select M4 O OV DD 1

GPIO1_DAT15 /SPI1_PCS3

SDHC1_WP/ IIC2_SDA / Write Protect T2 I OV DD 1

GPIO1_DAT30 /FTM2_CH0

eSDHC 2

SDHC2_CLK / Host to Card Clock F20 O OV DD 1

GPIO2_DAT09 /SPI2_SCK /
XSPI1_B_SCK

SDHC2_CLK_SYNC_IN/ Input Synchronous Clock H16 I OV DD 1

IIC6_SDA /GPIO1_DAT22 /
USB2_DRVVBUS /EVT0_B

SDHC2_CLK_SYNC_OUT/ Output Synchronuous Clock F16 O OV DD 1

IIC6_SCL /GPIO1_DAT23 /
USB2_PWRFAULT /EVT3_B

SDHC2_CMD / Command/Response G21 IO OV DD 26

GPIO2_DAT19 /SPI2_SOUT /
XSPI1_B_CS1_B

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 18 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SDHC2_DAT0 / Data E17 IO OV DD 4, 26

GPIO2_DAT11 /SPI2_SIN /
LPUART5_RTS_B /
FTM5_CH1 /
XSPI1_B_DATA0 /
cfg_gpinput4

SDHC2_DAT1 / Data D18 IO OV DD 4, 26

GPIO2_DAT12 /SPI2_PCS2 /
LPUART5_CTS_B /
FTM5_CH2 /
XSPI1_B_DATA1 /
cfg_gpinput5

SDHC2_DAT2 / Data H18 IO OV DD 4, 26

GPIO2_DAT13 /SPI2_PCS1 /
LPUART5_SIN /
FTM5_EXTCLK /
XSPI1_B_DATA2 /
cfg_gpinput6

SDHC2_DAT3 / Data F18 IO OV DD 4, 26

GPIO2_DAT14 /SPI2_PCS0 /
LPUART5_SOUT /
FTM5_CH0 /
XSPI1_B_DATA3 /
cfg_gpinput7

SDHC2_DAT4 / Data G19 IO OV DD 26

GPIO2_DAT15 /IIC7_SDA /
LPUART4_RTS_B /
FTM4_CH1 /XSPI1_B_DATA4

SDHC2_DAT5 / Data D20 IO OV DD 26

GPIO2_DAT16 /IIC7_SCL /
LPUART4_CTS_B /
FTM4_CH2 /XSPI1_B_DATA5

SDHC2_DAT6 / Data H20 IO OV DD 26

GPIO2_DAT17 /IIC8_SDA /
LPUART4_SIN /
FTM4_EXTCLK /
XSPI1_B_DATA6

SDHC2_DAT7 / Data H22 IO OV DD 26

GPIO2_DAT18 /IIC8_SCL /
LPUART4_SOUT /
FTM4_CH0 /XSPI1_B_DATA7

SDHC2_DS /GPIO2_DAT10 / Data Strobe (eMMC HS400 B20 I OV DD 1

SPI2_PCS3 /XSPI1_B_DQS mode)

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 19 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

DUART

UART1_SIN /GPIO1_DAT10 / Receive Data AE7 I OV DD 1

LPUART6_SIN /
FTM6_EXTCLK

UART1_SOUT / Transmit Data AB6 O OV DD 1, 4

GPIO1_DAT11 /
LPUART6_SOUT /
FTM6_CH0 /cfg_rcw_src1

DUART

UART2_SIN /GPIO1_DAT06 / Receive Data AD6 I OV DD 1

LPUART6_CTS_B /
FTM6_CH2

UART2_SOUT / Transmit Data AC5 O OV DD 1, 4

GPIO1_DAT07 /
LPUART6_RTS_B /
FTM6_CH1 /cfg_rcw_src0

Trust

TA_BB_TMP_DETECT_B Battery Backed Tamper Detect AC7 I TA_BB_V DD ---

TA_TMP_DETECT_B Tamper Detect AA7 I OV DD ---

System Control

HRESET_B Hard Reset AB2 IO OV DD 27, 7

PORESET_B Power On Reset Y6 I OV DD 21, 23

RESET_REQ_B / Reset Request (POR or Hard) AC1 O OV DD 5

GPIO2_DAT08

Clocking

DIFF_SYSCLK_N Differential System Clock AH8 I - ---

(negative)

DIFF_SYSCLK_P Differential System Clock AJ7 I - ---

(positive)

Debug

ASLEEP /GPIO2_DAT06 / Asleep AA1 O OV DD 4

EVT9_B /cfg_rcw_src2

CLK_OUT /GPIO2_DAT07 / Clock Out AB4 O OV DD 4

FTM1_CH1 /EVT4_B /
cfg_rcw_src3

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 20 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

EVT0_B/ IIC6_SDA / Event 0 H16 O OV DD 1

GPIO1_DAT22 /
SDHC2_CLK_SYNC_IN /
USB2_DRVVBUS

EVT1_B/ IIC5_SCL / Event 1 P2 O OV DD 1

GPIO1_DAT25 /
SDHC1_CLK_SYNC_OUT

EVT2_B/ IIC5_SDA / Event 2 R1 O OV DD 1

GPIO1_DAT24 /
SDHC1_CLK_SYNC_IN

EVT3_B/ IIC6_SCL / Event 3 F16 O OV DD 1

GPIO1_DAT23 /
SDHC2_CLK_SYNC_OUT /
USB2_PWRFAULT

EVT4_B/ CLK_OUT / Event 4 AB4 O OV DD 1, 4

GPIO2_DAT07 /FTM1_CH1 /
cfg_rcw_src3

EVT5_B/ IIC3_SCL / Event 5 V2 IO OV DD ---

GPIO1_DAT29 /CAN1_TX /
LPUART1_SOUT /FTM7_CH0

EVT6_B/ IIC3_SDA / Event 6 U3 IO OV DD ---

GPIO1_DAT28 /CAN1_RX /
LPUART1_SIN /
FTM7_EXTCLK

EVT7_B/ IIC4_SCL / Event 7 U7 IO OV DD ---

GPIO1_DAT27 /CAN2_TX /
LPUART1_CTS_B /
FTM7_CH2

EVT8_B/ IIC4_SDA / Event 8 T6 IO OV DD ---

GPIO1_DAT26 /CAN2_RX /
LPUART1_RTS_B /
FTM7_CH1

EVT9_B/ ASLEEP / Event 9 AA1 O OV DD 1, 4

GPIO2_DAT06 /cfg_rcw_src2

DFT

SCAN_MODE_B Internal Use Only AA3 I OV DD 10 21

TEST_SEL_B Internal Use Only Y4 I OV DD 21 22

JTAG

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 21 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

TBSCAN_EN_B An IEEE 1149.1 JTAG W5 I OV DD 19, 21

Compliance Enable pin. 0: To
be compliant to the 1149.1
specification for boundary
scan functions. The JTAG
compliant state is documented
in the BSDL. 1: JTAG
connects to DAP controller for
the Arm core debug.

TCK Test Clock W7 I OV DD ---

TDI Test Data In V4 I OV DD 9

TDO Test Data Out W1 O OV DD 2

TMS Test Mode Select V6 I OV DD 9

TRST_B Test Reset Y2 I OV DD 9

Analog Signals

D1_MVREF SSTL Reference Voltage P24 IO G1V DD/2 ---

FA_ANALOG_G_V Internal Use Only Y30 IO - 15

FA_ANALOG_PIN Internal Use Only P6 IO - 15

TD1_ANODE Thermal diode anode AD10 IO - 17

TD1_CATHODE Thermal diode cathode AE9 IO - 17

Serdes 1

SD1_IMP_CAL_RX SerDes Receive Impedence AD14 - SV DD 11

Calibration

SD1_IMP_CAL_TX SerDes Transmit Impedance AD20 - XV DD 16

Calibration

SD1_REF_CLK1_N SerDes PLL 1 Reference AG9 I SV DD ---

Clock Complement

SD1_REF_CLK1_P SerDes PLL 1 Reference AF10 I SV DD ---

Clock

SD1_REF_CLK2_N SerDes PLL 2 Reference AJ19 I SV DD ---

Clock Complement

SD1_REF_CLK2_P SerDes PLL 2 Reference AK20 I SV DD ---

Clock

SD1_RX0_N SerDes Receive Data AJ11 I SV DD ---

(negative)

SD1_RX0_P SerDes Receive Data AK10 I SV DD ---

(positive)

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 22 / 184
NXP Semiconductors
Pin assignments

(positive)

Ethernet Controller 1

EC1_GTX_CLK / Transmit Clock Out AH4 O OV DD 1

GPIO3_DAT07 /
SAI4_TX_SYNC /
SAI4_RX_SYNC /
FTM1_EXTCLK /
SWITCH_1588_DAT0

EC1_GTX_CLK125 / 125MHz Reference Clock AK2 I OV DD 1

GPIO3_DAT06 /
EC1_1722_DAT0

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 23 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

EC1_RXD0 /GPIO3_DAT02 / Receive Data AG1 I OV DD 1

SAI6_TX_BCLK /
SAI6_RX_BCLK

EC1_RXD1 /GPIO3_DAT03 / Receive Data AF2 I OV DD 1

SAI3_TX_BCLK /
SAI3_RX_BCLK

EC1_RXD2 /GPIO3_DAT04 / Receive Data AE3 I OV DD 1

SAI4_TX_BCLK /
SAI4_RX_BCLK /FTM1_CH2

EC1_RXD3 /GPIO3_DAT05 / Receive Data AE1 I OV DD 1

SAI5_TX_BCLK /
SAI5_RX_BCLK /FTM1_CH3 /
EC1_1722_DAT1

EC1_RX_CLK / Receive Clock AD2 I OV DD 1

GPIO3_DAT01 /
SAI3_TX_SYNC /
SAI3_RX_SYNC /
FTM1_QD_PHA /
EC1_1588_CLK_IN

EC1_RX_DV / Receive Data Valid AH2 I OV DD 1

GPIO3_DAT00 /
SAI6_TX_SYNC /
SAI6_RX_SYNC /
FTM1_QD_PHB /
EC1_1588_TRIG_IN1

EC1_TXD0 /GPIO3_DAT09 / Transmit Data AF6 O OV DD 1

SAI6_TX_DATA /
SAI6_RX_DATA /FTM1_CH4 /
EC1_1588_PULSE_OUT2

EC1_TXD1 /GPIO3_DAT10 / Transmit Data AF4 O OV DD 1

SAI3_TX_DATA /
SAI3_RX_DATA /FTM1_CH5 /
EC1_1588_CLK_OUT

EC1_TXD2 /GPIO3_DAT11 / Transmit Data AD4 O OV DD 1

SAI4_TX_DATA /
SAI4_RX_DATA /FTM1_CH6 /
EC1_1588_ALARM_OUT1

EC1_TXD3 /GPIO3_DAT12 / Transmit Data AG5 O OV DD 1

SAI5_TX_DATA /
SAI5_RX_DATA /FTM1_CH7 /
EC1_1588_PULSE_OUT1

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 24 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

EC1_TX_EN /GPIO3_DAT08 / Transmit Enable AJ3 O OV DD 1 14

SAI5_TX_SYNC /
SAI5_RX_SYNC /
FTM1_FAULT /
SWITCH_1588_DAT1

Ethernet Management Interface 1

EMI1_MDC /cfg_dram_type Management Data Clock AK6 O OV DD 4

EMI1_MDIO Management Data In/Out AK4 IO OV DD ---

General Purpose Input/Output

GPIO1_DAT02/ IIC1_SDA General Purpose Input/Output T4 IO OV DD ---

GPIO1_DAT03/ IIC1_SCL General Purpose Input/Output R5 IO OV DD ---

GPIO1_DAT06/ UART2_SIN / General Purpose Input/Output AD6 IO OV DD ---

LPUART6_CTS_B /
FTM6_CH2

GPIO1_DAT07/ General Purpose Input/Output AC5 O OV DD 1, 4

UART2_SOUT /
LPUART6_RTS_B /
FTM6_CH1 /cfg_rcw_src0

GPIO1_DAT10/ UART1_SIN / General Purpose Input/Output AE7 IO OV DD ---

LPUART6_SIN /
FTM6_EXTCLK

GPIO1_DAT11/ General Purpose Input/Output AB6 O OV DD 1, 4

UART1_SOUT /
LPUART6_SOUT /
FTM6_CH0 /cfg_rcw_src1

GPIO1_DAT15/ General Purpose Input/Output M4 IO OV DD ---

SDHC1_VSEL /SPI1_PCS3

GPIO1_DAT16/ General Purpose Input/Output M6 IO EV DD ---

SDHC1_CLK /SPI1_SCK /
SAI2_TX_SYNC /
SAI2_RX_SYNC

GPIO1_DAT17/ General Purpose Input/Output N3 IO EV DD 4

SDHC1_DAT0 /SPI1_SIN /
SAI2_TX_DATA /
SAI2_RX_DATA /cfg_gpinput0

GPIO1_DAT18/ General Purpose Input/Output P4 IO EV DD 4

SDHC1_DAT1 /SPI1_PCS2 /
SAI2_TX_BCLK /
SAI2_RX_BCLK /cfg_gpinput1

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 25 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO1_DAT19/ General Purpose Input/Output N1 IO EV DD 4

SDHC1_DAT2 /SPI1_PCS1 /
SAI1_TX_SYNC /
SAI1_RX_SYNC /
cfg_gpinput2

GPIO1_DAT20/ General Purpose Input/Output L5 IO EV DD 4

SDHC1_DAT3 /SPI1_PCS0 /
SAI1_TX_DATA /
SAI1_RX_DATA /cfg_gpinput3

GPIO1_DAT21/ General Purpose Input/Output N7 IO EV DD ---

SDHC1_CMD /SPI1_SOUT /
SAI1_TX_BCLK /
SAI1_RX_BCLK

GPIO1_DAT22/ IIC6_SDA / General Purpose Input/Output H16 IO OV DD ---

SDHC2_CLK_SYNC_IN /
USB2_DRVVBUS /EVT0_B

GPIO1_DAT23/ IIC6_SCL / General Purpose Input/Output F16 IO OV DD ---

SDHC2_CLK_SYNC_OUT /
USB2_PWRFAULT /EVT3_B

GPIO1_DAT24/ IIC5_SDA / General Purpose Input/Output R1 IO OV DD ---

SDHC1_CLK_SYNC_IN /
EVT2_B

GPIO1_DAT25/ IIC5_SCL / General Purpose Input/Output P2 IO OV DD ---

SDHC1_CLK_SYNC_OUT /
EVT1_B

GPIO1_DAT26/ IIC4_SDA / General Purpose Input/Output T6 IO OV DD ---

CAN2_RX /
LPUART1_RTS_B /
FTM7_CH1 /EVT8_B

GPIO1_DAT27/ IIC4_SCL / General Purpose Input/Output U7 IO OV DD ---

CAN2_TX /
LPUART1_CTS_B /
FTM7_CH2 /EVT7_B

GPIO1_DAT28/ IIC3_SDA / General Purpose Input/Output U3 IO OV DD ---

CAN1_RX /LPUART1_SIN /
FTM7_EXTCLK /EVT6_B

GPIO1_DAT29/ IIC3_SCL / General Purpose Input/Output V2 IO OV DD ---

CAN1_TX /LPUART1_SOUT /
FTM7_CH0 /EVT5_B

GPIO1_DAT30/ IIC2_SDA / General Purpose Input/Output T2 IO OV DD ---

FTM2_CH0 /SDHC1_WP

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 26 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO1_DAT31/ IIC2_SCL / General Purpose Input/Output U1 IO OV DD ---

FTM1_CH0 /SDHC1_CD_B

GPIO2_DAT06/ ASLEEP / General Purpose Input/Output AA1 O OV DD 1, 4

EVT9_B /cfg_rcw_src2

GPIO2_DAT07/ CLK_OUT / General Purpose Input/Output AB4 O OV DD 1, 4

FTM1_CH1 /EVT4_B /
cfg_rcw_src3

GPIO2_DAT08/ General Purpose Input/Output AC1 O OV DD 1, 5

RESET_REQ_B

GPIO2_DAT09/ General Purpose Input/Output F20 IO OV DD ---

SDHC2_CLK /SPI2_SCK /
XSPI1_B_SCK

GPIO2_DAT10/ SDHC2_DS / General Purpose Input/Output B20 IO OV DD ---

SPI2_PCS3 /XSPI1_B_DQS

GPIO2_DAT11/ General Purpose Input/Output E17 IO OV DD 4

SDHC2_DAT0 /SPI2_SIN /
LPUART5_RTS_B /
FTM5_CH1 /
XSPI1_B_DATA0 /
cfg_gpinput4

GPIO2_DAT12/ General Purpose Input/Output D18 IO OV DD 4

SDHC2_DAT1 /SPI2_PCS2 /
LPUART5_CTS_B /
FTM5_CH2 /
XSPI1_B_DATA1 /
cfg_gpinput5

GPIO2_DAT13/ General Purpose Input/Output H18 IO OV DD 4

SDHC2_DAT2 /SPI2_PCS1 /
LPUART5_SIN /
FTM5_EXTCLK /
XSPI1_B_DATA2 /
cfg_gpinput6

GPIO2_DAT14/ General Purpose Input/Output F18 IO OV DD 4

SDHC2_DAT3 /SPI2_PCS0 /
LPUART5_SOUT /
FTM5_CH0 /
XSPI1_B_DATA3 /
cfg_gpinput7

GPIO2_DAT15/ General Purpose Input/Output G19 IO OV DD ---

SDHC2_DAT4 /IIC7_SDA /
LPUART4_RTS_B /
FTM4_CH1 /XSPI1_B_DATA4

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 27 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO2_DAT16/ General Purpose Input/Output D20 IO OV DD ---

SDHC2_DAT5 /IIC7_SCL /
LPUART4_CTS_B /
FTM4_CH2 /XSPI1_B_DATA5

GPIO2_DAT17/ General Purpose Input/Output H20 IO OV DD ---

SDHC2_DAT6 /IIC8_SDA /
LPUART4_SIN /
FTM4_EXTCLK /
XSPI1_B_DATA6

GPIO2_DAT18/ General Purpose Input/Output H22 IO OV DD ---

SDHC2_DAT7 /IIC8_SCL /
LPUART4_SOUT /
FTM4_CH0 /XSPI1_B_DATA7

GPIO2_DAT19/ General Purpose Input/Output G21 IO OV DD ---

SDHC2_CMD /SPI2_SOUT /
XSPI1_B_CS1_B

GPIO2_DAT20/ General Purpose Input/Output D12 O OV DD 1, 5

XSPI1_A_CS1_B /
FTM8_CH0 /cfg_svr1

GPIO2_DAT21/ General Purpose Input/Output H12 O OV DD 1, 4

XSPI1_A_CS0_B /
FTM8_CH1 /cfg_svr0

GPIO2_DAT22/ General Purpose Input/Output H10 O OV DD 1, 5

XSPI1_A_SCK /FTM8_CH2 /
cfg_eng_use0

GPIO2_DAT23/ General Purpose Input/Output F10 IO OV DD ---

XSPI1_A_DQS /
FTM8_EXTCLK

GPIO2_DAT24/ General Purpose Input/Output G11 IO OV DD ---

XSPI1_A_DATA0 /
LPUART3_RTS_B /
FTM3_CH1

GPIO2_DAT25/ General Purpose Input/Output F12 IO OV DD ---

XSPI1_A_DATA1 /
LPUART3_CTS_B /
FTM3_CH2

GPIO2_DAT26/ General Purpose Input/Output H14 IO OV DD ---

XSPI1_A_DATA2 /
LPUART3_SIN /
FTM3_EXTCLK

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 28 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO2_DAT27/ General Purpose Input/Output E13 IO OV DD ---

XSPI1_A_DATA3 /
LPUART3_SOUT /FTM3_CH0

GPIO2_DAT28/ General Purpose Input/Output F14 IO OV DD ---

XSPI1_A_DATA4 /
LPUART2_RTS_B /
FTM2_CH1

GPIO2_DAT29/ General Purpose Input/Output D14 IO OV DD ---

XSPI1_A_DATA5 /
LPUART2_CTS_B /
FTM2_CH2

GPIO2_DAT30/ General Purpose Input/Output D16 IO OV DD ---

XSPI1_A_DATA6 /
LPUART2_SIN /
FTM2_EXTCLK

GPIO2_DAT31/ General Purpose Input/Output G15 IO OV DD ---

XSPI1_A_DATA7 /
LPUART2_SOUT

GPIO3_DAT00/ General Purpose Input/Output AH2 IO OV DD ---

EC1_RX_DV /
SAI6_TX_SYNC /
SAI6_RX_SYNC /
FTM1_QD_PHB /
EC1_1588_TRIG_IN1

GPIO3_DAT01/ General Purpose Input/Output AD2 IO OV DD ---

EC1_RX_CLK /
SAI3_TX_SYNC /
SAI3_RX_SYNC /
FTM1_QD_PHA /
EC1_1588_CLK_IN

GPIO3_DAT02/ EC1_RXD0 / General Purpose Input/Output AG1 IO OV DD ---

SAI6_TX_BCLK /
SAI6_RX_BCLK

GPIO3_DAT03/ EC1_RXD1 / General Purpose Input/Output AF2 IO OV DD ---

SAI3_TX_BCLK /
SAI3_RX_BCLK

GPIO3_DAT04/ EC1_RXD2 / General Purpose Input/Output AE3 IO OV DD ---

SAI4_TX_BCLK /
SAI4_RX_BCLK /FTM1_CH2

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 29 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO3_DAT05/ EC1_RXD3 / General Purpose Input/Output AE1 IO OV DD ---

SAI5_TX_BCLK /
SAI5_RX_BCLK /FTM1_CH3 /
EC1_1722_DAT1

GPIO3_DAT06/ General Purpose Input/Output AK2 IO OV DD ---

EC1_GTX_CLK125 /
EC1_1722_DAT0

GPIO3_DAT07/ General Purpose Input/Output AH4 IO OV DD ---

EC1_GTX_CLK /
SAI4_TX_SYNC /
SAI4_RX_SYNC /
FTM1_EXTCLK /
SWITCH_1588_DAT0

GPIO3_DAT08/ EC1_TX_EN / General Purpose Input/Output AJ3 IO OV DD ---

SAI5_TX_SYNC /
SAI5_RX_SYNC /
FTM1_FAULT /
SWITCH_1588_DAT1

GPIO3_DAT09/ EC1_TXD0 / General Purpose Input/Output AF6 IO OV DD ---

SAI6_TX_DATA /
SAI6_RX_DATA /FTM1_CH4 /
EC1_1588_PULSE_OUT2

GPIO3_DAT10/ EC1_TXD1 / General Purpose Input/Output AF4 IO OV DD ---

SAI3_TX_DATA /
SAI3_RX_DATA /FTM1_CH5 /
EC1_1588_CLK_OUT

GPIO3_DAT11/ EC1_TXD2 / General Purpose Input/Output AD4 IO OV DD ---

SAI4_TX_DATA /
SAI4_RX_DATA /FTM1_CH6 /
EC1_1588_ALARM_OUT1

GPIO3_DAT12/ EC1_TXD3 / General Purpose Input/Output AG5 IO OV DD ---

SAI5_TX_DATA /
SAI5_RX_DATA /FTM1_CH7 /
EC1_1588_PULSE_OUT1

GPIO3_DAT13/ SPI3_SIN / General Purpose Input/Output K4 IO OV DD ---

EC1_1722_DAT2

GPIO3_DAT14/ SPI3_SCK / General Purpose Input/Output K6 IO OV DD ---

EC1_1722_DAT3

GPIO3_DAT15/ SPI3_PCS0 / General Purpose Input/Output H6 IO OV DD ---

EC1_1588_TRIG_IN2 /
SWITCH_1588_DAT2

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 30 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO3_DAT16/ SPI3_SOUT / General Purpose Input/Output J5 IO OV DD ---

EC1_1588_ALARM_OUT2 /
SWITCH_1588_DAT3

GPIO3_DAT17/ General Purpose Input/Output H8 IO OV DD ---

USB_PWRFAULT /
SPI3_PCS1

GPIO3_DAT18/ General Purpose Input/Output G7 IO OV DD ---

USB_DRVVBUS /SPI3_PCS2

Flex Timer Module

FTM1_CH0/ IIC2_SCL / Channel 0 U1 IO OV DD ---

GPIO1_DAT31 /
SDHC1_CD_B

FTM1_CH1/ CLK_OUT / Channel 1 AB4 O OV DD 1, 4

GPIO2_DAT07 /EVT4_B /
cfg_rcw_src3

FTM1_CH2/ EC1_RXD2 / Channel 2 AE3 IO OV DD ---

GPIO3_DAT04 /
SAI4_TX_BCLK /
SAI4_RX_BCLK

FTM1_CH3/ EC1_RXD3 / Channel 3 AE1 IO OV DD ---

GPIO3_DAT05 /
SAI5_TX_BCLK /
SAI5_RX_BCLK /
EC1_1722_DAT1

FTM1_CH4/ EC1_TXD0 / Channel 4 AF6 IO OV DD ---

GPIO3_DAT09 /
SAI6_TX_DATA /
SAI6_RX_DATA /
EC1_1588_PULSE_OUT2

FTM1_CH5/ EC1_TXD1 / Channel 5 AF4 IO OV DD ---

GPIO3_DAT10 /
SAI3_TX_DATA /
SAI3_RX_DATA /
EC1_1588_CLK_OUT

FTM1_CH6/ EC1_TXD2 / Channel 6 AD4 IO OV DD ---

GPIO3_DAT11 /
SAI4_TX_DATA /
SAI4_RX_DATA /
EC1_1588_ALARM_OUT1

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 31 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

FTM1_CH7/ EC1_TXD3 / Channel 7 AG5 IO OV DD ---

GPIO3_DAT12 /
SAI5_TX_DATA /
SAI5_RX_DATA /
EC1_1588_PULSE_OUT1

FTM1_EXTCLK/ External Clock AH4 I OV DD 1

EC1_GTX_CLK /
GPIO3_DAT07 /
SAI4_TX_SYNC /
SAI4_RX_SYNC /
SWITCH_1588_DAT0

FTM1_FAULT/ EC1_TX_EN / Fault AJ3 I OV DD 1

GPIO3_DAT08 /
SAI5_TX_SYNC /
SAI5_RX_SYNC /
SWITCH_1588_DAT1

FTM1_QD_PHA/ Phase A AD2 I OV DD 1

EC1_RX_CLK /
GPIO3_DAT01 /
SAI3_TX_SYNC /
SAI3_RX_SYNC /
EC1_1588_CLK_IN

FTM1_QD_PHB/ Phase B AH2 I OV DD 1

EC1_RX_DV /
GPIO3_DAT00 /
SAI6_TX_SYNC /
SAI6_RX_SYNC /
EC1_1588_TRIG_IN1

FTM2_CH0/ IIC2_SDA / Channel 0 T2 IO OV DD ---

GPIO1_DAT30 /SDHC1_WP

FTM2_CH1/ Channel 1 F14 IO OV DD ---

XSPI1_A_DATA4 /
GPIO2_DAT28 /
LPUART2_RTS_B

FTM2_CH2/ Channel 2 D14 IO OV DD ---

XSPI1_A_DATA5 /
GPIO2_DAT29 /
LPUART2_CTS_B

FTM2_EXTCLK/ External Clock D16 I OV DD 1

XSPI1_A_DATA6 /
GPIO2_DAT30 /
LPUART2_SIN

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 32 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

FTM3_CH0/ Channel 0 E13 IO OV DD ---

XSPI1_A_DATA3 /
GPIO2_DAT27 /
LPUART3_SOUT

FTM3_CH1/ Channel 1 G11 IO OV DD ---

XSPI1_A_DATA0 /
GPIO2_DAT24 /
LPUART3_RTS_B

FTM3_CH2/ Channel 2 F12 IO OV DD ---

XSPI1_A_DATA1 /
GPIO2_DAT25 /
LPUART3_CTS_B

FTM3_EXTCLK/ External Clock H14 I OV DD 1

XSPI1_A_DATA2 /
GPIO2_DAT26 /
LPUART3_SIN

FTM4_CH0/ SDHC2_DAT7 / Channel 0 H22 IO OV DD ---

GPIO2_DAT18 /IIC8_SCL /
LPUART4_SOUT /
XSPI1_B_DATA7

FTM4_CH1/ SDHC2_DAT4 / Channel 1 G19 IO OV DD ---

GPIO2_DAT15 /IIC7_SDA /
LPUART4_RTS_B /
XSPI1_B_DATA4

FTM4_CH2/ SDHC2_DAT5 / Channel 2 D20 IO OV DD ---

GPIO2_DAT16 /IIC7_SCL /
LPUART4_CTS_B /
XSPI1_B_DATA5

FTM4_EXTCLK/ External Clock H20 I OV DD 1

SDHC2_DAT6 /
GPIO2_DAT17 /IIC8_SDA /
LPUART4_SIN /
XSPI1_B_DATA6

FTM5_CH0/ SDHC2_DAT3 / Channel 0 F18 IO OV DD 4

GPIO2_DAT14 /SPI2_PCS0 /
LPUART5_SOUT /
XSPI1_B_DATA3 /
cfg_gpinput7

FTM5_CH1/ SDHC2_DAT0 / Channel 1 E17 IO OV DD 4

GPIO2_DAT11 /SPI2_SIN /
LPUART5_RTS_B /
XSPI1_B_DATA0 /
cfg_gpinput4

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 33 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

FTM5_CH2/ SDHC2_DAT1 / Channel 2 D18 I OV DD 1, 4

GPIO2_DAT12 /SPI2_PCS2 /
LPUART5_CTS_B /
XSPI1_B_DATA1 /
cfg_gpinput5

FTM5_EXTCLK/ External Clock H18 I OV DD 1, 4

SDHC2_DAT2 /
GPIO2_DAT13 /SPI2_PCS1 /
LPUART5_SIN /
XSPI1_B_DATA2 /
cfg_gpinput6

FTM6_CH0/ UART1_SOUT / Channel 0 AB6 O OV DD 1, 4

GPIO1_DAT11 /
LPUART6_SOUT /
cfg_rcw_src1

FTM6_CH1/ UART2_SOUT / Channel 1 AC5 O OV DD 1, 4

GPIO1_DAT07 /
LPUART6_RTS_B /
cfg_rcw_src0

FTM6_CH2/ UART2_SIN / Channel 2 AD6 IO OV DD ---

GPIO1_DAT06 /
LPUART6_CTS_B

FTM6_EXTCLK/ External Clock AE7 I OV DD 1

UART1_SIN /GPIO1_DAT10 /
LPUART6_SIN

FTM7_CH0/ IIC3_SCL / Channel 0 V2 IO OV DD ---

GPIO1_DAT29 /CAN1_TX /
LPUART1_SOUT /EVT5_B

FTM7_CH1/ IIC4_SDA / Channel 1 T6 O OV DD 1

GPIO1_DAT26 /CAN2_RX /
LPUART1_RTS_B /EVT8_B

FTM7_CH2/ IIC4_SCL / Channel 2 U7 IO OV DD ---

GPIO1_DAT27 /CAN2_TX /
LPUART1_CTS_B /EVT7_B

FTM7_EXTCLK/ IIC3_SDA / External Clock U3 I OV DD 1

GPIO1_DAT28 /CAN1_RX /
LPUART1_SIN /EVT6_B

FTM8_CH0/ Channel 0 D12 O OV DD 1, 5

XSPI1_A_CS1_B /
GPIO2_DAT20 /cfg_svr1

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 34 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

FTM8_CH1/ Channel 1 H12 O OV DD 1, 4

XSPI1_A_CS0_B /
GPIO2_DAT21 /cfg_svr0

FTM8_CH2/ XSPI1_A_SCK / Channel 2 H10 O OV DD 1, 5

GPIO2_DAT22 /cfg_eng_use0

FTM8_EXTCLK/ External Clock F10 I OV DD 1

XSPI1_A_DQS /
GPIO2_DAT23

Controller Area Network

CAN1_RX/ IIC3_SDA / Receive Data U3 I OV DD 1

GPIO1_DAT28 /
LPUART1_SIN /
FTM7_EXTCLK /EVT6_B

CAN1_TX/ IIC3_SCL / Transmit Data V2 O OV DD 1

GPIO1_DAT29 /
LPUART1_SOUT /
FTM7_CH0 /EVT5_B

CAN2_RX/ IIC4_SDA / Receive Data T6 I OV DD 1

GPIO1_DAT26 /
LPUART1_RTS_B /
FTM7_CH1 /EVT8_B

CAN2_TX/ IIC4_SCL / Transmit Data U7 O OV DD 1

GPIO1_DAT27 /
LPUART1_CTS_B /
FTM7_CH2 /EVT7_B

Power-On-Reset Configuration

cfg_dram_type/ EMI1_MDC DRAM Select AK6 I OV DD 1, 4

cfg_eng_use0/ Power-on-Reset Configuration H10 I OV DD 1, 5

XSPI1_A_SCK /
GPIO2_DAT22 /FTM8_CH2

cfg_gpinput0/ SDHC1_DAT0 / General Input N3 I EV DD 1, 4

GPIO1_DAT17 /SPI1_SIN /
SAI2_TX_DATA /
SAI2_RX_DATA

cfg_gpinput1/ SDHC1_DAT1 / General Input P4 I EV DD 1, 4

GPIO1_DAT18 /SPI1_PCS2 /
SAI2_TX_BCLK /
SAI2_RX_BCLK

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 35 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

cfg_gpinput2/ SDHC1_DAT2 / General Input N1 I EV DD 1, 4

GPIO1_DAT19 /SPI1_PCS1 /
SAI1_TX_SYNC /
SAI1_RX_SYNC

cfg_gpinput3/ SDHC1_DAT3 / General Input L5 I EV DD 1, 4

GPIO1_DAT20 /SPI1_PCS0 /
SAI1_TX_DATA /
SAI1_RX_DATA

cfg_gpinput4/ SDHC2_DAT0 / General Input E17 I OV DD 1, 4

GPIO2_DAT11 /SPI2_SIN /
LPUART5_RTS_B /
FTM5_CH1 /XSPI1_B_DATA0

cfg_gpinput5/ SDHC2_DAT1 / General Input D18 I OV DD 1, 4

GPIO2_DAT12 /SPI2_PCS2 /
LPUART5_CTS_B /
FTM5_CH2 /XSPI1_B_DATA1

cfg_gpinput6/ SDHC2_DAT2 / General Input H18 I OV DD 1, 4

GPIO2_DAT13 /SPI2_PCS1 /
LPUART5_SIN /
FTM5_EXTCLK /
XSPI1_B_DATA2

cfg_gpinput7/ SDHC2_DAT3 / General Input F18 I OV DD 1, 4

GPIO2_DAT14 /SPI2_PCS0 /
LPUART5_SOUT /
FTM5_CH0 /XSPI1_B_DATA3

cfg_rcw_src0/ Reset Configuration Word AC5 I OV DD 1, 4

UART2_SOUT /
GPIO1_DAT07 /
LPUART6_RTS_B /
FTM6_CH1

cfg_rcw_src1/ Reset Configuration Word AB6 I OV DD 1, 4

UART1_SOUT /
GPIO1_DAT11 /
LPUART6_SOUT /FTM6_CH0

cfg_rcw_src2/ ASLEEP / Reset Configuration Word AA1 I OV DD 1, 4

GPIO2_DAT06 /EVT9_B

cfg_rcw_src3/ CLK_OUT / Reset Configuration Word AB4 I OV DD 1, 4

GPIO2_DAT07 /FTM1_CH1 /
EVT4_B

cfg_svr0/ XSPI1_A_CS0_B / Power-on-Reset Configuration H12 I OV DD 1, 4

GPIO2_DAT21 /FTM8_CH1

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 36 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

cfg_svr1/ XSPI1_A_CS1_B / Power-on-Reset Configuration D12 I OV DD 1, 5

GPIO2_DAT20 /FTM8_CH0

SPI1

SPI1_PCS0/ SDHC1_DAT3 / SPI Chip Select L5 IO EV DD 4

GPIO1_DAT20 /
SAI1_TX_DATA /
SAI1_RX_DATA /cfg_gpinput3

SPI1_PCS1/ SDHC1_DAT2 / SPI Chip Select N1 O EV DD 1, 4

GPIO1_DAT19 /
SAI1_TX_SYNC /
SAI1_RX_SYNC /
cfg_gpinput2

SPI1_PCS2/ SDHC1_DAT1 / SPI Chip Select P4 O EV DD 1, 4

GPIO1_DAT18 /
SAI2_TX_BCLK /
SAI2_RX_BCLK /cfg_gpinput1

SPI1_PCS3/ SDHC1_VSEL / SPI Chip Select M4 O OV DD 1

GPIO1_DAT15

SPI1_SCK/ SDHC1_CLK / Serial Clock M6 IO EV DD ---

GPIO1_DAT16 /
SAI2_TX_SYNC /
SAI2_RX_SYNC

SPI1_SIN/ SDHC1_DAT0 / Serial Data Input N3 I EV DD 1, 4

GPIO1_DAT17 /
SAI2_TX_DATA /
SAI2_RX_DATA /cfg_gpinput0

SPI1_SOUT/ SDHC1_CMD / Serial Data Output N7 O EV DD 1

GPIO1_DAT21 /
SAI1_TX_BCLK /
SAI1_RX_BCLK

SPI2

SPI2_PCS0/ SDHC2_DAT3 / SPI Chip Select F18 IO OV DD 4

GPIO2_DAT14 /
LPUART5_SOUT /
FTM5_CH0 /
XSPI1_B_DATA3 /
cfg_gpinput7

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 37 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SPI2_PCS1/ SDHC2_DAT2 / SPI Chip Select H18 O OV DD 1, 4

GPIO2_DAT13 /
LPUART5_SIN /
FTM5_EXTCLK /
XSPI1_B_DATA2 /
cfg_gpinput6

SPI2_PCS2/ SDHC2_DAT1 / SPI Chip Select D18 O OV DD 1, 4

GPIO2_DAT12 /
LPUART5_CTS_B /
FTM5_CH2 /
XSPI1_B_DATA1 /
cfg_gpinput5

SPI2_PCS3/ SDHC2_DS / SPI Chip Select B20 O OV DD 1

GPIO2_DAT10 /
XSPI1_B_DQS

SPI2_SCK/ SDHC2_CLK / Serial Clock F20 IO OV DD ---

GPIO2_DAT09 /
XSPI1_B_SCK

SPI2_SIN/ SDHC2_DAT0 / Serial Data Input E17 I OV DD 1, 4

GPIO2_DAT11 /
LPUART5_RTS_B /
FTM5_CH1 /
XSPI1_B_DATA0 /
cfg_gpinput4

SPI2_SOUT/ SDHC2_CMD / Serial Data Output G21 O OV DD 1

GPIO2_DAT19 /
XSPI1_B_CS1_B

SPI 3

SPI3_PCS0 /GPIO3_DAT15 / SPI Chip Select H6 O OV DD 1

EC1_1588_TRIG_IN2 /
SWITCH_1588_DAT2

SPI3_PCS1/ SPI Chip Select H8 O OV DD 1

USB_PWRFAULT /
GPIO3_DAT17

SPI3_PCS2/ SPI Chip Select G7 O OV DD 1

USB_DRVVBUS /
GPIO3_DAT18

SPI3_SCK /GPIO3_DAT14 / Serial Clock K6 O OV DD 1

EC1_1722_DAT3

SPI3_SIN /GPIO3_DAT13 / Serial Data Input K4 I OV DD 1

EC1_1722_DAT2

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 38 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SPI3_SOUT /GPIO3_DAT16 / Serial Data Output J5 O OV DD 1

EC1_1588_ALARM_OUT2 /
SWITCH_1588_DAT3

Ethernet Controller with 1588 Controller

EC1_1588_ALARM_OUT1/ Alarm Out AD4 O OV DD 1

EC1_TXD2 /GPIO3_DAT11 /
SAI4_TX_DATA /
SAI4_RX_DATA /FTM1_CH6

EC1_1588_ALARM_OUT2/ Alarm Out J5 O OV DD 1

SPI3_SOUT /GPIO3_DAT16 /
SWITCH_1588_DAT3

EC1_1588_CLK_IN/ Clock Input AD2 I OV DD 1

EC1_RX_CLK /
GPIO3_DAT01 /
SAI3_TX_SYNC /
SAI3_RX_SYNC /
FTM1_QD_PHA

EC1_1588_CLK_OUT/ Clock Out AF4 O OV DD 1

EC1_TXD1 /GPIO3_DAT10 /
SAI3_TX_DATA /
SAI3_RX_DATA /FTM1_CH5

EC1_1588_PULSE_OUT1/ Pulse Out AG5 O OV DD 1

EC1_TXD3 /GPIO3_DAT12 /
SAI5_TX_DATA /
SAI5_RX_DATA /FTM1_CH7

EC1_1588_PULSE_OUT2/ Pulse Out AF6 O OV DD 1

EC1_TXD0 /GPIO3_DAT09 /
SAI6_TX_DATA /
SAI6_RX_DATA /FTM1_CH4

EC1_1588_TRIG_IN1/ Trigger In AH2 I OV DD 1

EC1_RX_DV /
GPIO3_DAT00 /
SAI6_TX_SYNC /
SAI6_RX_SYNC /
FTM1_QD_PHB

EC1_1588_TRIG_IN2/ Trigger In H6 I OV DD 1
SPI3_PCS0 /GPIO3_DAT15 /
SWITCH_1588_DAT2

LPUART

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 39 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

LPUART1_CTS_B/ Clear To Send U7 I OV DD 1

IIC4_SCL /GPIO1_DAT27 /
CAN2_TX /FTM7_CH2 /
EVT7_B

LPUART1_RTS_B/ Request To Send T6 O OV DD 1

IIC4_SDA /GPIO1_DAT26 /
CAN2_RX /FTM7_CH1 /
EVT8_B

LPUART1_SIN/ IIC3_SDA / Receive Data U3 I OV DD 1

GPIO1_DAT28 /CAN1_RX /
FTM7_EXTCLK /EVT6_B

LPUART1_SOUT/ IIC3_SCL / Transmit Data V2 IO OV DD ---

GPIO1_DAT29 /CAN1_TX /
FTM7_CH0 /EVT5_B

LPUART2_CTS_B/ Clear To Send D14 I OV DD 1

XSPI1_A_DATA5 /
GPIO2_DAT29 /FTM2_CH2

LPUART2_RTS_B/ Request To Send F14 O OV DD 1

XSPI1_A_DATA4 /
GPIO2_DAT28 /FTM2_CH1

LPUART2_SIN/ Receive Data D16 I OV DD 1

XSPI1_A_DATA6 /
GPIO2_DAT30 /
FTM2_EXTCLK

LPUART2_SOUT/ Transmit Data G15 IO OV DD ---

XSPI1_A_DATA7 /
GPIO2_DAT31

LPUART3_CTS_B/ Clear To Send F12 I OV DD 1

XSPI1_A_DATA1 /
GPIO2_DAT25 /FTM3_CH2

LPUART3_RTS_B/ Request To Send G11 O OV DD 1

XSPI1_A_DATA0 /
GPIO2_DAT24 /FTM3_CH1

LPUART3_SIN/ Receive Data H14 I OV DD 1

XSPI1_A_DATA2 /
GPIO2_DAT26 /
FTM3_EXTCLK

LPUART3_SOUT/ Transmit Data E13 IO OV DD ---

XSPI1_A_DATA3 /
GPIO2_DAT27 /FTM3_CH0

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 40 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

LPUART4_CTS_B/ Clear To Send D20 I OV DD 1

SDHC2_DAT5 /
GPIO2_DAT16 /IIC7_SCL /
FTM4_CH2 /XSPI1_B_DATA5

LPUART4_RTS_B/ Request To Send G19 O OV DD 1

SDHC2_DAT4 /
GPIO2_DAT15 /IIC7_SDA /
FTM4_CH1 /XSPI1_B_DATA4

LPUART4_SIN/ Receive Data H20 I OV DD 1

SDHC2_DAT6 /
GPIO2_DAT17 /IIC8_SDA /
FTM4_EXTCLK /
XSPI1_B_DATA6

LPUART4_SOUT/ Transmit Data H22 IO OV DD ---

SDHC2_DAT7 /
GPIO2_DAT18 /IIC8_SCL /
FTM4_CH0 /XSPI1_B_DATA7

LPUART5_CTS_B/ Clear To Send D18 I OV DD 1, 4

SDHC2_DAT1 /
GPIO2_DAT12 /SPI2_PCS2 /
FTM5_CH2 /
XSPI1_B_DATA1 /
cfg_gpinput5

LPUART5_RTS_B/ Request To Send E17 O OV DD 1, 4

SDHC2_DAT0 /
GPIO2_DAT11 /SPI2_SIN /
FTM5_CH1 /
XSPI1_B_DATA0 /
cfg_gpinput4

LPUART5_SIN/ Receive Data H18 I OV DD 1, 4

SDHC2_DAT2 /
GPIO2_DAT13 /SPI2_PCS1 /
FTM5_EXTCLK /
XSPI1_B_DATA2 /
cfg_gpinput6

LPUART5_SOUT/ Transmit Data F18 IO OV DD 4

SDHC2_DAT3 /
GPIO2_DAT14 /SPI2_PCS0 /
FTM5_CH0 /
XSPI1_B_DATA3 /
cfg_gpinput7

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 41 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

LPUART6_CTS_B/ Clear To Send AD6 I OV DD 1

UART2_SIN /GPIO1_DAT06 /
FTM6_CH2

LPUART6_RTS_B/ Request To Send AC5 O OV DD 1, 4

UART2_SOUT /
GPIO1_DAT07 /FTM6_CH1 /
cfg_rcw_src0

LPUART6_SIN/ UART1_SIN / Receive Data AE7 I OV DD 1

GPIO1_DAT10 /
FTM6_EXTCLK

LPUART6_SOUT/ Transmit Data AB6 O OV DD 1, 4

UART1_SOUT /
GPIO1_DAT11 /FTM6_CH0 /
cfg_rcw_src1

USB

USB2_DRVVBUS/ IIC6_SDA / DR VBUS H16 O OV DD 1

GPIO1_DAT22 /
SDHC2_CLK_SYNC_IN /
EVT0_B

USB2_PWRFAULT/ Power Fault F16 I OV DD 1

IIC6_SCL /GPIO1_DAT23 /
SDHC2_CLK_SYNC_OUT /
EVT3_B

Synchronous Audio Interfaces

SAI1_RX_BCLK/ Receive Clock N7 I EV DD 1

SDHC1_CMD /
GPIO1_DAT21 /SPI1_SOUT /
SAI1_TX_BCLK

SAI1_RX_DATA/ Receiev Data L5 I EV DD 1, 4

SDHC1_DAT3 /
GPIO1_DAT20 /SPI1_PCS0 /
SAI1_TX_DATA /cfg_gpinput3

SAI1_RX_SYNC/ Receive Sync N1 IO EV DD 4

SDHC1_DAT2 /
GPIO1_DAT19 /SPI1_PCS1 /
SAI1_TX_SYNC /cfg_gpinput2

SAI1_TX_BCLK/ Transmit Clock N7 I EV DD 1

SDHC1_CMD /
GPIO1_DAT21 /SPI1_SOUT /
SAI1_RX_BCLK

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 42 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SAI1_TX_DATA/ Transmit Data L5 O EV DD 1, 4

SDHC1_DAT3 /
GPIO1_DAT20 /SPI1_PCS0 /
SAI1_RX_DATA /cfg_gpinput3

SAI1_TX_SYNC/ Transmit Sync N1 IO EV DD 4

SDHC1_DAT2 /
GPIO1_DAT19 /SPI1_PCS1 /
SAI1_RX_SYNC /
cfg_gpinput2

SAI2_RX_BCLK/ Receive Clock P4 I EV DD 1, 4

SDHC1_DAT1 /
GPIO1_DAT18 /SPI1_PCS2 /
SAI2_TX_BCLK /cfg_gpinput1

SAI2_RX_DATA/ Receiev Data N3 I EV DD 1, 4

SDHC1_DAT0 /
GPIO1_DAT17 /SPI1_SIN /
SAI2_TX_DATA /cfg_gpinput0

SAI2_RX_SYNC/ Receive Sync M6 IO EV DD ---

SDHC1_CLK /
GPIO1_DAT16 /SPI1_SCK /
SAI2_TX_SYNC

SAI2_TX_BCLK/ Transmit Clock P4 I EV DD 1, 4

SDHC1_DAT1 /
GPIO1_DAT18 /SPI1_PCS2 /
SAI2_RX_BCLK /cfg_gpinput1

SAI2_TX_DATA/ Transmit Data N3 O EV DD 1, 4

SDHC1_DAT0 /
GPIO1_DAT17 /SPI1_SIN /
SAI2_RX_DATA /cfg_gpinput0

SAI2_TX_SYNC/ Transmit Sync M6 IO EV DD ---

SDHC1_CLK /
GPIO1_DAT16 /SPI1_SCK /
SAI2_RX_SYNC

SAI3_RX_BCLK/ EC1_RXD1 / Receive Clock AF2 I OV DD 1

GPIO3_DAT03 /
SAI3_TX_BCLK

SAI3_RX_DATA/ EC1_TXD1 / Receiev Data AF4 I OV DD 1

GPIO3_DAT10 /
SAI3_TX_DATA /FTM1_CH5 /
EC1_1588_CLK_OUT

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 43 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SAI3_RX_SYNC/ Receive Sync AD2 IO OV DD ---

EC1_RX_CLK /
GPIO3_DAT01 /
SAI3_TX_SYNC /
FTM1_QD_PHA /
EC1_1588_CLK_IN

SAI3_TX_BCLK/ EC1_RXD1 / Transmit Clock AF2 I OV DD 1

GPIO3_DAT03 /
SAI3_RX_BCLK

SAI3_TX_DATA/ EC1_TXD1 / Transmit Data AF4 O OV DD 1

GPIO3_DAT10 /
SAI3_RX_DATA /FTM1_CH5 /
EC1_1588_CLK_OUT

SAI3_TX_SYNC/ Transmit Sync AD2 IO OV DD ---

EC1_RX_CLK /
GPIO3_DAT01 /
SAI3_RX_SYNC /
FTM1_QD_PHA /
EC1_1588_CLK_IN

SAI4_RX_BCLK/ EC1_RXD2 / Receive Clock AE3 I OV DD 1

GPIO3_DAT04 /
SAI4_TX_BCLK /FTM1_CH2

SAI4_RX_DATA/ EC1_TXD2 / Receiev Data AD4 I OV DD 1

GPIO3_DAT11 /
SAI4_TX_DATA /FTM1_CH6 /
EC1_1588_ALARM_OUT1

SAI4_RX_SYNC/ Receive Sync AH4 IO OV DD ---

EC1_GTX_CLK /
GPIO3_DAT07 /
SAI4_TX_SYNC /
FTM1_EXTCLK /
SWITCH_1588_DAT0

SAI4_TX_BCLK/ EC1_RXD2 / Transmit Clock AE3 I OV DD 1

GPIO3_DAT04 /
SAI4_RX_BCLK /FTM1_CH2

SAI4_TX_DATA/ EC1_TXD2 / Transmit Data AD4 O OV DD 1

GPIO3_DAT11 /
SAI4_RX_DATA /FTM1_CH6 /
EC1_1588_ALARM_OUT1

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 44 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SAI4_TX_SYNC/ Transmit Sync AH4 IO OV DD ---

EC1_GTX_CLK /
GPIO3_DAT07 /
SAI4_RX_SYNC /
FTM1_EXTCLK /
SWITCH_1588_DAT0

SAI5_RX_BCLK/ EC1_RXD3 / Receive Clock AE1 I OV DD 1

GPIO3_DAT05 /
SAI5_TX_BCLK /FTM1_CH3 /
EC1_1722_DAT1

SAI5_RX_DATA/ EC1_TXD3 / Receiev Data AG5 I OV DD 1

GPIO3_DAT12 /
SAI5_TX_DATA /FTM1_CH7 /
EC1_1588_PULSE_OUT1

SAI5_RX_SYNC/ Receive Sync AJ3 IO OV DD ---

EC1_TX_EN /GPIO3_DAT08 /
SAI5_TX_SYNC /
FTM1_FAULT /
SWITCH_1588_DAT1

SAI5_TX_BCLK/ EC1_RXD3 / Transmit Clock AE1 I OV DD 1

GPIO3_DAT05 /
SAI5_RX_BCLK /FTM1_CH3 /
EC1_1722_DAT1

SAI5_TX_DATA/ EC1_TXD3 / Transmit Data AG5 O OV DD 1

GPIO3_DAT12 /
SAI5_RX_DATA /FTM1_CH7 /
EC1_1588_PULSE_OUT1

SAI5_TX_SYNC/ Transmit Sync AJ3 IO OV DD ---

EC1_TX_EN /GPIO3_DAT08 /
SAI5_RX_SYNC /
FTM1_FAULT /
SWITCH_1588_DAT1

SAI6_RX_BCLK/ EC1_RXD0 / Receive Clock AG1 I OV DD 1

GPIO3_DAT02 /
SAI6_TX_BCLK

SAI6_RX_DATA/ EC1_TXD0 / Receiev Data AF6 I OV DD 1

GPIO3_DAT09 /
SAI6_TX_DATA /FTM1_CH4 /
EC1_1588_PULSE_OUT2

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 45 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SAI6_RX_SYNC/ Receive Sync AH2 IO OV DD ---

EC1_RX_DV /
GPIO3_DAT00 /
SAI6_TX_SYNC /
FTM1_QD_PHB /
EC1_1588_TRIG_IN1

SAI6_TX_BCLK/ EC1_RXD0 / Transmit Clock AG1 I OV DD 1

GPIO3_DAT02 /
SAI6_RX_BCLK

SAI6_TX_DATA/ EC1_TXD0 / Transmit Data AF6 O OV DD 1

GPIO3_DAT09 /
SAI6_RX_DATA /FTM1_CH4 /
EC1_1588_PULSE_OUT2

SAI6_TX_SYNC/ Transmit Sync AH2 IO OV DD ---

EC1_RX_DV /
GPIO3_DAT00 /
SAI6_RX_SYNC /
FTM1_QD_PHB /
EC1_1588_TRIG_IN1

USB PHY 1 and 2

USB1_D_M USB PHY Data Minus D2 IO - ---

USB1_D_P USB PHY Data Plus E1 IO - ---

USB1_ID USB PHY ID Detect D4 I - ---

USB1_RESREF USB PHY Impedance F4 IO - 18

Calibration

USB1_RX_M USB PHY 3.0 Receive Data K2 I - ---

(negative)

USB1_RX_P USB PHY 3.0 Receive Data L1 I - ---

(positive)

USB1_TX_M USB PHY 3.0 Transmit Data G1 O - ---

(negative)

USB1_TX_P USB PHY 3.0 Transmit Data H2 O - ---

(positive)

USB1_VBUS USB PHY VBUS H4 I - ---

USB2_D_M USB PHY Data Minus B8 IO - ---

USB2_D_P USB PHY Data Plus A7 IO - ---

USB2_ID USB PHY ID Detect E5 I - ---

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 46 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

USB2_RESREF USB PHY Impedance F6 IO - 18

Calibration

USB2_RX_M USB PHY 3.0 Receive Data A3 I - ---

(negative)

USB2_RX_P USB PHY 3.0 Receive Data B2 I - ---

(positive)

USB2_TX_M USB PHY 3.0 Transmit Data B6 O - ---

(negative)

USB2_TX_P USB PHY 3.0 Transmit Data A5 O - ---

(positive)

USB2_VBUS USB PHY VBUS D6 I - ---

USB_DRVVBUS / USB PHY Digital signal - Drive G7 O OV DD 1

GPIO3_DAT18 /SPI3_PCS2 VBUS

USB_PWRFAULT / USB PHY Digital signal - H8 I OV DD 1

GPIO3_DAT17 /SPI3_PCS1 Power Fault

IEEE 1588 signals

SWITCH_1588_DAT0/ IEEE 1588 signals AH4 IO OV DD ---

EC1_GTX_CLK /
GPIO3_DAT07 /
SAI4_TX_SYNC /
SAI4_RX_SYNC /
FTM1_EXTCLK

SWITCH_1588_DAT1/ IEEE 1588 signals AJ3 IO OV DD ---

EC1_TX_EN /GPIO3_DAT08 /
SAI5_TX_SYNC /
SAI5_RX_SYNC /
FTM1_FAULT

SWITCH_1588_DAT2/ IEEE 1588 signals H6 IO OV DD ---

SPI3_PCS0 /GPIO3_DAT15 /
EC1_1588_TRIG_IN2

SWITCH_1588_DAT3/ IEEE 1588 signals J5 IO OV DD ---

SPI3_SOUT /GPIO3_DAT16 /
EC1_1588_ALARM_OUT2

IEEE 1722 signals

EC1_1722_DAT0/ IEEE 1722 signals AK2 IO OV DD ---

EC1_GTX_CLK125 /
GPIO3_DAT06

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 47 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

EC1_1722_DAT1/ IEEE 1722 signals AE1 IO OV DD ---

EC1_RXD3 /GPIO3_DAT05 /
SAI5_TX_BCLK /
SAI5_RX_BCLK /FTM1_CH3

EC1_1722_DAT2/ SPI3_SIN / IEEE 1722 signals K4 IO OV DD ---

GPIO3_DAT13

EC1_1722_DAT3/ IEEE 1722 signals K6 IO OV DD ---

SPI3_SCK /GPIO3_DAT14

Display

DP_AUX_N Auxillary port (negative) A19 IO DP_SV DD ---

DP_AUX_P Auxillary port (positive) B18 IO DP_SV DD ---

DP_HPD Hot plug detect F8 I DP_OV DD 24

DP_LANE0_N Data lane (negative) A11 O DP_SV DD ---

DP_LANE0_P Data lane (positive) B10 O DP_SV DD ---

DP_LANE1_N Data lane (negative) A13 O DP_SV DD ---

DP_LANE1_P Data lane (positive) B12 O DP_SV DD ---

DP_LANE2_N Data lane (negative) A15 O DP_SV DD ---

DP_LANE2_P Data lane (positive) B14 O DP_SV DD ---

DP_LANE3_N Data lane (negative) A17 O DP_SV DD ---

DP_LANE3_P Data lane (positive) B16 O DP_SV DD ---

Data Sheet: Technical Data 48 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 49 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 50 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 51 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 52 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 53 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND100 Core, Platform and PLL AJ1 --- --- ---

Ground

GND101 Core, Platform and PLL AJ5 --- --- ---

Ground

GND102 Core, Platform and PLL AK8 --- --- ---

Ground

SD_GND01 SerDes1 core logic ground AB16 --- --- 20

SD_GND02 SerDes1 core logic ground AB18 --- --- 20

SD_GND03 SerDes1 core logic ground AB20 --- --- 20

SD_GND04 SerDes1 core logic ground AC21 --- --- 20

SD_GND05 SerDes1 core logic ground AE11 --- --- 20

SD_GND06 SerDes1 core logic ground AE13 --- --- 20

SD_GND07 SerDes1 core logic ground AE15 --- --- 20

SD_GND08 SerDes1 core logic ground AE17 --- --- 20

SD_GND09 SerDes1 core logic ground AE19 --- --- 20

SD_GND10 SerDes1 core logic ground AF20 --- --- 20

SD_GND11 SerDes1 core logic ground AG11 --- --- 20

SD_GND12 SerDes1 core logic ground AH10 --- --- 20

SD_GND13 SerDes1 core logic ground AH12 --- --- 20

SD_GND14 SerDes1 core logic ground AH14 --- --- 20

SD_GND15 SerDes1 core logic ground AH16 --- --- 20

SD_GND16 SerDes1 core logic ground AH18 --- --- 20

SD_GND17 SerDes1 core logic ground AH20 --- --- 20

SD_GND18 SerDes1 core logic ground AJ9 --- --- 20

SD_GND19 SerDes1 core logic ground AK18 --- --- 20

SENSEGND Ground Sense pin AG7 --- --- ---

OVDD1 General I/O supply J17 --- OV DD ---

OVDD2 General I/O supply K18 --- OV DD ---

OVDD3 General I/O supply T8 --- OV DD ---

OVDD4 General I/O supply V8 --- OV DD ---

G1VDD01 DDR supply K24 --- G1V DD ---

G1VDD02 DDR supply M24 --- G1V DD ---

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 54 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

G1VDD03 DDR supply N23 --- G1V DD ---

G1VDD04 DDR supply R23 --- G1V DD ---

G1VDD05 DDR supply U23 --- G1V DD ---

G1VDD06 DDR supply V24 --- G1V DD ---

G1VDD07 DDR supply W23 --- G1V DD ---

G1VDD08 DDR supply AA25 --- G1V DD ---

G1VDD09 DDR supply AA29 --- G1V DD ---

G1VDD10 DDR supply AC27 --- G1V DD ---

G1VDD11 DDR supply AE21 --- G1V DD ---

G1VDD12 DDR supply AE25 --- G1V DD ---

G1VDD13 DDR supply AE29 --- G1V DD ---

G1VDD14 DDR supply AG23 --- G1V DD ---

G1VDD15 DDR supply AG27 --- G1V DD ---

G1VDD16 DDR supply AH30 --- G1V DD ---

G1VDD17 DDR supply AJ21 --- G1V DD ---

G1VDD18 DDR supply AJ25 --- G1V DD ---

G1VDD19 DDR supply AK28 --- G1V DD ---

EVDD eSDHC supply - switchable P8 --- EV DD ---

SVDD1 SerDes core logic supply AA15 --- SV DD ---

SVDD2 SerDes core logic supply AA17 --- SV DD ---

SVDD3 SerDes core logic supply AA19 --- SV DD ---

SVDD4 SerDes core logic supply AB14 --- SV DD ---

XVDD1 SerDes transceiver supply AC15 --- XV DD ---

XVDD2 SerDes transceiver supply AC17 --- XV DD ---

XVDD3 SerDes transceiver supply AC19 --- XV DD ---

FA_VL Internal Use Only A29 --- FA_VL 15

PROG_MTR Internal Use Only J13 --- PROG_MTR 15

TA_PROG_SFP SFP Fuse Programming J15 --- TA_PROG_SFP ---

Override supply

TH_VDD Thermal Monitor Unit supply R7 --- TH_V DD ---

VDD01 Supply for cores and platform K14 --- V DD ---

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 55 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

VDD02 Supply for cores and platform L13 --- V DD ---

VDD03 Supply for cores and platform L17 --- V DD ---

VDD04 Supply for cores and platform L21 --- V DD ---

VDD05 Supply for cores and platform L23 --- V DD ---

VDD06 Supply for cores and platform M8 --- V DD ---

VDD07 Supply for cores and platform M10 --- V DD ---

VDD08 Supply for cores and platform M12 --- V DD ---

VDD09 Supply for cores and platform M16 --- V DD ---

VDD10 Supply for cores and platform N11 --- V DD ---

VDD11 Supply for cores and platform N15 --- V DD ---

VDD12 Supply for cores and platform N19 --- V DD ---

VDD13 Supply for cores and platform N21 --- V DD ---

VDD14 Supply for cores and platform P10 --- V DD ---

VDD15 Supply for cores and platform P14 --- V DD ---

VDD16 Supply for cores and platform P18 --- V DD ---

VDD17 Supply for cores and platform R9 --- V DD ---

VDD18 Supply for cores and platform R13 --- V DD ---

VDD19 Supply for cores and platform R17 --- V DD ---

VDD20 Supply for cores and platform R21 --- V DD ---

VDD21 Supply for cores and platform T12 --- V DD ---

VDD22 Supply for cores and platform T16 --- V DD ---

VDD23 Supply for cores and platform T20 --- V DD ---

VDD24 Supply for cores and platform U11 --- V DD ---

VDD25 Supply for cores and platform U15 --- V DD ---

VDD26 Supply for cores and platform U19 --- V DD ---

VDD27 Supply for cores and platform U21 --- V DD ---

VDD28 Supply for cores and platform V10 --- V DD ---

VDD29 Supply for cores and platform V14 --- V DD ---

VDD30 Supply for cores and platform V18 --- V DD ---

VDD31 Supply for cores and platform W9 --- V DD ---

VDD32 Supply for cores and platform W13 --- V DD ---

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 56 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

VDD33 Supply for cores and platform W17 --- V DD ---

VDD34 Supply for cores and platform W21 --- V DD ---

VDD35 Supply for cores and platform Y8 --- V DD ---

VDD36 Supply for cores and platform Y12 --- V DD ---

VDD37 Supply for cores and platform Y16 --- V DD ---

VDD38 Supply for cores and platform Y20 --- V DD ---

VDD39 Supply for cores and platform AA11 --- V DD ---

VDD40 Supply for cores and platform AA21 --- V DD ---

TA_BB_VDD Low Power Security Monitor AD12 --- TA_BB_V DD ---

supply

PIXEL_DVDD Pixel Clock PLL digital supply M20 --- PIXEL_DV DD ---

AVDD_CGA1 A72 Core Cluster Group A AC9 --- AVDD_CGA1 ---

PLL1 supply

AVDD_CGA2 A72 Core Cluster Group A AB10 --- AVDD_CGA2 ---

PLL2 supply

AVDD_PLAT Platform PLL supply AB8 --- AVDD_PLAT ---

AVDD_D1 DDR1 PLL supply T24 --- AVDD_D1 ---

AVDD_PIXEL Pixel Clock PLL analog supply AC13 --- AVDD_PIXEL ---

AVDD_SD1_PLL1 SerDes1 PLL 1 supply AD16 --- AVDD_SD1_PLL1 ---

AVDD_SD1_PLL2 SerDes1 PLL 2 supply AD18 --- AVDD_SD1_PLL2 ---

USB_HVDD1 USB PHY 3.3V Analog and J9 --- USB_HV DD ---

Digital supply HS

USB_HVDD2 USB PHY 3.3V Analog and J11 --- USB_HV DD ---
Digital supply HS

USB_SDVDD1 USB PHY 1.0/0.9V Analog J7 --- USB_SDV DD ---

and Digital HS

USB_SDVDD2 USB PHY 1.0/0.9V Analog K8 --- USB_SDV DD ---

and Digital HS

USB_SVDD1 USB PHY 1.0/0.9V Analog K10 --- USB_SV DD ---

and Digital SS

USB_SVDD2 USB PHY 1.0/0.9V Analog K12 --- USB_SV DD ---

and Digital SS

DP_OVDD PMA 1.8V common I/O supply J19 --- DP_OV DD ---

DP_SVDD PMA transmit core supply K22 --- DP_SV DD ---

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 57 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

DP_AVDD PMA common core supply K20 --- DP_AV DD ---

SENSEVDD VDD Sense pin AF8 --- SENSEV DD ---

Table continues on the next page...

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 58 / 184
NXP Semiconductors
Pin assignments

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

1. Functionally, this pin is an output or an input, but structurally it is an I/O because it either sample configuration input
during reset, is a muxed pin, or has other manufacturing test functions. This pin will therefore be described as an I/O for
boundary scan.
2. This output is actively driven during reset rather than being tri-stated during reset.
3. MDIC[0] is grounded through an 237Ω precision 1% resistor and MDIC[1] is connected to GV DD through an 237Ω
precision 1% resistor. For either full or half driver strength calibration of DDR IOs, use the same MDIC resistor value of
237Ω. Memory controller register setting can be used to determine automatic calibration is done to full or half drive strength.
These pins are used for automatic calibration of the DDR3/DDR3L IOs. The MDIC[0:1] pins must be connected to 237Ω
precision 1% resistors. MDIC[0] is grounded through a 162Ω precision 1% resistor and MDIC[1] is connected to GV DD
through a 162Ω precision 1% resistor. For either full or half driver strength calibration of DDR IOs, use the same MDIC
resistor value of 162Ω. The memory controller register setting can be used to determine automatic calibration is done to
full or half drive strength. These pins are used for automatic calibration of the DDR IOs. The MDIC[0:1] pins must be
connected to 162Ω precision 1% resistors.
4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor
is in its reset state. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net
at reset, a pull-up or active driver is needed.
5. Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or if there are any externally
connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external pull-up is
required to drive this pin to a safe state during reset.
6. Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the respective power supply.
7. This pin is an open-drain signal.
8. Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply.
9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.
10. These are test signals for factory use only and must be pulled up (100Ω to 1-kΩ) to the respective power supply for
normal operation.
11. This pin requires a 200Ω ± 1% pull-up to respective power-supply.
14.This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is
actively driven.
15. These pins must be pulled to ground (GND).
16. This pin requires a 698Ω ± 1% pull-up to respective power-supply.
17. These pins should be tied to ground if the diode is not utilized for temperature monitoring.
18. This pin should be grounded through a 200Ω ± 1% 100-ppm/ 0C precision resistor.
19. In normal operation, this pin must be pulled high to OVDD with 1 kΩ.
20. SD_GND must be directly connected to GND.
21. This pin will not be tested using JTAG Boundary Scan operation.
22. This pin must be pulled to OVDD through a 100Ω to 1kΩ resistor.
23. PORESET_B should be asserted zero during the JTAG Boundary Scan Operation, and is required to be controllable
on board.

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NXP Semiconductors
Electrical characteristics

Table 1. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

24. This pin requires an external 1-MΩ pull-down resistor.

25. This pin requires an external 499Ω ± 1% pull-down resistor.
26. Recommend that a weak pull-up resistor (10-100 kΩ) be placed on this pin to the respective power supply.
27. This pin requires a pull-up to the respective power supply so as to meet the timing requirements in Table 13. RESET
initialization timing specifications on page 75.

Warning
See "Connection Recommendations"in QorIQ LS1028A Design Checklist (AN12028)" for additional details on
properly connecting these pins for specific applications.

3 Electrical characteristics
This section describes the DC and AC electrical specifications for the chip. The chip is currently targeted to these specifications,
some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer
design specifications.

3.1 Overall DC electrical characteristics

This section describes the ratings, conditions, and other characteristics.

3.1.1 Absolute maximum ratings

This table provides the absolute maximum ratings

Table 2. Absolute maximum ratings 6, 7

Characteristic Symbol Min Max Value Unit Notes

Core and platform supply voltage VDD -0.3 1.08 V 1

Core PLL supply voltage AVDD_CGA1 -0.3 1.98 V -

Core PLL supply voltage AVDD_CGA2 -0.3 1.98 V -

Platform PLL supply voltage AVDD_PLAT -0.3 1.98 V -

DDR PLL supply voltage AVDD_D1 -0.3 1.98 V -

PLL supply voltage (SerDes, filtered AVDD_SD1_PLL1 -0.3 1.48 V -

from XVDD)

PLL supply voltage (SerDes, filtered AVDD_SD1_PLL2 -0.3 1.48 V -

from XVDD)

SFP fuse programming TA_PROG_SFP -0.3 1.98 V -

Table continues on the next page...

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Electrical characteristics

Table 2. Absolute maximum ratings 6, 7 (continued)

Characteristic Symbol Min Max Value Unit Notes

Thermal monitor unity supply TH_VDD -0.3 1.98 V -

SPI2/3, FlexSPI, Tamper_Detect, OVDD -0.3 1.98 V -

System control, GPIO1/2/3, I2C,
eSDHC2, SDHC1_VSEL, Ethernet
interface, Ethernet management
interface (EMI), TSEC_1588, DUART,
Debug, JTAG, POR signals, DFT,
USB_PWRFAULT, USB_DRVVBUS,
SAI3/4/5/6, Flextimer, CAN, LPUART

DDR3L DRAM I/O voltage G1VDD -0.3 1.42 V -

DDR4 DRAM I/O voltage G1VDD -0.3 1.26 V -

Pixel clock PLL digital supply PIXEL_DVDD -0.3 1.08 V -

Pixel clock PLL analog supply AVDD_PIXEL -0.3 1.98 V -

PMA common I/O supply DP_OVDD -0.3 1.98 V -

PMA transmit supply DP_SVDD -0.3 1.08 V -

PMA common core supply DP_AVDD -0.3 1.08 V -

eSDHC1 EVDD -0.3 3.63 V 8

eSDHC1, SPI1, SAI1/2 EVDD -0.3 1.98 V 9

Main power supply for internal circuitry SVDD -0.3 1.08 V -

of SerDes and pad power supply for
SerDes receivers and DIFF_SYSCLK

Pad power supply for SerDes XVDD -0.3 1.48 V -

transmitter

USB PHY 3.3V high supply voltage USB_HVDD -0.3 3.63 V 2

USB PHY analog and digital HS supply USB_SDVDD -0.3 1.08 V -

USB PHY analog and digital SS supply USB_SVDD -0.3 1.08 V -

voltage

Battery Backed Security Monitor supply TA_BB_VDD -0.3 1.08 V -

Input voltage for DDR4 and DDR3L GVIN -0.3 G1VDD x 1.05 V 3, 4
DRAM signals

Input voltage for DDR3L DRAM MVREF -0.3 G1VDD/2 x 1.05 V 3, 5

reference

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 2. Absolute maximum ratings 6, 7 (continued)

Characteristic Symbol Min Max Value Unit Notes

SPI2/3, FlexSPI, Tamper_Detect, OVIN -0.3 OVDD x 1.1 V 3, 5

eSDHC1, SPI1, SAI1/2 EVIN -0.3 EVDD x 1.1 V 3, 5

Input voltage for main power supply for SVIN -0.3 SVDD x 1.05 V 5
internal circuitry of SerDes and
DIFF_SYSCLK

PHY transceiver signals: USB USB_HVIN -0.3 USB_HVDD x 1.05 V -

transceiver supply for USB PHY

PHY transceiver signals: USB PHY USB_SVIN -0.3 USB_SVDD x 1.1 V -

Analog and Digital SS supply voltage

PHY transceiver signals: USB PHY USB_SDVIN -0.3 USB_SDVDD x 1.1 V -

Analog and Digital HS supply voltage

Storage temperature range TSTG -55 150 °C -

1. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
2. Transceiver supply for USB PHY.
3. Caution: The input voltage level of the signals must not exceed corresponding Max value. For example DDR4 must not
exceed 5% of G1VDD.
4. Typical DDR interface uses ODT enabled mode. For tests purposes with ODT off mode, simulation should be done first so
as to make sure that the overshoot signal level at the input pin does not exceed GVDD by more than 10%. The Overshoot/
Undershoot period should comply with JEDEC standards.
5. (G1, O, S, E)VIN, USB_S*VIN and USB_HVIN may overshoot/undershoot to a voltage and for a maximum duration as shown
in the Overshoot/undershoot voltage figure at the end of this section.
6. Functional operating conditions are given in Recommended operating conditions table. Absolute maximum ratings are stress
ratings only, and functional operations at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damange to the device.
7. Exposing device to Absolute Maximum Ratings conditions for long periods of time may affect reliability or cause permanent
damage.
8. When EVDD is powered with 3.3V supply.
9. When EVDD is powered with 1.8V supply.

3.1.2 Recommended Operating Conditions

This table provides the recommended operating conditions for this chip.

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NXP Semiconductors
Electrical characteristics

WARNING
The values shown are the recommended operating conditions and proper device operation outside these
conditions is not guaranteed.

Table 3. Recommended operating conditions

Parameter Symbol Min Typ Max Unit Notes

Core and platform supply voltage VDD 1.0 V - 30 mV 1.0 1.0 V + 30 mV V 1, 2, 3, 4

0.9V core and platform supply VDD 0.9 V - 30 mV 0.9 0.9 V + 30 mV V 1, 2, 3, 4

voltage

Core PLL supply voltage AVDD_CGA1 1.8 V - 90 mV 1.8 1.8 V + 90 mV V 5

Core PLL supply voltage AVDD_CGA2 1.8 V - 90 mV 1.8 1.8 V + 90 mV V 5

Platform PLL supply voltage AVDD_PLAT 1.8 V - 90 mV 1.8 1.8 V + 90 mV V 5

DDR PLL supply voltage AVDD_D1 1.8 V - 90 mV 1.8 1.8 V + 90 mV V 5

PLL supply voltage (SerDes, AVDD_SD1_PLL1 1.35 V - 67 mV 1.35 1.35 V + 67 mV V -

filtered from XVDD)

PLL supply voltage (SerDes, AVDD_SD1_PLL2 1.35 V - 67 mV 1.35 1.35 V + 67 mV V -

filtered from XVDD)

SFP fuse programming TA_PROG_SFP 1.8 V - 90 mV 1.8 1.8 V + 90 mV V 6

Thermal monitor unity supply TH_VDD 1.8 V - 90 mV 1.8 1.8 V + 90 mV V -

SPI2/3, FlexSPI, Tamper_Detect, OVDD 1.8 V - 90 mV 1.8 1.8 V + 90 mV V -

System control, GPIO1/2/3, I2C,
eSDHC2, SDHC1_VSEL,
Ethernet interface, Ethernet
management interface (EMI),
TSEC_1588, DUART, Debug,
JTAG, POR signals, DFT,
USB_PWRFAULT,
USB_DRVVBUS, SAI3/4/5/6,
Flextimer, CAN, LPUART

DDR3L DRAM I/O voltage G1VDD 1.35V - 67 mV 1.35 1.35V + 67 mV V -

DDR4 DRAM I/O voltage G1VDD 1.2V - 60 mV 1.2 1.2V + 60 mV V -

Pixel clock PLL digital supply PIXEL_DVDD 1.0 V - 50 mV 1.0 1.0 V + 50 mV V 3

Pixel clock PLL digital supply PIXEL_DVDD 0.9 V - 30 mV 0.9 0.9 V + 50 mV V 3

Pixel clock PLL analog supply AVDD_PIXEL 1.8 V - 90 mV 1.8 1.8 V + 90 mV V -

PMA common I/O supply DP_OVDD 1.8 V - 90 mV 1.8 1.8 V + 90 mV V -

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 3. Recommended operating conditions (continued)

Parameter Symbol Min Typ Max Unit Notes

PMA transmit supply DP_SVDD 1.0 V - 50 mV 1.0 1.0 V + 50 mV V 3

PMA transmit supply (at 0.9 V) DP_SVDD 0.9 V - 30 mV 0.9 0.9 V + 50 mV V 3

PMA common core supply DP_AVDD 1.0 V - 50 mV 1.0 1.0 V + 50 mV V 3

PMA common core supply (at 0.9 DP_AVDD 0.9 V - 30 mV 0.9 0.9 V + 50 mV V 3
V)

eSDHC1 EVDD 3.3 V - 165 mV 3.3 3.3 V + 165 mV V -

eSDHC1, SPI1, SAI1/2 EVDD 1.8 V - 90 mV 1.8 1.8 V + 90 mV V -

Main power supply for internal SVDD 1.0 V - 50 mV 1.0 1.0 V + 50 mV V 3

circuitry of SerDes and pad power
supply for SerDes receivers and
DIFF_SYSCLK

Main power supply for internal SVDD 0.9 V - 30 mV 0.9 0.9 V + 50 mV V 3

circuitry of SerDes and pad power
supply for SerDes receivers and
DIFF_SYSCLK

Pad power supply for SerDes XVDD 1.35 V - 67 mV 1.35 1.35 V + 67 mV V -

transmitter

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NXP Semiconductors
Electrical characteristics

Table 3. Recommended operating conditions (continued)

Parameter Symbol Min Typ Max Unit Notes

SPI2/3, FlexSPI, Tamper_Detect, OVIN GND - OVDD V 8, 10

System control, GPIO1/2/3, I2C,
eSDHC2, SDHC1_VSEL,
Ethernet interface, Ethernet
management interface (EMI),
TSEC_1588, DUART, Debug,
JTAG, POR signals, DFT,
USB_PWRFAULT,
USB_DRVVBUS, SAI3/4/5/6,
Flextimer, CAN, LPUART

eSDHC1, SPI1, SAI1/2 EVIN GND - EVDD V 8, 10

Input voltage for main power SVIN GND - SVDD V 10

supply for internal circuitry of
SerDes and DIFF_SYSCLK

PHY transceiver signals: USB USB_HVIN GND - USB_HVDD V -

transceiver supply for USB PHY

PHY transceiver signals: USB USB_SVIN GND - USB_SVDD V -

PHY Analog and Digital SS supply
voltage

PHY transceiver signals: USB USB_SDVIN GND - USB_SDVDD V -

PHY Analog and Digital HS
supply voltage

Normal operating temperature TA/TJ TA = 0 - TJ = 105 °C -

range

Extended temperature range TA/TJ TA = -40 - TJ = 105 °C -

High Extended temperature range TA/TJ TA = -40 - TJ = 125 °C -

AEC-Q100 Grade 3 temperature TA/TJ TA = -40 - TJ = 85 °C 11

range

Secure boot fuse programming TA/TJ TA = 0 - TJ = 105 °C 6

operating temperature range

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 3. Recommended operating conditions (continued)

Parameter Symbol Min Typ Max Unit Notes

1. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
2. Operation at 1.08V is allowable for up to 25 ms at initial power on.
3. For supported voltage requirement for a given part number, see the Orderable part numbers addressed by this document.
4. For additional information, see the Core and platform supply voltage filtering section in the chip design checklist.
5. AVDD_PLAT, AVDD_CGA1, AVDD_CGA2, and AVDD_D1 are measured at the input to the filter and not at the pin of the
device.
6. TA_PROG_SFP must be supplied 1.8V and the chip must operate in the specified fuse programming temperature range
only during secure boot fuse programming. For all other operating conditions, PROG_SFP must be tied to GND, subject to the
power sequencing constraints shown in Power Sequencing.
7. Transceiver supply for USB PHY.
8. Caution: The input voltage level of the signals must not exceed corresponding Max value. For example DDR4 must not
exceed 5% of G1VDD.
9. Typical DDR interface uses ODT enabled mode. For tests purposes with ODT off mode, simulation should be done first so
as to make sure that the overshoot signal level at the input pin does not exceed GVDD by more than 10%. The Overshoot/
Undershoot period should comply with JEDEC standards.
10. (G1, O, S, E)VIN, USB_S*VIN and USB_HVIN may overshoot/undershoot to a voltage and for a maximum duration as shown
in the Overshoot/undershoot voltage figure at the end of this section.
11. The Tj should not exceed 105°C. Proper thermal solution should be applied to meet this requirement.

This figure shows the undershoot and overshoot voltages at the interfaces of the chip.

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NXP Semiconductors
Electrical characteristics

Maximum overshoot

E/S/G1/O/USB*VDD
VIH

GND

VIL

Minimum undershoot
Overshoot/undershoot period

Notes:
The overshoot/undershoot period should be less than 10% of shortest possible toggling period of the input signal
or per input signal specific protocol requirement. For GPIO input signal overshoot/undershoot period, it should be
less than 10% of the SYSCLK period.

Figure 8. Overshoot/undershoot voltage for GnVDD/OVDD/EVDD/USB_HVDD/USB_S*VDD/SVDD

See the Recommended operating conditions table for actual recommended core voltage. Voltage to the processor interface I/Os
are provided through separate sets of supply pins and must be provided at the voltages shown in the Recommended operating
conditions table. The input voltage threshold scales with respect to the associated I/O supply voltage. EVDD and OVDD-based
receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses
differential receivers referenced by the externally supplied D1_MVREF signal (nominally set to G1VDD/2) as is appropriate for
the SSTL_1.35 electrical signaling standard and differential receivers referenced by the internally supplied reference signal as
is appropriate for the JEDEC DDR4 electrical signaling standard. The DDR DQS receivers cannot be operated in single-ended
fashion. The complement signal must be properly driven and cannot be grounded.

3.1.3 Output drive capabilities

This chip provides information on the characteristics of the output driver strengths.

NOTE
These are estimated values.

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NXP Semiconductors
Electrical characteristics

Table 4. Output drive capability 2, 3

Driver Type Minimum 2 Typ Maximum 3 Supply_V Notes

oltage

DDR4 signal - 18 (full-strength - G1VDD = 1

mode) 27 (half- 1.2V
strength mode)

DDR3L signal - 18 (full-strength - G1VDD = 1

mode) 27 (half- 1.35V
strength mode)

SPI2/3, FlexSPI, Tamper_Detect, 30 45 60 OVDD = -

System control, GPIO1/2/3, I2C, 1.8V
eSDHC2, SDHC1_VSEL, Ethernet
interface, Ethernet management
interface (EMI), TSEC_1588,
DUART, Debug, JTAG, POR signals,
DFT, USB_PWRFAULT,
USB_DRVVBUS, SAI3/4/5/6,
Flextimer, CAN, LPUART

eSDHC1, SPI1, SAI1/2 45 65 90 EVDD = -

3.3V

1. The drive strength of the DDR4 interface in half-strength mode is at Tj = 105°C and at G1VDD (min).
2. Minimum values reflect estimated numbers based on best-case processed device.
3. Maximum values reflect estimated numbers based on worst-case processed device.

3.2 Power sequencing

The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. For power up,
these requirements are as follows:
Step 1 -
• 1.8V: OVDD, DP_OVDD, AVDD_PIXEL, TH_VDD, AVDD_CGA1, AVDD_CGA2, AVDD_PLAT, AVDD_D1
• 3.3V: USB_HVDD
• 1.8V/3.3V: EVDD
— Drive TA_PROG_SFP = GND
— PORESET_B should be driven asserted and held during this step.
Step 2 -
• 1.0V / 0.9V: VDD, SVDD, DP_SVDD, DP_AVDD, PIXEL_DVDD, USB_SDVDD, USB_SVDD, TA_BB_VDD
Step 3-
• System with DDR3L memory (1.35V): G1VDD, XVDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2
• System with DDR4 memory (1.2V): G1VDD (XVDD, AVDDSD1_PLL1 and AVDD_SD1_PLL2 can be powered up in any step)

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NXP Semiconductors
Electrical characteristics

Items on the same step have no ordering requirement with respect to one another. Items on separate steps must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of their value.
All supplies must be at their stable values within 400 ms.
Negate PORESET_B input when the required assertion/hold time has been met per Table 13. RESET initialization timing
specifications on page 75.

NOTE
• While VDD is ramping up, current may be supplied from VDD through LS1028A to G1VDD.

• The 3.3V (USB_HVDD) in Step 1 and 1.0V/0.9V (USB_SDVDD, USB_SVDD) in Step 2 supplies should ramp
up within 95ms with respect to each other.

• 100us minimum spacing is required between Step 1 (DP_OVDD) and Step2 (DP_SVDD, DP_AVDD) supplies.

• If Trust Architecture Security Monitor battery backed feature is not used, TA_BB_VDD should be connected
with VDD.

• If using Trust Architecture Security Monitor battery backed features, prior to VDD ramping up to the 0.5 V
level, ensure that SVDD is ramped to recommended operational voltage and DIFF_SYSCLK_P/
DIFF_SYSCLK_N is running. These clocks should have a minimum frequency of 800 Hz and a maximum
frequency not greater than the supported system clock frequency for the device.

• Ramp rate requirements should be met per Table 9. Power supply ramp rate on page 72.

• While XVDD is ramping, current may be supplied from XVDD through chip to SVDD.

Differential System clock should meet DC and AC Specifications as per Differential system clock DC electrical characteristics on
page 73 and Differential system clock AC timing specifications on page 73 respectively.

Warning
Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates
and is preliminary.

For secure boot fuse programming, use the following steps:

1. After negation of PORESET_B, drive TA_PROG_SFP = 1.8 V after a required minimum delay per Table 5. TA_PROG_SFP
timing 5 on page 70.
2. After fuse programming is complete, it is required to return TA_PROG_SFP = GND before the system is power cycled or
powered down (VDD ramp down) per the required timing specified in Table 5. TA_PROG_SFP timing 5 on page 70. See
Security fuse processor on page 181 for additional details.

Warning
No activity other than that required for secure boot fuse programming is permitted while TA_PROG_SFP is driven
to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur
while TA_PROG_SFP = GND.

This figure shows the TA_PROG_SFP timing diagram.

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NXP Semiconductors
Electrical characteristics

Fuse programming

10% TA_PROG_SFP 10% TA_PROG_SFP

TA_PROG_SFP

90% VDD
VDD tTA_PROG_SFP_VDD

90% OVDD tTA_PROG_SFP_PROG 90% OVDD

PORESET_B
tTA_PROG_SFP_DELAY tTA_PROG_SFP_RST

NOTE: TA_PROG_SFP must be stable at 1.8 V prior to initiating fuse programming.

Figure 9. TA_PROG_SFP timing diagram

This table provides information on the power-down and power-up sequence parameters for TA_PROG_SFP.

Table 5. TA_PROG_SFP timing 5

Driver type Min Max Unit Notes

tTA_PROG_SFP_DELAY 10 — SYSCLKs 1

tTA_PROG_SFP_PROG 0 — us 2

tTA_PROG_SFP_VDD 0 — us 3

tTA_PROG_SFP_RST 0 — us 4

Notes:
1. Delay required from the deassertion of PORESET_B to driving TA_PROG_SFP ramp up. Delay measured from PORESET_B
deassertion at 90% OVDD to 10% TA_PROG_SFP ramp up.
2. Delay required from fuse programming completion to TA_PROG_SFP ramp down start. Fuse programming must complete
while TA_PROG_SFP is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted
while TA_PROG_SFP is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse
block may only occur while TA_PROG_SFP = GND. After fuse programming is complete, it is required to return TA_PROG_SFP
= GND.
3. Delay required from TA_PROG_SFP ramp-down complete to VDD ramp-down start. TA_PROG_SFP must be grounded to
minimum 10% TA_PROG_SFP before VDD reaches 90% VDD.
4. Delay required from TA_PROG_SFP ramp-down complete to PORESET_B assertion. TA_PROG_SFP must be grounded
to minimum 10% TA_PROG_SFP before PORESET_B assertion reaches 90% OVDD.
5. Only six secure boot fuse programming events are permitted per lifetime of a device.

3.3 Power-down requirements

The power-down cycle must complete such that all power supply values are below 0.4 V before a new power-up cycle can be
started.

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 70 / 184
NXP Semiconductors
Electrical characteristics

If performing secure boot fuse programming per Power sequencing on page 68, it is required that TA_PROG_SFP = GND before
the system is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in
Table 5. TA_PROG_SFP timing 5 on page 70.

NOTE
All input signals, including I/Os that are configured as inputs, driven into the chip need to monotonically increase/
decrease through entire rise/fall durations.

3.4 Power characteristics

This table shows the thermal power dissipation of the VDD power supply for A72 core/platform/DDR frequency combinations.

Table 6. LS1028A VDD power dissipation for the thermal design at 850C

Core Platform DDR data GPU and VDD (V) IOVDD4 (V) Power (W) Total Notes
frequency frequenc rate LCD Core and
(MHz) y(MHz) (MT/s) controller VDD (W) IOVDD (W) Platform
frequency Power
(MHz) (W)

1500 400 1600 700 1.0 1.0 6.25 1.9 8.15 1, 2, 3

1300 400 1600 650 1.0 1.0 5.90 1.9 7.80 1, 2, 3

1000 400 1600 500 1.0 1.0 4.35 1.9 6.25 1, 2, 3

800 300 1300 400 0.9 0.9 2.7 1.8 4.5 1, 2, 3

Notes:
1. Thermal power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform at
100% activity factor.
2. Thermal power are based on worst-case processed device.
3. Refer to AN12028 "QorIQ LS1028A Design Checklist":
"Maximum VDD Power and IO Power" shows the maximum power dissipation across junction temperature range. This should
be used as guide for power supply design and regulator sizing.
"Thermal Power" shows the thermal power across junction temperature range. This data should be used thermal solution design.
4. IOVDD includes SVDD, USB_SDVDD, USB_SVDD, PIXEL_DVDD, DP_SVDD and DP_AVDD

Table 7. LS1018A VDD power dissipation for the thermal design at 850C

Core Platform DDR data GPU and VDD (V) IOVDD4 (V) Power (W) Total Notes
frequency frequenc rate LCD Core and
(MHz) y(MHz) (MT/s) controller VDD (W) IOVDD (W) Platform
frequency Power
(MHz) (W)

1500 400 1600 700 1.0 1.0 5.25 1.9 7.15 1, 2, 3

1300 400 1600 650 1.0 1.0 5.10 1.9 7.0 1, 2, 3

1000 400 1600 500 1.0 1.0 3.65 1.9 5.55 1, 2, 3

Table continues on the next page...

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Data Sheet: Technical Data 71 / 184
NXP Semiconductors
Electrical characteristics

Table 7. LS1018A VDD power dissipation for the thermal design at 850C (continued)

Core Platform DDR data GPU and VDD (V) IOVDD4 (V) Power (W) Total Notes
frequency frequenc rate LCD Core and
(MHz) y(MHz) (MT/s) controller VDD (W) IOVDD (W) Platform
frequency Power
(MHz) (W)

800 300 1300 400 0.9 0.9 2.3 1.8 4.1 1, 2, 3

Notes:
1. Thermal power assumes Dhrystone running with activity factor of 90% on core and executing DMA on the platform at 100%
activity factor.
2. Thermal power are based on worst-case processed device.
3. Refer to AN12028 "QorIQ LS1028A Design Checklist":
"Maximum VDD Power and IO Power" shows the maximum power dissipation across junction temperature range. This should
be used as guide for power supply design and regulator sizing.
"Thermal Power" shows the thermal power across junction temperature range. This data should be used thermal solution design.
4. IOVDD includes SVDD, USB_SDVDD, USB_SVDD, PIXEL_DVDD, DP_SVDD and DP_AVDD

This table shows the estimated power dissipation on the TA_BB_VDD supply at allowable voltage levels.

Table 8. TA_BB_VDD power dissipation

Supply Maximum Unit Notes

TA_BB_VDD (SoC off, 40°C) 40 μW 1

TA_BB_VDD (SoC off, 70°C) 55 μW 1

Note: 1. When SoC is off, TA_BB_VDD may be supplied by battery power to retain the Zeroizable Master Key and other
trust architecture state. Board should implement a PMIC, which switches TA_BB_VDD to battery when SoC is powered
down. See the Device reference manual trust architecture chapter for more information.

3.5 Power-on ramp rate

This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum power-
on ramp rate is required to avoid excess in-rush current.
This table provides the power supply ramp rate specifications.

Table 9. Power supply ramp rate

Parameter Min Max Unit Notes

Required ramp rate for all voltage supplies (including OVDD/G1VDD/SVDD/XVDD/ — 25 V/ms 1, 2
EVDD/PIXEL_DVDD, all core and platform VDD supplies and all AVDD supplies.)

Required ramp rate for TA_PROG_SFP — 25 V/ms 1, 2

Required ramp rate for USB_HVDD — 26.7 V/ms 1, 2

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Table 9. Power supply ramp rate (continued)

Parameter Min Max Unit Notes

Maximum ramp time for DP_AVDD, DP_SVDD — 8 V/ms 3

Maximum ramp time for DP_OVDD — 16 V/ms 3

Notes:
1. Ramp rate is specified as a linear ramp from 10% to 90%. If non-linear (for example, exponential), the maximum rate of
change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
2. Over full recommended operating temperature range (see Recommended Operating Conditions).
3. From 10% to 90%

3.6 Input clocks

3.6.1 Differential system clock (DIFF_SYSCLK_P/DIFF_SYSCLK_N) timing specifications

The differential system clocking mode requires an on-board oscillator to provide reference clock input to the differential system
clock pair (DIFF_SYSCLK_P/DIFF_SYSCLK_N).
This differential clock pair can be configured to provide the clock to core, platform, and USB PLLs.
This figure shows a receiver reference diagram of the differential system clock.

50 Ω

DIFF_SYSCLK_P

Input
amp

DIFF_SYSCLK_N

50 Ω

Figure 10. HCSL receiver

This section provides the differential system clock DC and AC timing specifications.

3.6.1.1 Differential system clock DC electrical characteristics

For DC electrical characteristics, see DC-level requirement for SerDes reference clocks on page 126.
The differential system clock receiver's core power supply voltage requirements are specified in Recommended Operating
Conditions.

3.6.1.2 Differential system clock AC timing specifications

The DIFF_SYSCLK_P/DIFF_SYSCLK_N input pair supports an input clock frequency of 100 MHz.

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Electrical characteristics

For AC timing specifications, see SerDes reference clocks AC timing specifications on page 128.
Spread-spectrum clocking is not supported on differential system clock pair input.

3.6.2 USB reference clock specifications

The reference clock of the USB PHY is the DIFF_SYSCLK_P/DIFF_SYSCLK_N.

Table 10. USB AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Reference clock frequency fSYSCLK - 100 - MHz -

Reference clock frequency- FREF_OFFSET -300.0 - 300.0 ppm -

offset

Reference clock random JRMSREF_CLK - - 3.0 ps 1, 2

jitter (RMS)

Reference clock cycle-to- DJREF_CLK - 150.0 ps 3

cycle jitter

Reference clock duty cycle tKHK/tSYSCLK 40 - 60 % -

1. 1.5 MHz to Nyquist frequency. For example, for 100 MHz reference clock, the Nyquist frequency is 50 MHz.
2. The peak-to-peak Rj specification is calculated at 14.069 times the RJRMS for 10-12 BER.
3. DJ across all frequencies.

3.6.3 Gigabit Ethernet reference clock timing

This table provides the Ethernet gigabit reference clock DC electrical characteristics with OVDD = 1.8 V.

Table 11. EC_GTX_CLK125 DC electrical characteristics (OVDD = 1.8 V)1

Parameter Symbol Min Typical Max Unit Notes

Input high voltage VIH 1.2 — — V 2

Input low voltage VIL — — 0.3 x OVDD V 2

Input capacitance CIN — — 6 pF —

Input current (VIN = 0 V or VIN = OVDD) IIN — — ± 50 µA 3

Notes:
1. For recommended operating conditions, see Recommended Operating Conditions.
2. The min VIL and max VIH values are based on the respective min and max VIN values found in Recommended Operating
Conditions.
3. The symbol VIN, in this case, represents the OVIN symbol referenced in Recommended Operating Conditions.

This table provides the Ethernet gigabit reference clock AC timing specifications.

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Table 12. EC_GTX_CLK125 AC timing specifications 1

Parameter/Condition Symbol Min Typical Max Unit Notes

EC_GTX_CLK125 frequency fG125 125 - 100 ppm 125 125 + 100 MHz —
ppm

EC_GTX_CLK125 cycle time tG125 8 ns —

EC_GTX_CLK125 rise and fall time tG125R/tG125F — — ns 2

0.75
OVDD = 1.8 V

EC_GTX_CLK125 duty cycle tG125H/tG125 40 — 60 % 3

1000Base-T for RGMII

Notes:
1. At recommended operating conditions with OVDD = 1.8 V ± 90mV. See Recommended Operating Conditions.
2. Rise times are measured from 20% of OVDD to 80% of OVDD. Fall times are measured from 80% of OVDD to 20% of OVDD.
3. EC_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter.See RGMII AC timing specifications on
page 102 for duty cycle for the 10Base-T and 100Base-T reference clocks.

3.6.4 Other input clocks

A description of the overall clocking of this device is available in the chip reference manual in the form of a clock subsystem block
diagram. For information about the input clock requirements of functional modules sourced external of the chip, see the specific
interface section.

3.7 Reset initialization timing specifications

This table provides the RESET initialization timing specifications.

Table 13. RESET initialization timing specifications

Parameter Min Max Unit Notes

Required assertion time of PORESET_B after all 1.0 - ms 1

supply rails are stable

Required input assertion time of HRESET_B 32.0 - SYSCLK 2, 3, 7

Maximum rise/fall time of PORESET_B - 1.0 SYSCLK 4,6

Maximum rise/fall time of HRESET_B - 10 SYSCLK 4,5

Input setup time for POR configs with respect to 4.0 - SYSCLK 2
negation of PORESET_B

Input hold time for all POR configs with respect to 2.0 - SYSCLK 2
negation of PORESET_B

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Table 13. RESET initialization timing specifications (continued)

Parameter Min Max Unit Notes

Maximum valid-to-high impedance time for - 5.0 SYSCLK 2

actively driven POR configs with respect to
negation of PORESET_B

1. PORESET_B must be driven asserted before the core and platform power supplies are powered up.
2. DIFF_SYSCLK_P/DIFF_SYSCLK_N is the primary clock input for the chip.
3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The
device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is
documented in the reference manual's "Power-on Reset Sequence" section.
4. The system/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
5. For HRESET_B the rise/fall time should not exceed 10 SYSCLKs. Rise time refers to signal transitions from 20% to 70% of
OVDD. Fall time refers to transitions from 70% to 20% of OVDD.
6. For PORESET_B the rise/fall time should not exceed 1 SYSCLK. Rise time refers to signal transitions from 20% to 70% of
OVDD. Fall time refers to transitions from 70% to 20% of OVDD.
7. See General A-050124 erratum.

3.8 Controller Automatic Network interface (CAN)

3.8.1 CAN DC electrical chracteristics

This table provides the DC electrical characteristics for CAN-FD.

Table 14. DC electrical characteristics for CAN-FD (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0 V or VIN= OVDD) IIN - ±50 μA 3

Output high voltage (OVDD = min, IOH= VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOH= VOL - 0.4 V -

-0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

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3.8.2 CAN AC electrical characteristics

This table provides the CAN-FD AC timing specifications.

Table 15. CAN-FD AC timing specifications 1

Parameter Min Max Unit

Baud rate 10.0 8000.0 kbps

1. See Figure 11. on page 77.

This figure provides the CAN-FD AC test load.

Output Z0= 50 Ω OVDD/2

RL = 50 Ω

Figure 11. FlexCAN AC test load

3.9 DDR3L and DDR4 SDRAM controller

This section describes the DC and AC electrical specifications for the DDR3L and DDR4 SDRAM controller interface. Note that
the required G1VDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM, and the required G1VDD(typ) voltage is 1.2 V
when interfacing to DDR4 SDRAM.

3.9.1 DDR3L and DDR4 SDRAM controller DC electrical characteristics

This table provides the recommended opearting conditions for the DDR SDRAM controller when interfacing to DDR3L SDRAM.

Table 16. DDR3L SDRAM interface DC electrical characteristics (G1V DD = 1.35V) 1, 9

Parameter Symbol Min Typ Max Unit Notes

I/O reference voltage MVREFn 0.49 * G1VDD 0.5 * G1VDD 0.51 * G1VDD V 2, 3, 4

Input high voltage VIH MVREFn + - G1VDD V 5

0.090

Input low voltage VIL GND - MVREFn - 0.090 V 5

I/O leakage current IOZ -200.0 - 200.0 μA 6

I/O leakage current at 0.9V VDD IOZ -275.0 - 275.0 μA 6

and 1250C

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Table 16. DDR3L SDRAM interface DC electrical characteristics (G1V DD = 1.35V) 1, 9 (continued)

Parameter Symbol Min Typ Max Unit Notes

Output high current (VOUT = 0.641 IOH - - -23.3 mA 7, 8

Output low current (VOUT = 0.641 IOL 23.3 - - mA 7, 8

1. For recommended operating conditions, see Recommended Operating Conditions.

2. MVREFn is expected to be equal to 0.5 x G1VDD and to track G1VDD DC variations as measured at the receiver. Peak-to-
peak noise on MVREFn may not exceed the MVREFn DC level by more than ± 1% of G1VDD (i.e. ± 13.5 mV).
3. VTT is not applied directly to the device. It is the supply to which fare end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn - 0.04 and a max value of MVREFn + 0.04. VTT should track variations in the
DC level of MVREFn.
4. The voltage regulator for MVREFn must meet the specification stated in Table 17. Current draw characteristics for MVREFn
(G1V DD = 1.35V) 1 on page 78.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Refer to IBIS model for the complete output IV curve characteristics.
7. IOH and IOL are measured at G1VDD = 1.282V
8. Output leakage is measured with all outputs diabled, 0 V ≤ V OUT ≤ G1VDD
9. G1VDD is expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.

This tables provides the current draw characteristics for MVREFn.

Table 17. Current draw characteristics for MVREFn (G1V DD = 1.35V) 1

Parameter Symbol Min Max Unit

Current draw for MVREFn IMVREFn - 500.0 μA

1. For recommended operating conditions, see Recommended Operating Conditions.

This table provides the recommended opearting conditions for the DDR SDRAM controller when interfacing to DDR4 SDRAM.

Table 18. DDR4 SDRAM interface DC electrical characteristics (G1V DD = 1.2V) 1, 7

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 * G1VDD + 0.175 - V 2, 3

Input low voltage VIL - 0.7 * G1VDD - 0.175 V 2, 3

I/O leakage current IOZ -200.0 200.0 μA 4

I/O leakage current at 0.9V VDD and IOZ -275.0 275.0 μA 6

1250C

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Table 18. DDR4 SDRAM interface DC electrical characteristics (G1V DD = 1.2V) 1, 7 (continued)

Parameter Symbol Min Max Unit Notes

Output high current (VOUT = 0.641 V) IOH - -20.7 mA 5, 6

Output low current (VOUT = 0.641 V) IOL 20.7 - mA 5, 6

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
3. Internal Vref for data bus must be set to 0.7 x G1VDD
4. Refer to IBIS model for the complete output IV curve characteristics.
5. IOH and IOL are measured at G1VDD = 1.14V
6. Output leakage is measured with all outputs diabled, 0 V ≤ V OUT ≤ G1VDD
7. G1VDD is expected to be within 60 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source. G1VDD min = 1.14 V, G1VDD max = 1.26 V, and G1VDD typ = 1.2 V.

3.9.2 DDR3L and DDR4 SDRAM controller AC timing specifications

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR4 SDRAM.

Table 19. DDR4 SDRAM interface input AC timing specifications

Parameter Symbol Min Max Unit

AC input low voltage VILAC - 0.7 * G1VDD - 0.175 V

AC input high voltage VIHAC 0.7 * G1VDD + 0.175 - V

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM.

Table 20. DDR3L SDRAM interface input AC timing specifications 1

Parameter Symbol Min Max Unit

AC input low voltage VILAC - MVREFn-0.135 V

AC input high voltage VIHAC MVREFn+0.135 - V

1. See Figure 12. on page 83.

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM.

Table 21. DDR3L SDRAM interface input AC timing specifications 3

Parameter Symbol Min Max Unit Notes

Controller Skew for MDQS-MDQ/MECC tCISKEW - - ps -

Data Rate of 1300 MT/s in DDR3L -125.0 125.0 1

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Table 21. DDR3L SDRAM interface input AC timing specifications 3 (continued)

Parameter Symbol Min Max Unit Notes

Data Rate of 1600 MT/s in DDR3L -112.0 112.0 1

Tolerated Skew for MDQS-MDQ/MECC tDISKEW - - ps -

Data Rate of 1300 MT/s in DDR3L -250.0 250.0 2

Data Rate of 1600 MT/s in DDR3L -200.0 200.0 2

1. tCISKEW represents the amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be
captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = +/-(T / 4 - abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
3. See Figure 12. on page 83.

This table contains the output AC timing targets for the DDR3L SDRAM interface.

Table 22. DDR3L SDRAM interface output AC timing specifications 6

Parameter Symbol Min Max Unit Notes

MCK[n] cycle time tMCK 1250.0 2000.0 ps 1

ADDR/CMD/CNTL output setup with tDDKHAS - - ps -

respect to MCK

Data Rate of 1300 MT/s in DDR3L 606.0 - 2

Data Rate of 1600 MT/s in DDR3L 495.0 - 2

ADDR/CMD/CNTL output hold with tDDKHAX - - ps -

respect to MCK

Data Rate of 1300 MT/s in DDR3L 606.0 - 2

Data Rate of 1600 MT/s in DDR3L 495.0 - 2

MCK to MDQS Skew tDDKNMH - - ps -

Data Rate of 1300 MT/s in DDR3L -245.0 245.0 3, 4

Data Rate of 1600 MT/s in DDR3L -150.0 150.0 3, 4

MDQ/MECC/MDM output data eye tDDKXDEYE - - ps -

Data Rate of 1300 MT/s in DDR3L 500.0 - 5

Data Rate of 1600 MT/s in DDR3L 400.0 - 5

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Table 22. DDR3L SDRAM interface output AC timing specifications 6 (continued)

Parameter Symbol Min Max Unit Notes

MDQS preamble tDDKHMP 0.9 * tMCK - ps -

MDQS postamble tDDKHME 0.4 * tMCK 0.6 * tMCK ps -

1. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.
2. ADDR/CMD/CNTL includes all DDR SDRAM output signals except MCK/MCK_B, and MDQ/MECC/MDM/MDQS/MDQS_B.
3. Note that tDDKHMH follows the symbol conventions described above. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). The timing parameters listed in this
table assume that the MCK and MDQS signals are programmed to launch from the controller using the same adjustment value.
4. Note that it is required to program the start value of the DQS adjust for write leveling.
5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller
will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.
6. See Figure 13. on page 83.

NOTE
For the ADDR/CMD setup and hold specifications in Table 22. DDR3L SDRAM interface output AC timing
specifications 6 on page 80, it is assumed that the clock control register is set to adjust the memory clockes by
1/2 applied cycle .

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR4 SDRAM.

Table 23. DDR4 SDRAM interface input AC timing specifications 3

Parameter Symbol Min Max Unit Notes

Controller Skew for MDQS-MDQ/MECC tCISKEW - - ps -

Data Rate of 1300 MT/s in DDR4 -125.0 125.0 1

Data Rate of 1600 MT/s in DDR4 -112.0 112.0 1

Tolerated Skew for MDQS-MDQ/MECC tDISKEW - - ps -

Data Rate of 1300 MT/s in DDR4 -250.0 250.0 2

Data Rate of 1600 MT/s in DDR4 -200.0 200.0 2

This table contains the output AC timing targets for the DDR4 SDRAM interface.

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Table 24. DDR4 SDRAM interface output AC timing specifications 6

Parameter Symbol Min Max Unit Notes

MCK[n] cycle time tMCK 1250.0 1538.0 ps 1

ADDR/CMD/CNTL output setup with tDDKHAS - - ps -

respect to MCK

Data Rate of 1300 MT/s in DDR4 606.0 - 2

Data Rate of 1600 MT/s in DDR4 495.0 - 2

ADDR/CMD/CNTL output hold with tDDKHAX - - ps -

respect to MCK

Data Rate of 1300 MT/s in DDR4 606.0 - 2

Data Rate of 1600 MT/s in DDR4 495.0 - 2

MCK to MDQS Skew tDDKNMH -245.0 245.0 ps 3, 4

MDQ/MECC/MDM output data eye tDDKXDEYE - - ps -

Data Rate of 1300 MT/s in DDR4 500.0 - 5

Data Rate of 1600 MT/s in DDR4 400.0 - 5

MDQS preamble tDDKHMP 0.9 * tMCK - ps -

MDQS postamble tDDKHME 0.4 * tMCK 0.6 * tMCK ps -

NOTE
For the ADDR/CMD setup and hold specifications in Table 24. DDR4 SDRAM interface output AC timing
specifications 6 on page 82, it is assumed that the clock control register is set to adjust the memory clockes by
1/2 applied cycle .

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MCK[n]_B
MCK[n]
tMCK

MDQS[n]

tDISKEW

MDQ[x] D0 D1

tDISKEW
tDISKEW

Figure 12. DDR4 SDRAM interface input timing diagram

MCK_B

MCK
tMCK

tDDKHAS, tDDKHCS

tDDKHAX, tDDKHCX

ADDR/CMD Write A0 NOOP

tDDKHMP

tDDKHMH

MDQS[n]

tDDKHDS tDDKHME
tDDKLDS

MDQ[x] D0 D1

tDDKLDX
tDDKHDX

Figure 13. DDR4 SDRAM interface output timing diagram

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3.10 Enhanced secure digital host controller (eSDHC)

This table provides the DC electrical characteristics for the eSDHC interface. This device has two eSDHC interfaces. Out of the
two, eSDHC2 supports only 1.8 V voltage levels.

3.10.1 eSDHC DC electrical characteristics

This table provides the DC electrical characteristics for the eSDHC interface.

Table 25. eSDHC DC electrical characteristics (EV DD = 3.3V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x EVDD - V 2

Input low voltage VIL - 0.25 x EVDD V 2

Input/output leakage current IIN/IOZ - ±50 μA -

Output high voltage (IOH = -100μA at VOH 0.75 x EVDD - V -

EVDD min)

Output low voltage (IOL = 100μA at EVDD VOL - 0.125 x EVDD V -

min)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min VIL and max VIH values are based on the respective min and max EVIN values found in Recommended Operating
Conditions.

This table provides the DC electrical characteristics for the eSDHC interface.

Table 26. eSDHC DC electrical characteristics (EV DD/OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x EVDD/OVDD - V 2

Input low voltage VIL - 0.3 x EVDD/OVDD V 2

Input/output leakage current IIN/IOZ - ±50 μA -

Output high voltage (IOH = -2mA at EVDD/ VOH EVDD/OVDD - 0.45 - V -

OVDD min)

Output low voltage (IOL = 2mA at VOL - 0.45 V -

EVDD/OVDD min)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min VIL and max VIH values are based on the respective min and max EVIN/OVIN values found in Recommended
Operating Conditions.

3.10.2 eSDHC AC timing specifications

This table provides the eSDHC AC timing specifications as defined in the eSDHC clock input timing diagram.

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Table 27. eSDHC AC timing specifications (full-speed mode) 1, 3, 5, 6

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency SD/SDIO mode fSHSCK - - MHz -

SD/SDIO full-speed mode 0.0 25.0 1, 2, 3

eMMC full-speed mode 0.0 26.0 1, 2, 3

SDHC_CLK clock low time tSHSCKL 10.0 - ns 3

SDHC_CLK clock high time tSHSCKH 10.0 - ns 3

SDHC_CLK clock rise and fall times tSHSCKR/ - 3.0 ns 3

tSHSCKF

Input setup times (SDHC_CMD, tSHSIVKH 2.5 - ns 3, 4

SDHC_DATx to SDHC_CLK)

Input hold times (SDHC_CMD, tSHSIXKH 2.5 - ns 3

SDHC_DATx to SDHC_CLK)

Output hold time (SDHC_CLK to tSHSKHOX -3.0 - ns 3

SDHC_CMD, SDHC_DATx valid)

Output delay time (SDHC_CLK to tSHSKHOV - 3.0 ns 3

SDHC_CMD, SDHC_DATx valid)

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (R for rise) or
F ( F for fall).
2. In full-speed mode, the clock frequency value can be 0-25MHz for an SD/SDIO card and 0-26MHz for an eMMC device.
3. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF.
4. SDHC_SYNC_OUT/IN loop back is recommended to compensate the clock delay. In case the SDHC_SYNC_OUT/IN
loopback is not used, to satisfy setup timing, one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD,
and SDHC_DATx should not exceed 1ns for any high-speed eMMC . For any high-speed or default speed mode SD card, the
one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1.5ns.
5. See Figure 14. on page 86.
6. The AC timing specifications are based on the recommended operating conditions with EVDD =3.3V and OVDD=1.8V, see
Recommended Operating Conditions

This figure provides the eSDHC clock input timing diagram as shown here.

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eSDHC
external clock
VM VM VM
operational mode

tSHSCKL tSHSCKH

tSHSCK

tSHSCKR tSHSCKF

VM = Midpoint voltage (Respective supply / 2)

Figure 14. eSDHC clock input timing diagram

This table provides the eSDHC AC timing specifications as defined in the eSDHC clock input timing diagram.

Table 28. eSDHC AC timing specifications (high-speed mode) 1, 3, 5, 6, 7

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency SD/SDIO mode fSHSCK - - MHz -

SD/SDIO high-speed mode 0.0 50.0 1, 2, 3

eMMC high-speed mode 0.0 52.0 1, 2, 3

SDHC_CLK clock low time tSHSCKL 7.0 - ns 3

SDHC_CLK clock high time tSHSCKH 7.0 - ns 3

SDHC_CLK clock rise and fall times tSHSCKR/ - 3.0 ns 3

tSHSCKF

Input setup times (SDHC_CMD, tSHSIVKH 2.5 - ns 3, 4

SDHC_DATx to SDHC_CLK)

Input hold times (SDHC_CMD, tSHSIXKH 2.5 - ns 3

SDHC_DATx to SDHC_CLK)

Output hold time (SDHC_CLK to tSHSKHOX -3.0 - ns 3

SDHC_CMD, SDHC_DATx valid)

Output delay time (SDHC_CLK to tSHSKHOV - 3.0 ns 3

SDHC_CMD, SDHC_DATx valid)

Table continues on the next page...

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Data Sheet: Technical Data 86 / 184
NXP Semiconductors
Electrical characteristics

Table 28. eSDHC AC timing specifications (high-speed mode) 1, 3, 5, 6, 7 (continued)

Parameter Symbol Min Max Unit Notes

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (R for rise) or
F ( F for fall).
2. In high-speed mode, the clock frequency value can be 0-50MHz for an SD/SDIO card and 0-52MHz for an MMC card.
3. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF.
4. SDHC_SYNC_OUT/IN loop back is recommended to compensate the clock delay. In case the SDHC_SYNC_OUT/IN
loopback is not used, to satisfy setup timing, one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD,
and SDHC_DATx should not exceed 1ns for any high-speed eMMC . For any high-speed or default speed mode SD card, the
one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1.5ns.
5. See Figure 15. on page 87.
6. See Figure 16. on page 88.
7. The AC timing specifications are based on the recommended operating conditions with EVDD =3.3V and OVDD=1.8V, see
Recommended Operating Conditions

This figure provides the input AC timing diagram for high-speed mode.

VM VM VM VM

SDHC_CLK
t SHSIVKH t SHSIXKH

SDHC_DAT/SDHC_CMD
inputs

VM = Midpoint Voltage (Respective supply / 2)

Figure 15. eSDHC high-speed mode input AC timing diagram

This figure provides the output AC timing diagram for high-speed mode.

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Data Sheet: Technical Data 87 / 184
NXP Semiconductors
Electrical characteristics

VM VM VM VM

SDHC_CLK

SDHC_CMD/ SDHC_DAT
outputs

t SHSKHOV tSHSKHOX

VM = Midpoint Voltage (Respective supply / 2)

Figure 16. eSDHC high-speed mode output AC timing diagram

This table provides the eSDHC AC timing specifications for SDR50 mode on devices without a voltage translator.

Table 29. eSDHC AC timing specifications (SDR50 mode without voltage translator) 2, 3, 4, 5

Parameter Symbol Min Max Unit Notes

SDHC_CLK clock frequency fSHSCK 0.0 100.0 MHz -

SDHC_CLK rise and fall times tSHSCKR/ - 2.0 ns 1

tSHSCKF

Skew between tSHSKEW -0.1 0.1 ns 1

SDHC_CLK_SYNC_OUT and
SDHC_CLK

SDHC_CLK duty cycle tSHSCK 47.0 53.0 % -

Input setup times (SDHC_CMD, tSHSIVKH 2.1 - ns 1

SDHC_DATx to
SDHC_CLK_SYNC_IN)

Input hold times (SDHC_CMD, tSHSIXKH 1.1 - ns 1

SDHC_DATx to
SDHC_CLK_SYNC_IN)

Output hold time (SDHC_CLK to tSHSKHOX 1.7 - ns 1

SDHC_CMD, SDHC_DATx valid)

Output delay time (SDHC_CLK to tSHSKHOV - 6.1 ns 1

SDHC_CMD, SDHC_DATx valid)

Table continues on the next page...

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Data Sheet: Technical Data 88 / 184
NXP Semiconductors
Electrical characteristics

Table 29. eSDHC AC timing specifications (SDR50 mode without voltage translator) 2, 3, 4, 5 (continued)

Parameter Symbol Min Max Unit Notes

1. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 30 pF.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (R for rise) or
F ( F for fall).
3. See Figure 17. on page 89.
4. See Figure 18. on page 90.
5. The AC timing specifications are based on the recommended operating conditions with EVDD /OVDD =1.8V, see
Recommended Operating Conditions

This figure provides the eSDHC input AC timing diagram for SDR50 mode.

T CLK

SDHC_CLK_SYNC_IN

TSHSIVKH TSHSIXKH

SDHC_CMD/
SDHC_DAT
input

Figure 17. eSDHC SDR50 mode input AC timing diagram

This figure provides the eSDHC output timing diagram for SDR50 mode.

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Data Sheet: Technical Data 89 / 184
NXP Semiconductors
Electrical characteristics

T
CLK

SDHC_CLK

T
SHSKHOV

SDHC_CMD/
SDHC_DAT
output

T
SHSKHOX

Figure 18. eSDHC SDR50 mode output timing diagram

This table provides the eSDHC AC timing specifications for DDR50/DDR mode.

Table 30. eSDHC AC timing specifications (DDR50/DDR mode without voltage translator) 3, 4, 5, 6

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency fSHCK - - MHz -

SD/SDIO DDR50 mode - 45 1

eMMC DDR mode - 45 2

SDHC_CLK duty cycle tSHSCK 47.0 53.0 % -

Skew between tSHSKEW -0.65 0.65 ns -

SDHC_CLK_SYNC_OUT and
SDHC_CLK

SDHC_CLK rise and fall times tSHCKR/ - - ns -

tSHCKF
SD/SDIO DDR50 mode - 4.0 1

eMMC DDR mode - 2.0 2

Input setup times (SDHC_DATx to tSHDIVKH - - ns -

SDHC_CLK_SYNC_IN)

SD/SDIO DDR50 mode 2.7 - 1

eMMC DDR mode 2.7 - 2

Input hold times (SDHC_DATx to tSHDIXKH 0.75 - ns 1

SDHC_CLK_SYNC_IN)

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 30. eSDHC AC timing specifications (DDR50/DDR mode without voltage translator) 3, 4, 5, 6 (continued)

Parameter Symbol Min Max Unit Notes

Output hold time (SDHC_CLK to tSHDKHOX - - ns -

SDHC_DATx valid)

SD/SDIO DDR50 mode 1.7 - 1

eMMC DDR mode 3.4 - 2

Output delay time (SDHC_CLK to tSHDKHOV - - ns -

SDHC_DATx valid)

SD/SDIO DDR50 mode - 7.3 1

eMMC DDR mode - 7.75 2

Input setup time (SDHC_CMD to tSHCIVKH - - ns -

SDHC_CLK_SYNC_IN)

SD/SDIO DDR50 mode 6.9 - 1

eMMC DDR mode 7.1 - 2

Input hold time (SDHC_CMD to tSHCIXKH 0.75 - ns 1

SDHC_CLK_SYNC_IN)

Output hold time (SDHC_CLK to tSHCKHOX - - ns -

SDHC_CMD valid)

SD/SDIO DDR50 mode 1.7 - 1

eMMC DDR mode 3.9 - 2

Output delay time (SDHC_CLK to tSHCKHOV - - ns -

SDHC_CMD valid)

SD/SDIO DDR50 mode - 15.3 1

eMMC DDR mode - 18.0 2

Table continues on the next page...

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Data Sheet: Technical Data 91 / 184
NXP Semiconductors
Electrical characteristics

Table 30. eSDHC AC timing specifications (DDR50/DDR mode without voltage translator) 3, 4, 5, 6 (continued)

Parameter Symbol Min Max Unit Notes

1. CCARD ≤ 10pF, (1 card).

2. CL = CBUS + CHOST + CCARD ≤ 20 pF for MMC, ≤ 25pF for Input Data of DDR50, ≤ 30pF for Input CMD of DDR50.
3. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (R for rise) or
F ( F for fall).
4. See Figure 19. on page 92.
5. See Figure 20. on page 93.
6. The AC timing specifications are based on the recommended operating conditions with EVDD /OVDD =1.8V and EVDD=3.3V,
see Recommended Operating Conditions

This figure provides the eSDHC DDR50/DDR mode input AC timing diagram.

T SHCK

SDHC_CLK_SYNC_IN

T T
SHDIVKH SHDIXKH

SDHC_DAT
input

T T
SHCIVKH SHCIXKH

SDHC_CMD
input

Figure 19. eSDHC DDR50/DDR mode input AC timing diagram

This figure provides the eSDHC DDR50/DDR mode output AC timing diagram.

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Data Sheet: Technical Data 92 / 184
NXP Semiconductors
Electrical characteristics

T SHCK

SDHC_CLK

T
SHDKHOV

SDHC_DAT
output

T
SHDKHOX
T
SHCKHOV

SDHC_CMD
output

T
SHCKHOX

Figure 20. eSDHC DDR50/DDR mode output AC timing diagram

This table provides the eSDHC AC timing specifications for SDR104/eMMC HS200 mode (VDD=1.0V)

Table 31. eSDHC AC timing specifications (SDR104/HS200 mode) (VDD=1.0V) 2, 3, 5

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency fSHCK - - MHz -

SD/SDIO SDR104 mode - 200.0 -

eMMC HS200 mode - 200.0 -

SDHC_CLK duty cycle tSHSCK 45 55 % -

SDHC_CLK rise and fall times tSHCKR/ - 1.0 ns 1

tSHCKF

Output hold time (SDHC_CLK to TSHKHOX - - ns -

SDHC_CMD, SDHC_DATx valid)

SD/SDIO SDR104 mode 1.58 - 1

eMMC HS200 mode 1.6 - 1

Output delay time (SDHC_CLK to TSHKHOV - - ns -

SDHC_CMD, SDHC_DATx valid)

SD/SDIO SDR104 mode - 2.9 1

Table continues on the next page...

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Data Sheet: Technical Data 93 / 184
NXP Semiconductors
Electrical characteristics

Table 31. eSDHC AC timing specifications (SDR104/HS200 mode) (VDD=1.0V) 2, 3, 5 (continued)

Parameter Symbol Min Max Unit Notes

eMMC HS200 mode - 2.9 1

Input data window (UI) tSHIDV - - Unit -

interva
SD/SDIO SDR104 mode 0.5 - l 1

eMMC HS200 mode 0.475 - 1

1. CL = CBUS + CHOST + CCARD ≤ 15pF.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (R for rise) or
F ( F for fall).
3. See Figure 21. on page 96.
4. Board skew between clock and data pins should be less than 100ps
5. The AC timing specifications are based on the recommended operating conditions with EVDD /OVDD =1.8V, see
Recommended Operating Conditions

This table provides the eSDHC AC timing specifications for SDR104/eMMC HS200 mode (VDD=0.9V)

Table 32. eSDHC AC timing specifications (SDR104/HS200 mode)(VDD=0.9V) 2, 3, 5

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency fSHCK - - MHz -

SD/SDIO SDR104 mode - 166.6 -

eMMC HS200 mode - 166.6 -

SDHC_CLK duty cycle tSHSCK 45.0 55.0 % -

SDHC_CLK rise and fall times tSHCKR/ - 1.0 ns 1

tSHCKF

Output hold time (SDHC_CLK to TSHKHOX - - ns -

SDHC_CMD, SDHC_DATx valid)

SD/SDIO SDR104 mode 1.58 - 1

eMMC HS200 mode 1.6 - 1

Output delay time (SDHC_CLK to TSHKHOV - - ns -

SDHC_CMD, SDHC_DATx valid)

SD/SDIO SDR104 mode - 4.0 1

Table continues on the next page...

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Data Sheet: Technical Data 94 / 184
NXP Semiconductors
Electrical characteristics

Table 32. eSDHC AC timing specifications (SDR104/HS200 mode)(VDD=0.9V) 2, 3, 5 (continued)

Parameter Symbol Min Max Unit Notes

eMMC HS200 mode - 4.0 1

Input data window (UI) tSHIDV - - Unit -

interva
SD/SDIO SDR104 mode 0.5 - l 1

eMMC HS200 mode 0.475 - 1

1. CL = CBUS + CHOST + CCARD ≤ 15pF.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (R for rise) or
F ( F for fall).
3. See Figure 21. on page 96.
4. Board skew between clock and data pins should be less than 100ps
5. The AC timing specifications are based on the recommended operating conditions with EVDD /OVDD =1.8V, see
Recommended Operating Conditions

This figure provides the eSDHC SDR104/HS200 mode timing diagram.

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Data Sheet: Technical Data 95 / 184
NXP Semiconductors
Electrical characteristics

T
SHCK

SDHC_CLK

T
SHIDV

SDHC_CMD/
DATA
SDHC_DAT input

T
SHKHOV

SDHC_CMD/ SDHC_DAT
DATA DATA
output

T
SHKHOX

Figure 21. eSDHC SDR104/HS200 mode timing diagram

This table provides the eSDHC AC timing specifications for eMMC HS400 mode (VDD=1.0V).

Table 33. eSDHC AC timing specifications (HS400 mode) (VDD=1.0) 2, 3, 4, 5, 6

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency fSHCK - 150.0 MHz -

Output hold time (SDHC_CLK to TSHKHOX 0.75 - ns 1

SDHC_CMD, SDHC_DATx valid)

Output delay time (SDHC_CLK to TSHKHOV - 2.58 ns 1

SDHC_CMD, SDHC_DATx valid)

Data valid skew to DQS TSHRQV - 0.45 ns 1

Data hold skew to DQS TSHRQHX - 0.45 ns 1

Command valid skew to DQS TSHRQV_CM - 0.45 ns 1

Command hold skew to DQS TSHRQHX_C - 0.45 ns 1

Table continues on the next page...

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Data Sheet: Technical Data 96 / 184
NXP Semiconductors
Electrical characteristics

Table 33. eSDHC AC timing specifications (HS400 mode) (VDD=1.0) 2, 3, 4, 5, 6 (continued)

Parameter Symbol Min Max Unit Notes

DQS pulse width TSHDSPWS 1.97 - ns 1

Duty cycle distortion tSHSCK_DIS 0.0 0.3 ns 1

1. CL = CBUS + CHOST + CCARD ≤ 15pF.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (R for rise) or
F ( F for fall).
3. See Figure 22. on page 98.
4. See Figure 23. on page 99.
5. The AC timing specifications are based on the recommended operating conditions with OVDD =1.8V, see Recommended
Operating Conditions
6. Supoorted on eSDHC2 interface only

This table provides the eSDHC AC timing specifications for eMMC HS400 mode (VDD=0.9V).

Table 34. eSDHC AC timing specifications (HS400 mode)(VDD=0.9V) 2, 3, 4, 5, 6

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency fSHCK - 125.0 MHz -

Output hold time (SDHC_CLK to TSHKHOX 0.75 - ns 1

SDHC_CMD, SDHC_DATx valid)

Output delay time (SDHC_CLK to TSHKHOV - 3.25 ns 1

SDHC_CMD, SDHC_DATx valid)

Data valid skew to DQS TSHRQV - 0.45 ns 1

Data hold skew to DQS TSHRQHX - 0.45 ns 1

Command valid skew to DQS TSHRQV_CM - 0.45 ns 1

Command hold skew to DQS TSHRQHX_C - 0.45 ns 1

DQS pulse width TSHDSPWS 1.97 - ns 1

Duty cycle distortion tSHSCK_DIS 0.0 0.3 ns 1

Table continues on the next page...

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Data Sheet: Technical Data 97 / 184
NXP Semiconductors
Electrical characteristics

Table 34. eSDHC AC timing specifications (HS400 mode)(VDD=0.9V) 2, 3, 4, 5, 6 (continued)

Parameter Symbol Min Max Unit Notes

1. CL = CBUS + CHOST + CCARD ≤ 15pF.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (R for rise) or
F ( F for fall).
3. See Figure 22. on page 98.
4. See Figure 23. on page 99.
5. The AC timing specifications are based on the recommended operating conditions with OVDD =1.8V, see Recommended
Operating Conditions
6. Supoorted on eSDHC2 interface only

This figure provides the eSDHC HS400 mode input timing diagram.

Data Strobe
tSHDSPW tSHDSPW
VT

TSHRQV
TSHRQHX TSHRQV TSHRQHX

VOH
DAT[7:0]

VOL

TSHRQV_CMD TSHRQHX_CMD

VOH
CMD
OutPut
VOL

Figure 22. eSDHC HS400 mode input timing diagram

This figure provides the eSDHC HS400 mode output timing diagram.

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Data Sheet: Technical Data 98 / 184
NXP Semiconductors
Electrical characteristics

Tclk

SDHC_CLK

TSHKHOV

SDHC_CMD/SDHC_DAT
output

TSHKHOX

Figure 23. eSDHC HS400 mode output timing diagram

3.11 Ethernet interface (EMI, RGMII and IEEE Std 1588™)

This section describes the DC and AC electrical characteristics for the Ethernet controller, Ethernet management, and IEEE Std
1588 interfaces.

3.11.1 Ethernet management interface (EMI)

This section describes the electrical characteristics for the Ethernet management interface (EMI) interface.
™
The EMI1 interface timings are compatible with IEEE Std 802.3 clauses 22 and 45.

3.11.1.1 EMI DC electrical characteristics

This table provides the EMI1 DC electrical characteristics.

Table 35. EMI1 DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0 or VIN = OVIN) IIN - ±50 μA 3

Output high voltage (OVDD = min, IOH = VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V -

0.5 mA)

Table continues on the next page...

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Data Sheet: Technical Data 99 / 184
NXP Semiconductors
Electrical characteristics

Table 35. EMI1 DC electrical characteristics (OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

1. For recommended operating conditions, see Recommended Operating Conditions.

3.11.1.2 EMI AC timing specifications

This table provides the EMI1 AC timing specifications.

Table 36. EMI1 AC timing specifications 4, 5

Parameter Symbol Min Max Unit Notes

MDC frequency fMDC - 2.5 MHz 1

MDC clock pulse width high tMDCH 160.0 - ns -

MDC to MDIO delay tMDKHDX (Y x tenet_clk) - 3 (Y x tenet_clk) + 3 ns 2, 3, 4

MDIO to MDC setup time tMDDVKH 8.0 - ns -

MDIO to MDC hold time tMDDXKH 0.0 - ns -

1. This parameter is dependent on the Ethernet clock frequency. The EMDIO_CFG [MDIO_CLK_DIV] field determines the clock
frequency of the MgmtClk Clock EMI1_MDC.
2. tenet_clk is the Ethernet clock period.
3. MDIO timing is configurable by programming EMDIO_CFG register fields.
4. The default value of Y is 5. Y value is determined by EMDIO_CFG[NEG], EMDIO_CFG[MDIO_HOLD] and EMDIO[EHOLD].
It is recommended to use EMDIO_CFG[NEG]=1 for MDIO transactions.
5. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing
(MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to
the tMDC clock reference (K) going to the high (H) state or setup time.
6. See Figure 24. on page 101.

This figure shows the Ethernet management interface 1 timing diagram.

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Data Sheet: Technical Data 100 / 184
NXP Semiconductors
Electrical characteristics

tMDC

MDC

tMDCH

MDIO
(Input)

tMDDVKH

tMDDXKH

MDIO
(Output)

tMDKHDX

Figure 24. Ethernet management interface 1 timing diagram

3.11.2 Reduced media-independent interface (RGMII)

3.11.2.1 RGMII DC electrical characteristics

This table provides the DC electrical characteristics for the RGMII interface.

Table 37. RGMII DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN=0 or VIN = OVIN) IIN - ±50 μA 3, 4

Output high voltage (OVDD = min, IOH = VOH 1.35 - V 3

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V 3

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min VIL and max VIH values are based on the respective min and max OVIN values found in Recommended Operating
Conditions.
3. The symbol OVDD represents the recommended operating voltage of the supply referenced in Recommended Operating
Conditions.
4. The symbol OVIN represents the input voltage of the supply referenced in Recommended Operating Conditions.

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NXP Semiconductors
Electrical characteristics

3.11.2.2 RGMII AC timing specifications

This table provides the RGMII AC timing specifications.

Table 38. RGMII AC timing specifications 8, 9

Parameter Symbol Min Typ Max Unit Notes

Data to clock output skew (at tSKRGT_TX -500.0 0.0 500.0 ps 1

transmitter)

Data to clock input skew (at tSKRGT_R 1.0 - 2.6 ns 2, 3

receiver) X

Clock period duration tRGT 7.2 8.0 8.8 ns 4

Duty cycle for 10BASE-T and tRGTH/ 40.0 50.0 60.0 % 4, 5

100BASE-TX tRGT

Duty cycle for Gigabit tRGTH/ 45.0 50.0 55.0 % -

tRGT

Rise time (20%-80%) tRGTR - - 0.75 ns 6, 7

Fall time (20%-80%) tRGTF - - 0.75 ns 6, 7

1. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than 300 ppm.
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so,
additional PCB delay is probably not needed.
3. For 10/100 Mbps, the max value is unspecified.
4. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
5. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned
between.
6. Applies to inputs and outputs.
7. The system/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
8. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing.
Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing
skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
9. See Figure 25. on page 103.

This figure shows the RGMII AC timing and multiplexing diagrams.

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Data Sheet: Technical Data 102 / 184
NXP Semiconductors
Electrical characteristics

tRGT
tRGTH
GTX_CLK
(At MAC, output)
tSKRGT_TX tSKRGT_TX
TXD[8:5][3:0] TXD[8:5]
TXD[3:0] TXD[7:4]
TXD[7:4][3:0]
(At MAC, output)

TX_CTL TXD[4] TXD[9]

(At MAC, output) TXEN TXERR
PHY equivalent to tSKRGT_RX PHY equivalent to tSKRGT_RX

TX_CLK
(At PHY, input)

tRGT
tRGTH
RX_CLK
(At PHY, output)

RXD[8:5][3:0] RXD[8:5]
RXD[7:4][3:0] RXD[3:0] RXD[7:4]
(At PHY, output) PHY equivalent to tSKRGT_TX PHY equivalent to tSKRGT_TX

RX_CTL RXD[4] RXD[9]

RXDV RXERR
(At PHY, output)
tSKRGT_RX tSKRGT_RX
RX_CLK
(At MAC, input)

Figure 25. RGMII AC timing and multiplexing diagrams

3.11.3 IEEE 1588

3.11.3.1 IEEE 1588 DC electrical characteristics

This table provides the IEEE 1588 DC electrical characteristics.

Table 39. IEEE 1588 DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0 or VIN = OVDD) IIN - ±50 μA 3

Output high voltage (OVDD = min, IOH = VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V -

0.5 mA)

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 39. IEEE 1588 DC electrical characteristics (OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

1. For recommended operating conditions, see Recommended Operating Conditions.

3.11.3.2 IEEE 1588 AC timing specifications

This table provides the AC timing specifications for the IEEE 1588 interface.

Table 40. IEEE 1588 AC timing specifications 5, 6

Parameter Symbol Min Typ Max Unit Notes

EC1_1588_CLK_IN clock period t1588CLK 5.0 - TRX_CLK x 7 ns 1, 2

EC1_1588_CLK_IN duty cycle tT1588CLK 40.0 50.0 60.0 % 3

H/
tT1588CLK

EC1_1588_CLK_IN peak-to-peak tT1588CLKI - - 250.0 ps -

jitter NJ

Rise time EC1_1588_CLK_IN tT1588CLKI 1.0 - 2.0 ns -

(20% to 80%) NR

Fall time EC1_1588_CLK_IN tT1588CLKI 1.0 - 2.0 ns -

(80% to 20%) NF

EC1_1588_CLK_OUT clock tT1588CLK 5.0 - - ns 4

period OUT

EC1_1588_CLK_OUT duty cycle tT1588CLK 30.0 50.0 70.0 % -

OTH/
tT1588CLK
OUT

EC1_1588_PULSE_OUT1/2, tT1588OV 0 - 4.0 ns -

EC1_1588_ALARM_OUT1/2

EC1_1588_TRIG_IN1/2 pulse tT1588TRIG 2 x t1588CLK_MAX - - ns 1

width H

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 40. IEEE 1588 AC timing specifications 5, 6 (continued)

Parameter Symbol Min Typ Max Unit Notes

1. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns, respectively.
2. TRX_CLK is the maximum clock period of the ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.
3. This needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.
4. There are two input clock sources: TSEC_1588_CLK_IN and ENETC system clock. When using TSEC_1588_CLK_IN, the
minimum clock period is 2 x t T1588CLK.
5. See Figure 26. on page 105.
6. See Figure 27. on page 105.

This figure shows the data and command output AC timing diagram.

tT1588CLKOUT
tT1588CLKOUTH

TSEC_1588_CLK_OUT

tT1588OV

TSEC_1588_PULSE_OUT1/2
TSEC_1588_ALARM_OUT1/2

Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting.
Otherwise, it is counted starting at the falling edge.

Figure 26. IEEE 1588 output AC timing

This figure shows the data and command input AC timing diagram.

tT1588CLK

TSEC_1588_CLK_IN tT1588CLKH

TSEC_1588_TRIG_IN1/2

tT1588TRIGH

Figure 27. IEEE 1588 input AC timing

3.11.4 TSN SWITCH 1588

3.11.4.1 TSN SWITCH 1588 DC electrical characteristics

This table provides the SWITCH 1588 DC electrical characteristics.

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NXP Semiconductors
Electrical characteristics

Table 41. SWITCH 1588 DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0 or VIN = OVDD) IIN - ±50 μA 3

Output high voltage (OVDD = min, IOH = VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

3.11.4.2 TSN SWITCH 1588 AC timing specifications

This table provides the AC timing specifications for the SWITCH 1588 interface.

Table 42. SWITCH 1588 AC timing specifications

Parameter Symbol Min Max Unit

SWITCH_1588_DATn pulse width (configured tS1588TRIG 6.4 - ns

as input)

3.11.5 IEEE 1722

3.11.5.1 IEEE 1722 DC electrical characteristics

This table provides the IEEE 1722 DC electrical characteristics.

Table 43. IEEE 1722 DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0 or VIN = OVDD) IIN - ±50 μA 3

Output high voltage (OVDD = min, IOH = VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V -

0.5 mA)

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 43. IEEE 1722 DC electrical characteristics (OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

1. For recommended operating conditions, see Recommended Operating Conditions.

3.11.5.2 IEEE 1722 AC timing specifications

This table provides the AC timing specifications for the IEEE 1722 interface.

Table 44. IEEE 1722 AC timing specifications

Parameter Symbol Min Max Unit Notes

EC1_1722_DATn pulse width tT1722TRIG 5.0 - ns Programmed

(configured as input) through
PTCMRa[TMOD
E]

3.12 Flex serial peripheral interface (FlexSPI)

3.12.1 FlexSPI DC electrical characteristics

This table provides the DC electrical characteristics for the FlexSPI interface.

Table 45. FlexSPI DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (0V ≤ VIN ≤ OVDD) IIN - ±50 μA 3

Output high voltage (IOH = -100 μA) VOH 0.85xOVDD - V -

Output low voltage (IOH = 100 μA) VOL - 0.15xOVDD V -

1. For recommended operating conditions, see Recommended Operating Conditions.

3.12.2 FlexSPI AC timing specifications

This table provides the FlexSPI timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

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NXP Semiconductors
Electrical characteristics

Table 46. SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0 2, 3, 4

Parameter Symbol Min Max Unit Notes

Clock frequency FSCK - 100.0 MHz -

Duty cycle distortion Tdis -0.5 0.5 ns -

CS output hold time tFSKHOX2 (FLSHxCR1[TCSH - ns 1

]*T)- 0.54

CS output delay tFSKHOV2 ((FLSHxCR1[TCSS - ns 1

]+0.5)*T) - 0.74

Setup time for incoming data-without tFSIVKH 2.4 - ns -

DQS

Hold time for incoming data without DQS tFSIXKH 1.05 - ns -

Output data delay tFSKHOV 2.35 ns -

Output data hold tFSKHOX -1.35 - ns -

1. Refer Flash Control Register 1 (FLSHxyCR1) in QorIQ LS1028ARM for more details, where x: A or B, y: 1 or 2.
2. See Figure 29. on page 110.
3. See Figure 30. on page 111.
4. See Figure 31. on page 111.

This table provides the FlexSPI timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] =0x1 or 0x2

Table 47. SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x1 or 0x2 2, 3, 4

Parameter Symbol Min Max Unit Notes

Clock frequency FSCK - 100.0 MHz -

Duty cycle distortion Tdis -0.5 0.5 ns -

CS output hold time tFSKHOX2 (FLSHxCR1[TCSH - ns 1

]*T) - 0.54

CS output delay tFSKHOV2 ((FLSHxCR1[TCSS - ns 1

]+0.5)*T) - 0.74

Setup time for incoming data-without tFSIVKH 2.4 - ns -

DQS

Hold time for incoming data without DQS tFSIXKH 1.05 - ns -

Output data delay tFSKHOV 2.35 ns -

Output data hold tFSKHOX -1.35 - ns -

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NXP Semiconductors
Electrical characteristics

Table 47. SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x1 or 0x2 2, 3, 4 (continued)

Parameter Symbol Min Max Unit Notes

This table provides the FlexSPI timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] =0x1 or 0x2

Table 48. DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x1, or 0x2 3, 4, 5

Parameter Symbol Min Max Unit Notes

Clock frequency FSCK - 75.0 MHz -

Duty cycle distortion Tdis -0.5 0.5 ns -

CS output hold time tFSKHOX2 ((FLSHxCR1[TCSH - ns 1

]+0.5)* T/2 ) - 0.54

CS output delay tFSKHOV2 ((FLSHxCR1[TCSS - ns 1

]+0.5)* T/2) - 0.74

Data Valid Window tFSIDVW 0.3 - UI 2

Output data delay tFSKHOV/ - 3.96 ns -

tFSKLOV

Output data hold tFSKHOX/ 2.85 - ns -

tFSKLOX

1. Refer Flash Control Register 1 (FLSHxyCR1) in QorIQ LS1028ARM for more details, where x: A or B, y: 1 or 2.
2. For DDR, Unit Internval (UI) is half of period. For example, 5 ns for 100 MHz
3. See Figure 29. on page 110.
4. See Figure 30. on page 111.
5. See Figure 32. on page 112.

This table provides the FlexSPI timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] =0x3

Table 49. DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3 2, 3, 4, 5

Parameter Symbol Min Max Unit Notes

Clock frequency FSCK - 125.0 MHz -

Duty cycle distortion Tdis -0.5 0.5 ns -

CS output hold time tFSKHOX2 ((FLSHxCR1[TCSH - ns 1

]+0.5)* T/2 ) - 0.54

Table continues on the next page...

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Electrical characteristics

Table 49. DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3 2, 3, 4, 5 (continued)

Parameter Symbol Min Max Unit Notes

CS output delay tFSKHOV2 ((FLSHxCR1[TCSS - ns 1

]+0.5)* T/2) - 0.74

DQS to data valid tFSIVKH/ -0.7 0.7 ns -

tFSIVKL

DQS to data invalid tFSIIVKH/ -0.7 0.9 ns -

tFSIIVKL

Output data delay tFSKHOV/ - 2.57 ns -

tFSKLOV

Output data hold tFSKHOX/ 1.4 - ns -

tFSKLOX

1. Refer Flash Control Register 1 (FLSHxyCR1) in QorIQ LS1028ARM for more details, where x: A or B, y: 1 or 2.
2. See Figure 29. on page 110.
3. See Figure 30. on page 111.
4. See Figure 32. on page 112.
5. See Figure 28. on page 110.

This figure shows the FlexSPI data input timing in DDR mode with an external DQS.

XSPI_A_SCK
XSPI_B_SCK

XSPI_A_DQS
XSPI_B_DQS
tFSIVKH tFSIVKL tFSIIVKH
tFSIIVKL

Input Data

Figure 28. FlexSPI input AC timing - DDR mode with an external DQS

This figure shows the AC test load for the FlexSPI interface.

Output Z0= 50 Ω Respective

supply / 2
RL = 50 Ω

Figure 29. AC test load for FlexSPI

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Electrical characteristics

This figure shows the FlexSPI clock input timing diagram.

t HIGH

FlexSPI clock

t LOW

Figure 30. FlexSPI clock input timing diagram

This figure shows the FlexSPI AC timing diagram for SDR mode.

XSPI_A_SCK
XSPI_B_SCK
tFSIXKH
tFSIVKH
Input S igna ls :

tFSKHOX
tFSKHOV
Output S igna ls :

tFSKHOV2 tFSKHOX2
XSPI_A_CS0
XSPI_A_CS1
XSPI_B_CS0
XSPI_B_CS1

Figure 31. FlexSPI SDR mode AC timing diagram

This figure shows the FlexSPI AC timing diagram for DDR mode 1 and 2.

Freescale Semiconductor Freescale Confidential Proprietary 3

Preliminary—Subject to Change Without Notice
Freescale Internal Use Only

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NXP Semiconductors
Electrical characteristics

XSPI_A_SCK
XSPI_B_SCK
tFSIDVW

Input Signals:

tFSIDVW tFSKHOV
tFSKLOX
Output Signals:

tFSKLOV
tFSKHOV2 tFSKHOX tFSKHOX2
XSPI_A_CS0_B
XSPI_A_CS1_B
XSPI_B_CS0_B
XSPI_B_CS1_B

Figure 32. FlexSPI DDR mode 1 and 2 AC timing diagram

3.13 Flextimer interface

This section describes the DC and AC electrical characteristics for the Flextimer interface. There are Flextimer pins on various
power supplies in this device.

3.13.1 FlexTimer DC electrical characteristics

This table provides the DC electrical characteristics for Flextimer.

Table 50. FlexTimer DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0V or VIN = OVDD) IIN - ±50 μA 3

Output high voltage (OVDD = min, IOH = VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

3.13.2 FlexTimer AC timing specifications

This table provides theAC timing specifications for Flextimer.

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NXP Semiconductors
Electrical characteristics

Table 51. FlexTimer AC timing specifications 2

Parameter Symbol Min Max Unit Notes

Flextimer inputs - minimum pulse width tPIWID 20.0 - ns 1

1. Flextimer inputs and outputs are asynchronous to any visible clock. Flextimer outputs should be synchronized before use by
any external synchronous logic. Flextimer inputs are required to be valid for at least tPIWID to ensure proper operation.
2. See Figure 33. on page 113.

This figure provides the AC test load for the Flextimer.

Output Z0= 50 Ω (L/O) VDD/2

RL = 50 Ω

Figure 33. Flextimer AC test load

3.14 General purpose input/output (GPIO)

3.14.1 GPIO DC electrical characteristics

This table provides the DC electrical characteristics for the GPIO interface.

Table 52. GPIO DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0V or VIN= OVDD) IIN - ±50 μA 3

Output high voltage (OVDD = min, IOH = VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

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NXP Semiconductors
Electrical characteristics

3.14.2 GPIO AC timing specifications

This table provides the GPIO input and output AC timing specifications.

Table 53. GPIO AC timing specifications 2

Parameter Symbol Min Max Unit Notes

GPIO inputs-minimum pulse width tPIWID 20.0 - ns 1

1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs must be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
2. See Figure 34. on page 114.

The figure below provides the AC test load for the GPIO.

Output Z0= 50 Ω Respective

supply / 2
RL = 50 Ω

Figure 34. GPIO AC test load

3.15 Display Port/eDP interface (DP/eDP)

This section describes the AC and DC electrical characteristics for the Display Port/eDP interface.

3.15.1 eDP/DP DC electrical characteristics

This table provides the DC electrical characteristics for eDP transmitter module.

Table 54. eDP transmitter DC electrical characteristics (DP_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential Peak-to-peak Output VTX-DIFFp- 180.0 200.0 220.0 mV 2, 3

Voltage Swing Level 0 p-Level0

Differential Peak-to-peak Output VTX-DIFFp- 225.0 250.0 275.0 mV 2, 3

Voltage Swing Level 1 p-Level1

Differential Peak-to-peak Output VTX-DIFFp- 270.0 300.0 330.0 mV 2, 3

Voltage Swing Level 2 p-Level2

Differential Peak-to-peak Output VTX-DIFFp- 315.0 350.0 385.0 mV 2, 3

Voltage Swing Level 3 p-Level3

Table continues on the next page...

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Electrical characteristics

Table 54. eDP transmitter DC electrical characteristics (DP_OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

Differential Peak-to-peak Output VTX-DIFFp- 360.0 400.0 440.0 mV 2, 3

Voltage Swing Level 4 p-Level4

Differential Peak-to-peak Output VTX-DIFFp- 405.0 450.0 495.0 mV 2, 3

Voltage Swing Level 5 p-Level5

Maximum allowed Differential VTX-DIFFP- - - 1380.0 mV 4

Peak-to- Peak Output Voltage P-MAX

Transmit lane short-circuit current ITX-SHORT - - 50.0 mA 5

AC coupling capacitor CTX 75.0 - 265.0 nF 5, 6

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Steps between VTX-DIFF-p-p voltages must be monotonic.
3. Specified at the package pins.
4. Allows eDP Source devices to support differential signal voltages compatible with eDP v1.3 (and lower) devices and designs.
5. From DP1.3
6. Use 100nF typical value

This table provides the DC electrical characteristics for DP transmitter module.

Table 55. DP transmitter DC electrical characteristics (DP_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential Peak-to-peak Output VTX-DIFFp- 340.0 400.0 460.0 mV 2, 3, 4

Voltage Swing Level 0 p-Level0

Differential Peak-to-peak Output VTX-DIFFp- 510.0 600.0 680.0 mV 2, 3, 4

Voltage Swing Level 1 p-Level1

Differential Peak-to-peak Output VTX-DIFFp- 690.0 800.0 920.0 mV 2, 3, 4

Voltage Swing Level 2 p-Level2

Differential Peak-to-peak Output VTX-DIFFp- 850.0 1200.0 1380.0 mV 2, 3, 4

Voltage Swing Level 3 p-Level3

Transmit lane short-circuit current ITX-SHORT - - 50.0 mA 5

Pre-emphasis Level 0 VTX- - 0.0 - dB 6

PREEMP-
RATIO-
Level0

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Electrical characteristics

Table 55. DP transmitter DC electrical characteristics (DP_OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

Pre-emphasis Level 1 VTX- 2.8 3.5 4.2 dB 6

PREEMP-
RATIO-
Level1

Pre-emphasis Level 2 VTX- 4.8 6.0 7.2 dB 6

PREEMP-
RATIO-
Level2

Pre-emphasis Level 3 VTX- 7.5 9.5 11.4 dB 7

PREEMP-
RATIO-
Level3

Pre-emphasis Post Cursor2 Level VTX- - 0.0 - dB 8

0 PREEMP-
POST2-
RATIO-
Level0

Pre-emphasis Post Cursor2 Level VTX- -1.1 -0.9 -0.7 dB 8

1 PREEMP-
POST2-
RATIO-
Level1

Pre-emphasis Post Cursor2 Level VTX- -2.3 -1.9 -1.5 dB 8

2 PREEMP-
POST2-
RATIO-
Level2

Pre-emphasis Post Cursor2 Level VTX- -3.7 -3.1 -2.5 dB 8

3 PREEMP-
POST2-
RATIO-
Level3

AC coupling capacitor CTX 75.0 - 265.0 nF 5, 9

TX DC Common Mode Voltage VTX-DC- 0.0 - 2.0 V 10

TX AC Common Mode Voltage for VTX-AC- - - 20.0 mV -

HBR and RBR CM rms

TX AC Common Mode Voltage for VTX-AC- - - 30.0 mV -

HBR2 CM rms

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 55. DP transmitter DC electrical characteristics (DP_OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Steps between VTX-DIFF-p-p voltages must be monotonic.
3. Specified at the package pins.
4. Voltage Swing Level 3 for RBR and HBR is optional.
5. From DP1.3
6. Support for Pre-emphasis Levels 0, 1, and 2 is required.
7. Support for Pre-emphasis Level 3 is optional.
8. At TP1 (refer eDP spec 1.4)
9. Use 100nF typical value
10. Common mode voltage is equal to Vbias_TX voltage.

This table provides the DP_HPD DC electrical characteristics.

Table 56. DP_HPD DC electrical characteristics (DP_OV DD = 1.8V) 1

Parameter Min Typ Max Unit

DP_HPD Voltage 2.25 - 3.6 V

Hot plug detection threshold 2.0 - - V

Hot unplug detection threshold - - 0.8 V

Input leakage current - 2.4 3.8 uA

1. For recommended operating conditions, see Recommended Operating Conditions.

This table lists the eDP/DPAUXchannel electrical specifications.

Table 57. eDP/DP AUX channel electrical specifications (DP_OV DD = 1.8V) 1, 3, 4

Parameter Symbol Min Typ Max Unit Notes

Manchester transaction unit UIMAN 0.4 - 0.6 us 2, 3, 4

interval

Number of pre-charge pulses Pre- 10.0 - 16.0 - 5

charge
Pulses

AUX CH bus park time TAUX-BUS- 10.0 - - ns 6

PARK

AUX Peak-to-peak differential VAUX- 0.18 0.2 1.38 V 7

voltage at TX package pins (TP1) DIFFP-P
for eDP1.4

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Electrical characteristics

Table 57. eDP/DP AUX channel electrical specifications (DP_OV DD = 1.8V) 1, 3, 4 (continued)

Parameter Symbol Min Typ Max Unit Notes

AUX Peak-to-peak differential VTX_AUX- 0.29 - 0.4 V 7

voltage at TX package pins (TP1) DIFFP-P
when transmitting for DP 1.3
specification

AUX Peak-to-peak differential VRX_AUX- 0.29 - 1.38 V 7

voltage at TX package pins (TP1) DIFFP-P
when receiving for DP 1.3
specification

AUX channel DC common mode VAUX-DC- 0.0 - 1.2 V -

voltage for eDP 1.4 specification CM-eDP

AUX channel DC common mode VAUX-DC- 0.0 - 2.0 V -

voltage for DP 1.3 specification CM-DP

AUX AC-coupling capacitor CTX 75.0 - 200.0 nF 8

AUX short circuit current limit IAUX_SHO - - 90.0 mA -

AUX turn around common mode VAUX- - - 0.3 V 9

voltage TURN-CM

AUX CH termination DC VAUX_TER - 100.0 - ohm -

resistance M_R

Maximum allowable UI variation Tcycle-to- - - 0.08 UI 10, 11

within a single transaction of a cycle jitter
transmitting device

Maximum allowable variation for Tcycle-to- - - 0.04 UI 12, 11

adjacent bit times within a single cycle jitter
transaction of a transmitting
device

Maximum allowable UI variation Tcycle-to- - - 0.1 UI 13, 11

within a single transaction of a cycle jitter
receiving device

Maximum allowable variation for Tcycle-to- - - 0.05 UI 14, 11

adjacent bit times within a single cycle jitter
transaction of a receiving device

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Electrical characteristics

Table 57. eDP/DP AUX channel electrical specifications (DP_OV DD = 1.8V) 1, 3, 4 (continued)

Parameter Symbol Min Typ Max Unit Notes

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Results in the bit rate of 1Mbps including the overhead of Manchester-II coding.
3. See Figure 35. on page 119.
4. See Figure 36. on page 120.
5. Each pulse is a 0 in Manchester-II code.
6. Period after the AUX CH STOP condition for which the bus is parked.
7. VAUX-DIFFP-P = 2 × | VDP_AUX_P - VDP_AUX_M |
8. Use 100nF typical value
9. Steady state common mode voltage shift between transmit and receive modes of operation
10. Equal to 48ns maximum. The transmitting device is an upstream device for a Request transaction and a downstream device
for a Reply transaction.
11. At TP2 (refer eDP spec 1.4)
12. Equal to 24ns maximum. The transmitting device is an upstream device for a Request transaction and a downstream device
for a Reply Transaction.
13. Equal to 60ns maximum. The transmitting device is an upstream device for a Request transaction and a downstream device
for a Reply Transaction.
14. Equal to 30ns maximum. The transmitting device is an upstream device for a Request transaction and a downstream device
for a Reply Transaction.

This figure illustrates the Aux CH EYE mask at the transmitting device's package pins and vertices values

2 3

1
4

6 5

Point Time (UI) Minimum Voltage Value at Six Vertices (mV)

1 0.01 0
2 0.11 90
3 0.89 90
4 0.99 0
5 0.89 -90
6 0.11 -90
Note: For eDP 1.4 at TP1

Figure 35. Aux CH EYE mask for manchester-II transactions at transmitting device's package

This figure illustrates mask vertices for Aux CH EYE at connector pins of TX device

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NXP Semiconductors
Electrical characteristics

2 3

1
4

6 5

Point Time (from Eye Center) (ns) Minimum Voltage Value at Six Vertices (mV)

1 -185 0
2 -135 145
3 135 145
4 185 0
5 135 -145
6 -135 -145
Note: For DP 1.3 at TP2

Figure 36. Aux CH EYE mask at connector pins of TX device

3.15.2 eDP/DP AC timing specifications

This table provides the DP_HPD AC timing specifications.

Table 58. DP_HPD AC timing specifications

Parameter Symbol Min Max Unit Notes

IRQ_HPD Pulse/glitch detection tHPD_WIDTH 0.25 - ms 1

threshold for Upstream device

IRQ_HPD Pulse /Hot Unplug event tHPD_UNPLU 2.0 - ms 2

detection threshold for Upstream device G_WIDTH

IRQ_HPD minimum spacing tHPD_MIN_SP 2.0 - ms 3

ACING

1. When the pulse width is narrower than this threshold, the upstream device must ignore the pulse as a glitch.
2. When the pulse width is narrower than this threshold, the upstream device must read the Link/Sink Device Status field and
take corrective action. When the pulse width is wider than this threshold, it is likely to be actual cable unplug/re-plug event.
Upon detecting HPD high, the upstream device must read the Link/Sink Device Status field, and if the link is unstable, read the
Link/Sink Capability field of the DPCD before initiating Link Training.
3. Minimum Time after asserting HPD at the end of IRQ_HPD before de-asserting HPD at the start of the following IRQ_HPD.

This table provides the eDP/DP transmitter output AC timing specifications.

Table 59. eDP/DP transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit interval for BR1 UIBR1 - 617.3 - ps 1

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Electrical characteristics

Table 59. eDP/DP transmitter AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

Unit interval for BR2 UIBR2 - 463.0 - ps 1

Unit interval for BR3 UIBR3 - 411.5 - ps 1

Unit interval for BR4 UIBR4 - 370.4 - ps 1

Unit interval for BR5 UIBR5 - 308.6 - ps 1

Unit interval for BR6 UIBR6 - 231.5 - ps 1

Unit interval for BR7 UIBR7 - 185.0 - ps 1

Deterministic jitter DJMAX - - 0.17 x UI ps 2, 3

Total jitter TJMAX - - 0.27 x UI ps 2, 3

Lane Intra-pair output skew LTX- - - 20.0 ps 4, 5

SKEWINTR
A_PAIR
CHIP

Lane Intra-pair Rise-fall Time TTX- - - 5.0 % 6, 4

Mismatch RISE_FALL
_MISMATC
H_DIFF

D+/D- TX Output Rise/Fall Time TTX- 50.0 - 130.0 ps 7, 4

RISE/TTX-
FALL

Minimum TX EYE Width at TP1 TTXEYE_R 0.82 - - UI 8

Minimum TX EYE Width at TP1 TTXEYE_H 0.72 - - UI 9

Minimum TX EYE Width at TP1 TTXEYE_H 0.73 - - UI 10

BR2

Maximum time between the jitter TTX-EYE- - - 0.09 UI 8

median and maximum deviation MEDIANto-
from the median at TP1 MAX-
JITTER_RB
R

Maximum time between the jitter TTX-EYE- - - 0.147 UI 9

median and maximum deviation MEDIANto-
from the median at TP1 MAX-
JITTER_HB
R

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Electrical characteristics

Table 59. eDP/DP transmitter AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

Maximum time between the jitter TTX-EYE- - - 0.135 UI 10

median and maximum deviation MEDIANto-
from the median at TP1 MAX-
JITTER_HB
R2

Differential Return Loss at RLTX-DIFF 12.0 - - dB 4, 11

0.675GHz

Differential Return Loss at RLTX-DIFF 9.0 - - dB 4, 11

1.35GHz

Clock Jitter Rejection Bandwidth FTX- - - 4.0 MHz 12

REJECTION
BW

1. High Limit= +300ppm; Low Limit= -5300ppm. For constant (non-SSC) Frequency
2. Based on D10.2 pattern
3. The EYE diagram must be measured with a Compliance Test Load and a signal analyzer that includes a Link CDR emulation
function matching the DisplayPort receiver Jitter Tolerance Mask specifications
4. At TP1 (refer eDP spec 1.4)
5. Applies to all supported lanes.
6. D+ rise to D- fall mismatch and D+ fall to D- rise mismatch.
7. 20% to 80%
8. For RBR
9. For HBR
10. For HBR2
11. Straight loss line between 0.675 GHz and 1.35 GHz
12. Transmitter jitter must be measured at source connector pins using a signal analyzer that has a second-order PLL with
closed-loop tracking bandwidth of 20MHz (for D10.2 pattern) and damping factor of 1.428.

This table provides the AC requirements for eDP reference clocks.

Table 60. DP_REFCLK_P and DP_REFCLK_N input clock requirements. 8

Parameter Symbol Min Typ Max Unit Notes

DP_REFCLK_P and tDP_REFCL - 27.0 - MHz 1

DP_REFCLK_N frequency K

DP_REFCLK_P and tDP_REFCL -300.0 - 300.0 ppm -

DP_REFCLK_N clock frequency K_TOL
tolerance

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Electrical characteristics

Table 60. DP_REFCLK_P and DP_REFCLK_N input clock requirements. 8 (continued)

Parameter Symbol Min Typ Max Unit Notes

Differential peak-to-peak 0.5 - 2.2 V 2

amplitude

External AC coupling capacitor CTX 100.0 - - nF 3

DP_REFCLK_P and tDP_REFCL 45.0 - 55.0 % -

DP_REFCLK_N reference clock K_DUTY
duty cycle

DP_REFCLK_P and tR/tF - - 400.0 ps 4

DP_REFCLK_N rise and fall time

Input deterministic Jitter tDP_REFCL - - 9.0 ps 5

K_DJ

Input Phase Noise tDP_REFCL - - -125 dBc/Hz max dBC/ 6

K_PN @ 10 kHz Hz

-130 dBc/Hz max

@ 100 kHz

-140 dBc/Hz max

@ 1 MHz

-140 dBc/Hz max

@ 10 MHz

Input Random Jitter tDP_REFCL - - 2.963 ps 7

K_RJ

1. Non-SSC pure tone clock

2. At Package pin
3. Place before receiver pins
4. 20% to 80%
5. Over a band of 10KHz to 10MHz
6. The noise floor density range is from 10 KHz to 10 MHz
7. The integrated jitter range is from 10 KHz to 10 MHz
8. HCSL clock receiver

3.16 High-speed serial interfaces (HSSI)

The chip features a Serializer/Deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The
SerDes interface can be used for PCI Express, SGMII, 1000Base-KX, USXGMII and serial ATA (SATA) data transfers.
This section describes the most common portion of the SerDes DC electrical specifications: the DC requirement for SerDes
reference clocks. The SerDes data lane's transmitter (Tx) and receiver (Rx) reference circuits are also described.

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Electrical characteristics

3.16.1 Signal terms definitions

The SerDes uses differential signaling to transfer data across the serial link. This section defines the terms that are used in the
description and specification of differential signals.
This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This
figure shows the waveform for either a transmitter output (SD_TXn_P and SD_TXn_N) or a receiver input (SD_RXn_P and
SD_RXn_N). Each signal swings between A volts and B volts where A > B.

SD_TXn_P or
SD_RXn_P
A Volts

Vcm= (A + B)/2

SD_TXn_N or
SD_RXn_N
B Volts

Differential swing, VID orVOD = A - B

Differential peak voltage, VDIFFp = |A - B|
Differential peak-to-peak voltage, VDIFFpp =2 x VDIFFp (not shown)

Figure 37. Differential voltage definitions for transmitter or receiver

Using this waveform, the definitions are as described in the following list. To simplify the illustration, the definitions assume that
the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment:

Single-Ended Swing The transmitter output signals and the receiver input signals SD_TXn_P, SD_TXn_N, SD_RXn_P and
SD_RXn_N each have a peak-to-peak swing of A - B volts. This is also referred to as each signal
wire's single-ended swing.
Differential Output The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the
Voltage, VOD (or two complementary output voltages: VSD_TX n_P - VSD_TXn_N. The VOD value can be either positive or
Differential Output negative.
Swing)

Differential Input The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two
Voltage, V ID (or complementary input voltages: VSD_RXn_P- VSD_RXn_N. The VID value can be either positive or
Differential Input negative.
Swing)

Differential Peak The peak value of the differential transmitter output signal or the differential receiver input signal is
Voltage, V DIFFp defined as the differential peak voltage, VDIFFp = |A - B| volts.
Differential Peak-to- Because the differential output signal of the transmitter and the differential input signal of the receiver
Peak, V DIFFp-p each range from A - B to -(A - B) volts, the peak-to-peak value of the differential transmitter output
signal or the differential receiver input signal is defined as differential peak-to-peak voltage, VDIFFp-p =
2 x VDIFFp = 2 x |(A - B)| volts, which is twice the differential swing in amplitude, or twice the
differential peak. For example, the output differential peak-to-peak voltage can also be calculated as
VTX-DIFFp-p = 2 x |VOD|.
Differential The differential waveform is constructed by subtracting the inverting signal (SD_TXn_N, for example)
Waveform from the non-inverting signal (SD_TXn_P, for example) within a differential pair. There is only one
signal trace curve in a differential waveform. The voltage represented in the differential waveform is
not referenced to ground. See Figure 42. on page 130 as an example for differential waveform.
Common Mode The common mode voltage is equal to half of the sum of the voltages between each conductor of a
Voltage, V cm balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSD_TXn_P +
VSD_TXn_N) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two complementary output voltages

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Electrical characteristics

within a differential pair. In a system, the common mode voltage may often differ from one
component's output to the other's input. It may be different between the receiver input and driver
output circuits within the same component. It is also referred to as the DC offset on some occasions.

To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common
mode voltage of 2.25 V and outputs, TD and TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage
swing of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because the
differential signaling environment is fully symmetrical in this example, the transmitter output's differential swing (VOD) has the
same amplitude as each signal's single-ended swing. The differential output signal ranges between 500 mV and -500 mV. In
other words, VOD is 500 mV in one phase and -500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The
peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

3.16.2 SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N.
SerDes may be used for various combinations of the following IP blocks based on the RCW Configuration field SRDS_PRTCLn:
• SGMII (1.25 Gbps), QSGMII (5 Gbps)
• PCIe (2.5 GT/s, 5 GT/s and 8 GT/s )
• SATA (1.5 Gbps, 3.0 Gbps, and 6.0 Gbps)
The following sections describe the SerDes reference clock requirements and provide application information.

3.16.2.1 SerDes spread-spectrum clock source recommendations

SDn_REF_CLKn_P and SDn_REF_CLKn_N are designed to work with spread-spectrum clocking for the PCI Express protocol
only with the spreading specification defined in Table 61. SerDes spread-spectrum clock source recommendations 1 on page
125. When using spread-spectrum clocking for PCI Express, both ends of the link partners should use the same reference clock.
For best results, a source without significant unintended modulation must be used.
The SerDes transmitter does not support spread-spectrum clocking for the SATA protocol. The SerDes receiver does support
spread-spectrum clocking on receive, which means the SerDes receiver can receive data correctly from a SATA serial link partner
using spread-spectrum clocking.
Spread-spectrum clocking cannot be used if the same SerDes reference clock is shared with other non-spread-spectrum-
supported protocols. For example, if spread-spectrum clocking is desired on a SerDes reference clock for the PCI Express
protocol and the same reference clock is used for any other protocol, such as SATA or SGMII because of the SerDes lane usage
mapping option, spread-spectrum clocking cannot be used at all.
This table provides the source recommendations for SerDes spread-spectrum clocking.

Table 61. SerDes spread-spectrum clock source recommendations 1

Parameter Min Max Unit Notes

Frequency modulation 30 33 kHz —

Frequency spread +0 -0.5 % 2

Notes:
1. At recommended operating conditions. See Recommended Operating Conditions.
2. Only down-spreading is allowed.

3.16.2.2 SerDes reference clock receiver characteristics

This figure shows a receiver reference diagram of the SerDes reference clocks.

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NXP Semiconductors
Electrical characteristics

50 Ω

SDn_REF_CLKn_P

Input
amp

SDn_REF_CLKn_N

50 Ω

Figure 38. Receiver of SerDes reference clocks

The characteristics of the clock signals are as follows:

• The SerDes transceiver's core power supply voltage requirements (SVDD) are as specified in Recommended Operating
Conditions.
• The SerDes reference clock receiver reference circuit structure is as follows:
— The SDn_REF_CLKn_P and SDn_REF_CLKn_N are internally AC-coupled differential inputs as shown in Figure 38.
on page 126. Each differential clock input (SDn_REF_CLKn_P or SDn_REF_CLKn_N) has on-chip 50-Ω termination
to SGNDn followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the differential mode and single-
ended mode descriptions in Signal terms definitions on page 124 for detailed requirements.
• The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is
not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input is
AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V ÷ 50 = 8 mA)
while the minimum common mode input level is 0.1 V above SGNDn. For example, a clock with a 50/50 duty cycle
can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0-0.8 V), such that
each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at
400 mV.
— If the device driving the SDn_REF_CLKn_P and SDn_REF_CLKn_N inputs cannot drive 50 Ω to SGNDn DC or the
drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip.
• The input amplitude requirement is described in detail in the following sections.

3.16.2.3 DC-level requirement for SerDes reference clocks

The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below.
Differential mode:
• The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-to-peak (or between
200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended
swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-
coupled connection.

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Electrical characteristics

• For an external DC-coupled connection, as described in SerDes reference clock receiver characteristics on page 125, the
maximum average current requirements sets the requirement for average voltage (common mode voltage) as between 100
mV and 400 mV. Figure 39. on page 127 shows the SerDes reference clock input requirement for DC-coupled connection
scheme.

200 mV < Input amplitude or differential peak < 800 mV

SDn_REF_CLKn_P Vmax < 800mV

100 mV < Vcm < 400 mV

SDn_REF_CLKn_N Vmin > 0 V

Figure 39. Differential reference clock input DC requirements (external DC-coupled)

• For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Because the
external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in
different common mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode
voltage set to GND. Each signal wire of the differential inputs is allowed to swing below and above the common mode voltage
(GND). Figure 40. on page 127 shows the SerDes reference clock input requirement for AC-coupled connection scheme.

200 mV < Input amplitude or differential peak < 800 mV

SDn_REF_CLKn_P Vmax < Vcm + 400 mV

Vcm

Vmin > Vcm - 400 mV

SDn_REF_CLK_N

Figure 40. Differential reference clock input DC requirements (external AC-coupled)

Single-ended mode:
• The reference clock can also be single-ended. The SDn_REF_CLKn_P input amplitude (single-ended swing) must be
between 400 mV and 800 mV peak-to-peak (from VMIN to VMAX) with SDn_REF_CLKn_N either left unconnected or tied to
ground.
• The SDn_REF_CLKn_P input average voltage must be between 200 and 400 mV. Figure 41. on page 128 shows the SerDes
reference clock input requirement for single-ended signaling mode.
• To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled externally. For the
best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase (SDn_REF_CLKn_N)
through the same source impedance as the clock input (SDn_REF_CLKn_P) in use.

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Electrical characteristics

400 mV < SD_REF_CLKn input amplitude < 800 mV

SDn_REF_CLKn_P

SDn_REF_CLKn_N

Figure 41. Single-ended reference clock input DC requirements

3.16.2.4 SerDes reference clocks AC timing specifications

For protocols with data rates up to 5 Gb/s where there is no reference clock jitter specification (ex: SGMII), use the PCIe 2.5G
clock jitter requirements.
For protocols with data rates greater than 5 Gb/s and less than 8 Gb/s where there is no reference clock jitter specification, use
the PCIe 5G clock jitter requirements.
For protocols with data rates greater than 8 Gb/s and less than 16 Gb/s where there is no reference clock jitter specification (ex:
USXGMII-10.3125G), use the PCIe 8G or XFI clock jitter requirements.
Use the protocol’s reference clock frequency tolerance specification (ex: +/-100 ppm for SGMII/USXGMII/1000Base-KX, +/-300
ppm for PCIe and +/-350 ppm for SATA).
This table defines the AC requirements for SerDes reference clocks for PCI Express. SerDes reference clocks need to be verified
by the customer’s application design.

Table 62. SD1_REF_CLKn_P and SD1_REF_CLKn_N input clock requirements

Parameter Symbol Min Typ Max Unit Notes

SD1_REF_CLKn_P/ tCLK_REF - 100/125 - MHz 1

SD1_REF_CLKn_N frequency
range

PCI Express SD1_REF_CLKn_P/ tCLK_TOL -300.0 - 300.0 ppm 2

SD1_REF_CLKn_N clock
frequency tolerance

SGMII SD1_REF_CLKn_P/ tCLK_TOL -100.0 - 100.0 ppm 3

SD1_REF_CLKn_N clock
frequency tolerance

SD1_REF_CLKn_P/ tCLK_DUTY 40.0 50.0 60.0 % 4

SD1_REF_CLKn_N reference
clock duty cycle

SD1_REF_CLKn_P/ tCLK_DJ - - 42.0 ps -

SD1_REF_CLKn_N max
deterministic peak-to-peak jitter at
10 -6 BER

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Table 62. SD1_REF_CLKn_P and SD1_REF_CLKn_N input clock requirements (continued)

Parameter Symbol Min Typ Max Unit Notes

SD1_REF_CLKn_P/ tCLK_TJ - - 86.0 ps 5

SD1_REF_CLKn_N total
reference clock jitter at 10 -6 BER
(peak-to-peak jitter at refClk input)

PCI Express 5 GT/s tREFCLK- - - 3.0 ps 6

SD1_REF_CLKn_P/ LF-RMS RMS
SD1_REF_CLKn_N 10 kHz to 1.5
MHz RMS jitter

PCI Express 5 GT/s tREFCLK- - - 3.1 ps 6

SD1_REF_CLKn_P/ HF-RMS RMS
SD1_REF_CLKn_N > 1.5 MHz to
Nyquist RMS jitter

SD1_REF_CLKn_P/ tCLKRR/ 0.6 - 4.0 V/ns 7, 8

SD1_REF_CLKn_N rising/falling tCLKFR
edge rate

PCI Express 8 GT/s tREFCLK- - - 1.0 ps 9

SD1_REF_CLKn_P/ RMS-DC RMS
SD1_REF_CLKn_N RMS
reference clock jitter

Differential input high voltage VIH 150.0 - - mV 4

Differential input low voltage VIL - - -150.0 mV 4

Rising edge rate Rise-Fall - - 20.0 % 10, 11, 12

(SD1_REF_CLKn_P) to falling matching
edge rate (SD1_REF_CLKn_N)
matching

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Electrical characteristics

Table 62. SD1_REF_CLKn_P and SD1_REF_CLKn_N input clock requirements (continued)

Parameter Symbol Min Typ Max Unit Notes

1. Caution: Only 100, 125, and 156.25 have been tested. In-between values do not work correctly with the rest of the system.
2. For PCI Express (2.5, 5 and 8 GT/s).
3. For SGMII, 2.5G SGMII and QSGMII.
4. Measurement taken from differential waveform.
5. Limits from PCI Express CEM Rev 2.0.
6. For PCI Express 5 GT/s, per PCI Express base specification Rev 3.0.
7. Measured from -150 mV to +150 mV on the differential waveform (derived from SD1_REF_CLKn_P minus
SD1_REF_CLKn_N). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV
measurement window is centered on the differential zero crossing.
8. See Figure 42. on page 130.
9. For PCI Express 8 GT/s, per PCI Express base specification Rev. 3.0.
10. Measurement taken from single-ended waveform.
11. Matching applies to rising edge for SD1_REF_CLKn_P and falling edge rate for SD1_REF_CLKn_N. It is measured using
a ±75 mV window centered on the median cross point where SD1_REF_CLKn_P rising meets SD1_REF_CLKn_N falling. The
median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The
rise edge rate of SD1_REF_CLKn_P must be compared to the fall edge rate of SD1_REF_CLKn_N, the maximum allowed
difference should not exceed 20% of the slowest edge rate.
12. See Figure 43. on page 131.

This figure shows the differential measurement points for rise and fall time.

Rise-edge rate Fall-edge rate

VIH = + 150 mV

0.0 V

VIL = - 150 mV

SDn_REF_CLKn_P
SDn_REF_CLKn_N

Figure 42. Differential measurement points for rise and fall time

This figure shows the single-ended measurement points for rise and fall time matching.

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NXP Semiconductors
Electrical characteristics

SDn_REF_CLKn_N SDn_REF_CLKn_N
TFALL TRISE

VCROSS MEDIAN + 75 mV

VCROSS MEDIAN VCROSS MEDIAN

VCROSS MEDIAN - 75 mV

SDn_REF_CLKn_P SDn_REF_CLKn_P

Figure 43. Single-ended measurement points for rise and fall time matching

For protocols with data rates greater than 8 Gb/s where there is no reference clock jitter specification (ex:USXGMII-10.3125G),
use the PCIe 8G clock jitter requirements.
This table defines the AC requirements for SerDes reference clocks for USXGMII-10.3125G SerDes reference clocks need to
be verified by the customer’s application design.

Table 63. SD1_REF_CLKn_P and SD1_REF_CLKn_N input clock requirements for USXGMII

Parameter Symbol Min Typ Max Unit Notes

Frequency range tCLK_REF - 156.25 - MHz 1

Clock frequency tolerance tCLK_TOL -100 - 100 ppm -

Reference clock duty cycle tCLK_DUTY 40 50 60 % 2

Single side band noise at 1 kHz at 1 kHz - - -85 dBC/ 3

Single side band noise at 10 kHz at 10 kHz - - -108 dBC/ 3

Single side band noise at 100 kHz at 100 - - -128 dBC/ 3

kHz Hz

Single side band noise at 1 MHz at 1 MHz - - -138 dBC/ 3

Single side band noise at 10 MHz at 10 - - -138 dBC/ 3

MHz Hz

Random jitter (1.2 MHz to 15 MHz) tCLK_RJ - - 0.8 ps -

Total reference clock jitter at 10 -12 tCLK_TJ - - 11 ps -

BER (1.2 MHz to 15 MHz)

Spurious noise (1.2 MHz to 15 NA - - -75 dBC -

MHz)

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 63. SD1_REF_CLKn_P and SD1_REF_CLKn_N input clock requirements for USXGMII (continued)

Parameter Symbol Min Typ Max Unit Notes

1. Caution: Only 156.25 have been tested. Inbetween values do not work correctly with the rest of the system.
2. Measurement taken from differential waveform.
3. Per XFP specification, Rev 4.5, the Module Jitter Generation spec at XFI optical output is 10mUI (RMS) and 100 mUI (p-p).
In the CDR mode, the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter.

3.16.3 SerDes transmitter and receiver reference circuits

This figure shows the reference circuits for SerDes data lane's transmitter and receiver.

SDn_TXn_P SDn_RXn_P

50 Ω
Transmitter 100 Ω Receiver

SDn_TXn_N SDn_RXn_N 50 Ω

Figure 44. SerDes transmitter and receiver reference circuits

The DC and AC specifications of the SerDes data lanes are defined in each interface protocol section below based on the
application usage:
• PCI Express
• SATA
• SGMII
• USXGMII
Note that an external AC-coupling capacitor is required for the above serial transmission protocols with the capacitor value defined
in the specification of each protocol section.

3.16.4 PCI Express

3.16.4.1 Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 ppm of each other at all times. This is specified
to allow bit rate clock sources with a ±300 ppm tolerance.

3.16.4.2 PCI Express clocking requirements for SD1_REF_CLKn_P and SD1_REF_CLKn_N

SD1_REF_CLK1_N / SD1_REF_CLK1_P and SD1_REF_CLK2_N / SD1_REF_CLK2_P may be used for various SerDes PCI
Express configurations based on the RCW Configuration field SRDS_PRTCL.
For more information on these specifications, see SerDes reference clocks on page 125.

3.16.4.3 PCI Express DC electrical characteristics

This section describes the PCI Express DC physical layer transmitter specifications for 2.5 GT/s, 5 GT/s, and 8 GT/s. This table
defines the PCI Express 2.0 (2.5 GT/s) DC electrical characteristics for the differential output at all transmitters. The parameters
are specified at the component pins.

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Data Sheet: Technical Data 132 / 184
NXP Semiconductors
Electrical characteristics

Table 64. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Differential peak-to-peak output VTX-DIFFP- 800.0 1000.0 1200.0 mV 2

voltage P

De-emphasized differential output VTX-DE- 3.0 3.5 4.0 dB 3

voltage (ratio) RATIO

DC differential transmitter ZTX-DIFF- 80.0 100.0 120.0 Ω 4

impedance DC

Transmitter DC impedance ZTX-DC 40.0 50.0 60.0 Ω 5

1. For recommended operating conditions, see Recommended Operating Conditions.

2. VTX_DIFFp-p = 2 x | VTX-D+ - VTX-D- |
3. Ratio of VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition.
4. Transmitter DC differential mode low impedance
5. Required transmitter D+ as well as D- DC Impedance during all states.

This table defines the DC electrical characteristics for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The
parameters are specified at the component pins.

Table 65. PCI Express 2.0 (2.5 GT/s) differential receiver input DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Differential peak-to-peak voltage VRX- 175.0 1000.0 1200.0 mV 2, 3

DIFFP-P

DC differential input impedance ZRX-DIFF- 80.0 100.0 120.0 Ω 4, 5

DC input impedance ZRX-DC 40.0 50.0 60.0 Ω 6, 3, 5

Powered down DC input ZRX-HIGH- 50.0 - - kΩ 7, 8

impedance IMP-DC

Electrical idle detect threshold VRX-IDLE- 65.0 - 175.0 mV 9, 3

DET-DIFFp-
p

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NXP Semiconductors
Electrical characteristics

Table 65. PCI Express 2.0 (2.5 GT/s) differential receiver input DC electrical characteristics 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

1. For recommended operating conditions, see Recommended Operating Conditions.

2. VRX_DIFFp-p = 2 x | VRX-D+ - VRX-D- |
3. Measured at the package pins with a test load of 50Ω to GND on each pin.
4. Receiver DC differential mode impedance.
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all configured lanes on a port.
6. Required receiver D+ as well as D- DC impedance (50 ± 20% tolerance).
7. Required receiver D+ as well as D- DC impedance when the receiver terminations do not have power.
8. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300mV above the receiver ground.
9. VRX-IDLE-DET-DIFFp-p = 2 x | VRX-D+ - VRX-D- |

This table defines the PCI Express 2.0 (5 GT/s) DC electrical characteristics for the differential output at all transmitters. The
parameters are specified at the component pins.

Table 66. PCI Express 2.0 (5 GT/s) differential transmitter output DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Differential peak-to-peak output VTX-DIFFP- 800.0 1000.0 1200.0 mV 2

voltage P

Low power differential peak-peak VTX-DIFFP- 400.0 500.0 1200.0 mV 2

output voltage P-LOW

De-emphasized differential output VTX-DE- 3.0 3.5 4.0 dB 3

voltage (ratio) RATIO-3.5d
B

De-emphasized differential output VTX-DE- 5.5 6.0 6.5 dB 3

voltage (ratio) RATIO-6.0d
B

DC differential transmitter ZTX-DIFF- 80.0 100.0 120.0 Ω 4

impedance DC

Transmitter DC impedance ZTX-DC 40.0 50.0 60.0 Ω 5

1. For recommended operating conditions, see Recommended Operating Conditions.

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Data Sheet: Technical Data 134 / 184
NXP Semiconductors
Electrical characteristics

This table defines the DC electrical characteristics for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The
parameters are specified at the component pins.

Table 67. PCI Express 2.0 (5 GT/s) differential receiver input DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Differential peak-to-peak voltage VRX- 120.0 1000.0 1200.0 mV 2, 3

DIFFP-P

DC differential input impedance ZRX-DIFF- 80.0 100.0 120.0 Ω 4, 5

DC input impedance ZRX-DC 40.0 50.0 60.0 Ω 6, 3, 5

Powered down DC input ZRX-HIGH- 50.0 - - kΩ 7, 8

impedance IMP-DC

Electrical idle detect threshold VRX-IDLE- 65.0 - 175.0 mV 9, 3

DET-DIFFp-
p

1. For recommended operating conditions, see Recommended Operating Conditions.

This table defines the PCI Express 3.0 (8 GT/s) DC electrical characteristics for the differential output at all transmitters. The
parameters are specified at the component pins.

Table 68. PCI Express 3.0 (8 GT/s) differential transmitter output DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Full swing transmitter voltage with VTX-FS- 800.0 - 1300.0 mVp- 2

no TX Eq NO-EQ p

Reduced swing transmitter VTX-RS- 400.0 - 1300.0 mV 2

voltage with no TX Eq NO-EQ

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NXP Semiconductors
Electrical characteristics

Table 68. PCI Express 3.0 (8 GT/s) differential transmitter output DC electrical characteristics 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

De-emphasized differential output VTX-DE- 3.0 3.5 4.0 dB 3

voltage (ratio) RATIO-3.5d
B

De-emphasized differential output VTX-DE- 5.5 6.0 6.5 dB 3

voltage (ratio) RATIO-6.0d
B

Minimum swing during EIEOS for ZTX- 250.0 - - mVp- 4

full swing EIEOS-FS p

Minimum swing during EIEOS for ZTX- 232.0 - - mVp- 4

reduced swing EIEOS-RS p

DC differential transmitter ZTX-DIFF- 80.0 100.0 120.0 Ω 5

impedance DC

Transmitter DC impedance ZTX-DC 40.0 50.0 60.0 Ω 6

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Voltage measurements for VTX-FS-NO-EQ and VTX-RS-NO-EQ are made using the 64-zeroes/64-ones pattern in the compliance
pattern.
3. Ratio of VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition.
4. Voltage limits comprehend both full swing and reduced swing modes. The transmitter must reject any changes that would
violate this specification. The maximum level is covered in the VTX-FS-NO-EQ measurement which represents the maximum peak
voltage the transmitter can drive. The VTX-EIEOS-FS and VTX-EIEOS-RS voltage limits are imposed to guarantee the EIEOS
threshold of 175 mVP-P at the receiver pin. This parameter is measured using the actual EIEOS pattern that is part of the
compliance pattern and then removing the ISI contribution of the breakout channel.
5. Transmitter DC differential mode low impedance
6. Required transmitter D+ as well as D- DC Impedance during all states.

This table defines the DC electrical characteristics for the PCI Express 3.0 (8 GT/s) differential input at all receivers. The
parameters are specified at the component pins.

Table 69. PCI Express 3.0 (8 GT/s) differential receiver input DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

DC differential input impedance ZRX-DIFF- 80.0 100.0 120.0 Ω 2, 3

DC input impedance ZRX-DC 40.0 50.0 60.0 Ω 4, 5, 3

Powered down DC input ZRX-HIGH- 50.0 - - kΩ 6, 7

impedance IMP-DC

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 69. PCI Express 3.0 (8 GT/s) differential receiver input DC electrical characteristics 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

Electrical idle detect threshold VRX-IDLE- 65.0 - 175.0 mV 8, 5

DET-DIFFp-
p

Generator launch voltage VRX- - 800.0 - mV 9

LAUNCH-8
G

Eye height (-20dB channel) VRX-SV-8G 25.0 - - mV 10

Eye height (-12dB channel) VRX-SV-8G 50.0 - - mV 10

Eye height (-3dB channel) VRX-SV-8G 200.0 - - mV 10

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Receiver DC differential mode impedance.
3. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all configured lanes on a port.
4. Required receiver D+ as well as D- DC impedance (50 ± 20% tolerance).
5. Measured at the package pins with a test load of 50Ω to GND on each pin.
6. Required receiver D+ as well as D- DC impedance when the receiver terminations do not have power.
7. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300mV above the receiver ground.
8. VRX-IDLE-DET-DIFFp-p = 2 x | VRX-D+ - VRX-D- |
9. Measured at TP1 per PCI Express base specification Rev 3.0.
10. Measured at TP2 per PCI Express base specification Rev 3.0. VRX-SV-8G is tested at three different voltages to ensure the
receiver device under test is capable of equalizing over a range of channel loss profiles. In the parameter names, "SV" refers
to stressed voltage. VRX-SV-8G is referenced to TP2P and is obtained after post-processing data is captured at TP2.

3.16.4.4 PCI Express AC timing specifications

This section describes the PCI Express AC physical layer transmitter specifications for 2.5 GT/s, 5 GT/s, and 8 GT/s.This table
defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified
at the component pins. The AC timing specifications do not include RefClk jitter.

Table 70. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 399.88 400.0 400.12 ps 1

Minimum transmitter eye width TTX-EYE 0.75 - - UI 2, 3, 4, 5

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NXP Semiconductors
Electrical characteristics

Table 70. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

Maximum time between the jitter TTX-EYE- - - 0.125 UI 6, 3, 4, 5

median and maximum deviation MEDIAN-to-
from the median MAX-
JITTER

AC coupling capacitor CTX 75.0 - 200.0 nF 7, 8

1. Each UI is 400 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
2. The maximum transmitter jitter can be derived as TTX-MAX-JITTER = 1 -TTX-EYE = 0.25 UI. Does not include spread-spectrum
or REFCLK jitter. Includes devices random jitter at 10 -12.
3. Specified at the measurement point into a timing and voltage test load and measured over any 250 consecutive transmitter
Uis.
4. A TTX-EYE - 0.75 UI provides for a a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter Uis. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the
total transmitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same
as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal
as opposed to the averaged time value.
5. See Figure 46. on page 143.
6. Jiiter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered transmitter
UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all
edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI.
7. All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component
itself.
8. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.

This table defines the AC timing specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters
are specified at the component pins. The AC timingspecifications do not include RefClk jitter.

Table 71. PCI Express 2.0 (2.5 GT/s) differential receiver input AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 399.88 400.0 400.12 ps 1

Minimum receiver eye width TRX-EYE 0.4 - - UI 2, 3, 4

Maximum time between the jitter TRX-EYE- - - 0.3 UI 3, 4, 5

median and maximum deviation MEDIAN-to-
from the median MAX-
JITTER

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NXP Semiconductors
Electrical characteristics

Table 71. PCI Express 2.0 (2.5 GT/s) differential receiver input AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

1. Each UI is 400 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
2. The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX-MAX-JITTER
= 1 - TRX-EYE = 0.6 UI.
3. Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered transmitter
UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all
edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI.
4. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in
which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any
250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter median describes the
point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If
the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
5. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a
fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.

This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all transmitters. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.

Table 72. PCI Express 2.0 (5 GT/s) differential transmitter output AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 199.94 200.0 200.06 ps 1

Minimum transmitter eye width TTX-EYE 0.75 - - UI 2, 3, 4, 5

Transmitter deterministic jitter > TTX-HF-DJ- - - 0.15 UI -

1.5 MHz DD

Transmitter RMS jitter < 1.5 MHz TTX-LF- - 3.0 - ps 6

RMS

AC coupling capacitor CTX 75.0 - 200.0 nF 7, 8

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NXP Semiconductors
Electrical characteristics

Table 72. PCI Express 2.0 (5 GT/s) differential transmitter output AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

1. Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
2. The maximum transmitter jitter can be derived as TTX-MAX-JITTER = 1 -TTX-EYE = 0.25 UI. Does not include spread-spectrum
or REFCLK jitter. Includes devices random jitter at 10 -12.
3. Specified at the measurement point into a timing and voltage test load and measured over any 250 consecutive transmitter
Uis.
4. A TTX-EYE - 0.75 UI provides for a a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter Uis. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the
total transmitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same
as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal
as opposed to the averaged time value.
5. See Figure 46. on page 143.
6. Reference input clock RMS jitter (< 1.5 MHz) at pin < 1 ps.
7. All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component
itself.
8. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.

This table defines the AC timing specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.

Table 73. PCI Express 2.0 (5 GT/s) differential receiver input AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 199.94 200.0 200.06 ps 1

Max receiver inherent timing error TRX-TJ-CC - - 0.4 UI -

Max receiver inherent TRX-DJ- - - 0.3 UI -

deterministic timing error DD-CC

1. Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.

This table defines the PCI Express 3.0 (8 GT/s) AC specifications for the differential output at all transmitters. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.

Table 74. PCI Express 3.0 (8 GT/s) differential transmitter output AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 124.9625 125.0 125.0375 ps 1

AC coupling capacitor CTX 176.0 - 265.0 nF 2, 3

Transmitter uncorrelated total jitter TTX-UTJ - - 31.25 ps p- -

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NXP Semiconductors
Electrical characteristics

Table 74. PCI Express 3.0 (8 GT/s) differential transmitter output AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

Transmitter uncorrelated TTX-UDJ- - - 12.0 ps p- -

deterministic jitter DD p

Total uncorrelated pulse width TTX-UPW- - - 24.0 ps p- 4, 5

jitter (PWJ) TJ p

Deterministic data dependent jitter TTX-UPW- - - 10.0 ps p- 4, 5

(DjDD) uncorrelated pulse width DJDD p
jitter (PWJ)

Data-dependent jitter TTX-DDJ - - 18.0 ps p- 4

1. Each UI is 125 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
2. All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component
itself.
3. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
4. Measured with optimized preset value after de-embedding to transmitter pin.
5. PWJ parameters shall be measured after data-dependent jitter (DDJ) separation.

This table defines the AC timing specifications for the PCI Express 3.0 (8 GT/s) differential input at all receivers. The parameters
are specified at the component pins. The AC timingspecifications do not include RefClk jitter.

Table 75. PCI Express 3.0 (8 GT/s) differential receiver input AC timing specifications 5

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 124.9625 125.0 125.0375 ps 1, 2

Eye width at TP2P TRX-SV-8G 0.3 - 0.35 UI 2

Differential mode interference VRX-SV- 14.0 - - mV 3

DIFF-8G

Sinusoidal jitter at 100 MHz TRX-SV- - - 0.1 UI p-p 4, 5

SJ-8G

Random jitter TRX-SV- - - 2.0 ps 6, 5

RJ-8G RMS

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NXP Semiconductors
Electrical characteristics

Table 75. PCI Express 3.0 (8 GT/s) differential receiver input AC timing specifications 5 (continued)

Parameter Symbol Min Typ Max Unit Notes

1. Each UI is 125 ps ± 300 ppm. UI does not account for spreadspectrum clock dictated variations.
2. TRX-SV-8G is referenced to TP2P and is obtained after post-processing data is captured at TP2. TRX-SV-8G includes the effects
of applying the behavioral receiver model and receiver behavioral equalization.
3. Frequency = 2.1GHz. VRX-SV-DIFF-8G voltage may need to be adjusted over a wide range for the different loss calibration
channels.
4. Fixed at 100 MHz. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency.
5. See Figure 45. on page 142.
6. Random jitter spectrally flat before filtering. Random jitter (Rj) is applied over the following range: The low frequency limit
may be between 1.5 and 10 MHz, and the upper limit is 1.0 GHz. Rj may be adjusted to meet the 0.3 UI value for TRX-SV-8G.

This figure shows the swept sinusoidal jitter mask.

0.03 MHz 100 MHz

Sj sweep range

1.0 UI
20 dB
Rj (ps RMS)
Sj (UI PP)

decade

Sj
0.1 UI

Rj
~ 3.0 ps RMS

0.01 MHz 0.1 MHz 1.0 MHz 10 MHz 100 MHz 1000 MHz

Figure 45. Swept sinusoidal jitter mask

The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be
connected to the test/measurement load within 0.2 inches of that load, as shown in the following figure. Note that the allowance
of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may
benefit from D+ and D- not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state
where the measurement point is located, the measurement point is assumed to be the D+ and Dpackage pins.

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Data Sheet: Technical Data 142 / 184
NXP Semiconductors
Electrical characteristics

D + package pin

C = CTX

Transmitter
silicon
+ package

C = CTX

D - package pin
R = 50 Ω R = 50 Ω

Figure 46. Test and measurement load

3.16.5 Serial ATA (SATA)

3.16.5.1 SATA DC electrical characteristics

This table provides the differential transmitter output DC characteristics for the SATAinterface at Gen1i/1m or 1.5 Gbits/s
transmission.

Table 76. SATA Gen 1i/1m 1.5G transmitter DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Transmitter differential output VSATA_TX 400.0 500.0 600.0 mV p- Terminated by

voltage DIFF p a 50Ω load.

Transmitter differential pair ZSATA_TX 85.0 100.0 115.0 Ω DC

impedance DIFFIM impedance.

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Terminated by a 50Ω load.
3. DC impedance.

This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface.

Table 77. SATA Gen 1i/1m 1.5G receiver input DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Differential input voltage VSATA_RX 240.0 500.0 600.0 mV p- 2

DIFF p

Differential receiver input ZSATA_RX 85.0 100.0 115.0 Ω 3

impedance SEIM

OOB signal detection threshold VSATA_OO 50.0 120.0 240.0 mV p- -

B p

Table continues on the next page...

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Data Sheet: Technical Data 143 / 184
NXP Semiconductors
Electrical characteristics

Table 77. SATA Gen 1i/1m 1.5G receiver input DC electrical characteristics 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Voltage relative to common of either signal comprising a differential pair.
3. DC impedance.

This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i/2m or 3.0 Gbits/s
transmission.

Table 78. SATA Gen 2i/2m 3G transmitter DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Transmitter differential output VSATA_TX 400.0 - 700.0 mV p- Terminated by

voltage DIFF p a 50Ω load.

Transmitter differential pair ZSATA_TX 85.0 100.0 115.0 Ω DC

impedance DIFFIM impedance.

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Terminated by a 50Ω load.
3. DC impedance.

This table provides the Gen2i/2m or 3 Gbits/s differential receiver input DC characteristics for the SATA interface.

Table 79. SATA Gen 2i/2m 3G receiver input DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Differential input voltage VSATA_RX 240.0 - 750.0 mV p- 2

DIFF p

Differential receiver input ZSATA_RX 85.0 100.0 115.0 Ω 3

impedance SEIM

OOB signal detection threshold VSATA_OO 75.0 120.0 240.0 mV p- -

B p

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Voltage relative to common of either signal comprising a differential pair.
3. DC impedance.

This table provides the differential transmitter output DC characteristics for the SATA interface at Gen 3i transmission.

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 144 / 184
NXP Semiconductors
Electrical characteristics

Table 80. SATA Gen 3i transmitter DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Transmitter differential output VSATA_TX 240.0 - 900.0 mV p- Terminated by

voltage DIFF p a 50Ω load.

Transmitter differential pair ZSATA_TX 85.0 100.0 115.0 Ω DC

impedance DIFFIM impedance.

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Terminated by a 50Ω load.
3. DC impedance.

This table provides the Gen 3i differential receiver input DC characteristics for the SATAinterface.

Table 81. SATA Gen 3i receiver input DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Differential input voltage VSATA_RX 240.0 - 1000.0 mV p- 2

DIFF p

Differential receiver input ZSATA_RX 85.0 100.0 115.0 Ω 3

impedance SEIM

OOB signal detection threshold VSATA_OO 75.0 120.0 200.0 mV p- -

B p

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Voltage relative to common of either signal comprising a differential pair.
3. DC impedance.

3.16.5.2 SATA AC timing specifications

This table provides the AC requirements for the SATA reference clock. These requirements must be guaranteed by the customer’s
application design.

Table 82. SATA reference clock input requirements

Parameter Symbol Min Typ Max Unit Notes

SDn_REF_CLKn_P/ tCLK_REF - 100 / 125 - MHz 1

SDn_REF_CLKn_N frequency
range

SDn_REF_CLKn_P/ tCLK_TOL -350.0 - 350.0 ppm -

SDn_REF_CLKn_N frequency
tolerance

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Table 82. SATA reference clock input requirements (continued)

Parameter Symbol Min Typ Max Unit Notes

SDn_REF_CLKn_P/ tCLK_DUTY 40 50 60 % 2
SDn_REF_CLKn_N reference
clock duty cycle

SDn_REF_CLKn_P/ tCLK_CJ - - 100.0 ps 3

SDn_REF_CLKn_N cycle-to-
cycle clock jitter (period jitter)

SDn_REF_CLKn_P/ tCLK_PJ -50.0 - 50.0 - 3, 4, 5

SDn_REF_CLKn_N total
reference clock jitter, phase jitter
(peak-to-peak)

1. Caution: Only 100 MHz and 125 MHz have been tested. In-between values do not work correctly with the rest of the system.
2. Measurement taken from differential waveform.
3. At RefClk input.
4. In a frequency band from 150 kHz to 15 MHz at BER of 10 -12.
5. Total peak-to-peak deterministic jitter must be less than or equal to 50 ps.

This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 1i/1m or 1.5 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.

Table 83. Gen 1i/1m 1.5 G transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 666.4333 666.6667 670.2333 - -

Channel speed tCH_SPEE - 1.5 - Gbps -

Total jitter, data-data 5 UI USATA_TX - - 0.355 UI p-p 1

TJ5UI

Total jitter, data-data 250 UI USATA_TX - - 0.47 UI p-p 1

TJ250UI

Deterministic jitter, data-data 5 UI USATA_TX - - 0.175 UI p-p 1

DJ5UI

Deterministic jitter, data-data 250 USATA_TX - - 0.22 UI p-p 1

UI DJ250UI

1. Measured at transmitter output pins peak-to-peak phase variation; random data pattern.

This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. The AC timing
specifications do not include RefClk jitter.

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Table 84. Gen 1i/1m 1.5 G receiver AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 666.4333 666.6667 670.2333 - -

Total jitter, data-data 5 UI USATA_RX - - 0.43 UI p-p Measured at

TJ5UI the receiver.

Total jitter, data-data 250 UI USATA_RX - - 0.6 UI p-p Measured at

TJ250UI the receiver.

Deterministic jitter, data-data 5 UI USATA_RX - - 0.25 UI p-p Measured at

DJ5UI the receiver.

Deterministic jitter, data-data 250 USATA_RX - - 0.35 UI p-p Measured at

UI DJ250UI the receiver.

This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 2i/2m or 3.0 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.

Table 85. Gen 2i/2m 3 G transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 333.2167 333.3333 335.1167 - -

Channel speed tCH_SPEE - 3.0 - Gbps -

Total jitter, fC3DB = fBAUD ÷ 500 USATA_TX - - 0.37 UI p-p 1

TJfB/500

Total jitter, fC3DB = fBAUD ÷ 1667 USATA_TX - - 0.55 UI p-p 1

TJfB/1667

Deterministic jitter, fC3DB = fBAUD ÷ USATA_TX - - 0.19 UI p-p 1

500 TJfB/500

Deterministic jitter, fC3DB = fBAUD ÷ USATA_TX - - 0.35 UI p-p 1

1667 TJfB/1667

1. Measured at transmitter output pins peak-to-peak phase variation; random data pattern.

This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i/2m or 3.0 Gbits/s transmission.
The AC timing specifications do not include RefClk jitter.

Table 86. Gen 2i/2m 3 G receiver AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 333.2167 333.3333 335.1167 - -

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Table 86. Gen 2i/2m 3 G receiver AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

Total jitter, fC3DB = fBAUD ÷ 500 USATA_RX - - 0.6 UI p-p Measured at

TJfB/500 the receiver.

Total jitter, fC3DB = fBAUD ÷ 1667 USATA_RX - - 0.65 UI p-p Measured at

TJfB/1667 the receiver.

Deterministic jitter, fC3DB = fBAUD ÷ USATA_RX - - 0.42 UI p-p Measured at

500 TJfB/500 the receiver.

Deterministic jitter, fC3DB = fBAUD ÷ USATA_RX - - 0.35 UI p-p Measured at

1667 TJfB/1667 the receiver.

This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 3i transmission. The AC
timing specifications do not include RefClk jitter.

Table 87. Gen 3i transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit

Unit Interval UI 166.6083 167.6667 167.5583 -

Channel speed tCH_SPEED - 6.0 - Gbps

Total jitter before and after compliance JT - - 0.52 UI p-p

interconnect channel

Random jitter before compliance JR - - 0.18 UI p-p

interconnect channel

This table provides the differential receiver input AC characteristics for the SATA interface at Gen 3i transmission The AC timing
specifications do not include RefClk jitter.

Table 88. Gen 3i receiver AC timing specifications

Parameter Symbol Min Typ Max Unit

Unit Interval UI 166.6083 167.6667 167.5583 -

Total jitter before and after compliance JT - - 0.6 UI p-p

interconnect channel

Random jitter before compliance JR - - 0.18 UI p-p

interconnect channel

3.16.6 SGMII interface

Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in Figure 47. on page
150, where CTX is the external (on board) AC-coupled capacitor. Each SerDes transmitter differential pair features 100-Ω output
impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XGNDn. The reference circuit
of the SerDes transmitter and receiver is shown in Figure 44. on page 132.

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Electrical characteristics

3.16.6.1 SGMII clocking requirements for SDn_REF_CLK1_P and SDn_REF_CLK1_N

When operating in SGMII mode, a SerDes reference clock is required on SDn_REF_CLK[1:2]_P and SDn_REF_CLK[1:2]_N
pins.
For more information on these specifications, see SerDes reference clocks on page 125.

3.16.6.2 SGMII and SGMII 2.5G DC electrical characteristics

This table describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are
measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N), as provided in the SGMII transmitter DC measurement
circuit figure as shown below.

Table 89. SGMII DC transmitter electrical characteristics 1, 12, 13

Parameter Symbol Min Typ Max Unit Notes

Output high voltage VOH - - 1.5 x |VOD|-max mV 2

Output low voltage VOL |VOD|-min/2 - - mV 2

Output differential voltage |VOD| 320.0 500.0 725.0 mV 3, 4, 5

Output differential voltage |VOD| 293.8 459.0 665.6 mV 3, 4, 6

Output differential voltage |VOD| 266.9 417.0 604.7 mV 3, 4, 7

Output differential voltage |VOD| 240.6 376.0 545.2 mV 3, 4, 8

Output differential voltage |VOD| 213.1 333.0 482.9 mV 3, 4, 9

Output differential voltage |VOD| 186.9 292.0 423.4 mV 3, 4, 10

Output differential voltage |VOD| 160.0 250.0 362.5 mV 3, 4, 11

Output impedance (differential) RO 80.0 100.0 120.0 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. This does not align to DC-coupled SGMII.
3. |VOD| = |VSD_TXn_P - VSD_TXn_N|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 x |VOD|.
4. The |VOD| value shown in Typ column is based on the condition of XnVDD-Typ, no common mode offset variation. SerDes
transmitter is terminated with 100-Ω differential load between SDn_TXn_P and SDn_TXn_N.
5. LNmTECR0[AMP_RED]=0b000000
6. LNmTECR0[AMP_RED]=0b000001
7. LNmTECR0[AMP_RED]=0b000011
8. LNmTECR0[AMP_RED]=0b000010
9. LNmTECR0[AMP_RED]=0b000110 (default)
10. LNmTECR0[AMP_RED]=0b000111
11. LNmTECR0[AMP_RED]=0b010000
12. See Figure 47. on page 150.
13. See Figure 48. on page 151.

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This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.

SDn_TXn_P SDn_RXn_P
CTX

50 Ω

Transmitter 100 Ω Receiver

CTX
SDn_TXn_N SDn_RXn_N
50 Ω

SGMII
SerDes Interface
SDn_RXn_P SDn_TXn_P
CTX

50 Ω

Receiver Transmitter
100 Ω

CTX
SDn_RXn_N SDn_TXn_N
50 Ω

Figure 47. 4-wire AC-coupled SGMII serial link connection example

This figure shows the SGMII transmitter DC measurement circuit.

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Electrical characteristics

SGMII
SerDes Interface

SDn_TXn_P

50 Ω

Transmitter 100 Ω VOD

50 Ω

SDn_TXn_N

Figure 48. SGMII transmitter DC measurement circuit

This table defines the SGMII 2.5G transmitter DC electrical characteristics for 3.125 GBaud.

Table 90. SGMII 2.5G transmitter DC electrical characteristics1

Parameter Symbol Min Typical Max Unit Notes

Output differential voltage │VOD│ 400 - 600 mV -

Output impedance (differential) RO 80 100 120 Ω -

Notes:
1. For recommended operating conditions, see Recommended Operating Conditions.

This table lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not supported. Clock is recovered
from the data.

Table 91. SGMII DC receiver electrical characteristics 1

Parameter Symbol Min Max Unit Notes

DC input voltage range VIN N/A N/A - 2

Input differential voltage (REIDL_TH = VRX_DIFFp-p 100.0 1200.0 mV 3, 4

001, default)

Input differential voltage (REIDL_TH = VRX_DIFFp-p 175.0 1200.0 mV 3, 4

100)

Loss of signal threshold (REIDL_TH = VLOS 30.0 100.0 mV 5, 4

001, default)

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Table 91. SGMII DC receiver electrical characteristics 1 (continued)

Parameter Symbol Min Max Unit Notes

Loss of signal threshold (REIDL_TH = VLOS 65.0 175.0 mV 5, 4

100)

Receiver differential input impedance ZRX_DIFF 80.0 120.0 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Input must be externally AC coupled.
3. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
4. The REIDL_TH shown in the table referes to the chip's LNmGCR1[REIDL_TH] bit field.
5. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express.

This table defines the SGMII 2.5G receiver DC electrical characteristics for 3.125 GBaud.

Table 92. SGMII 2.5G receiver DC electrical characteristics 1

Parameter Symbol Min Typical Max Unit Notes

Input differential voltage VRX_DIFFp-p 200 - 1200 mV -

Loss of signal threshold VLOS 75 - 200 mV -

Receiver differential input impedance ZRX_DIFF 80 - 120 Ω -

Notes:
1. For recommended operating conditions, see Recommended Operating Conditions.

3.16.6.3 SGMII and SGMII 2.5G AC timing specifications

This table provides the SGMII and SGMII 2.5G transmit AC timing specifications. A source synchronous clock is not supported.
The AC timing specifications do not include RefClk jitter.

Table 93. SGMII transmitter AC timing specifications 4

Parameter Symbol Min Typ Max Unit Notes

Deterministic jitter JD - - 0.17 UI p-p -

Total jitter JT - - 0.35 UI p-p 1

Unit interval: 1.25 GBaud (SGMII) UI 800-100ppm 800.0 800+100ppm ps 2

Unit interval: 3.125 GBaud (2.5G UI 320-100ppm 320.0 320+100ppm ps 2

SGMII)

AC coupling capacitor CTX 10.0 - 200.0 nF 3

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Table 93. SGMII transmitter AC timing specifications 4 (continued)

Parameter Symbol Min Typ Max Unit Notes

1. See Figure 50. on page 154.

2. Each UI is 800 ps ± 100 ppm or 320 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter output.
4. See Figure 49. on page 153.

Transmitter and receiver AC characteristics are measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N) or at the
receiver inputs (SDn_RXn_P and SDn_RXn_N) respectively, as shown in this figure.

D + package pin

C = CTX

Transmitter
silicon
+ package

C = CTX

D - package pin
R = 50 Ω R = 50 Ω

Figure 49. SGMII AC test/measurement load

This table provides the SGMII and SGMII 2.5G receiver AC timing specifications. TheAC timing specifications do not include
RefClk jitter. Source synchronous clocking is notsupported. Clock is recovered from the data.

Table 94. SGMII receiver AC timing specifications 3

Parameter Symbol Min Typ Max Unit Notes

Deterministic jitter tolerance JD - - 0.37 UI p-p 1

Combined deterministic and JDR - - 0.55 UI p-p 1

random jitter tolerance

Total jitter tolerance JT - - 0.65 UI p-p 1, 2, 3

Unit interval: 1.25 GBaud (SGMII) UI 800-100ppm 800.0 800+100ppm ps 1

Unit interval: 3.125 GBaud (2.5G UI 320-100ppm 320.0 320+100ppm ps 1

SGMII)

Bit error ratio BER - - 10 -12 - -

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Table 94. SGMII receiver AC timing specifications 3 (continued)

Parameter Symbol Min Typ Max Unit Notes

1. Measured at receiver.
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of the Single-frequency sinusoidal jitter limits
figure shown below. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise,
crosstalk and other variable system effects.
3. See Figure 50. on page 154.

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of this figure.

8.5 UI p-p

Sinuosidal
Jitter 20 dB/dec
Amplitude

0.10 UI p-p

baud/142000 Frequency baud/1667 20 MHz

Figure 50. Single-frequency sinusoidal jitter limits

3.16.7 Quad serial media-independent interface (QSGMII)

3.16.7.1 QSGMII clocking requirements for SDn_REF_CLKn_P and SDn_REF_CLKn_N

For more information on these specifications, see SerDes reference clocks on page 125.

3.16.7.2 QSGMII DC electrical characteristics

This table describes the QSGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics
are measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N).

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Table 95. QSGMII transmitter DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit

Output differential voltage VDIFF 400.0 - 900.0 mV

Differential resistance TRD 80.0 100.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

This table defines the QSGMII receiver DC electrical characteristics.

Table 96. QSGMII receiver DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit

Input differential voltage VDIFF 100.0 - 900.0 mV

Differential resistance RRDIN 80.0 100.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

3.16.7.3 QSGMII AC timing specifications

This table provides the QSGMII transmitter AC timing specifications.

Table 97. QSGMII transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit

Transmitter baud rate TBAUD 5.000-100ppm 5.0 5.000+100ppm Gb/s

Uncorrelated high probability jitter TUHPJ - - 0.15 UI p-p

Total jitter tolerance JT - - 0.3 UI p-p

This table provides the QSGMII receiver AC timing specifications.

Table 98. QSGMII receiver AC timing specifications 2

Parameter Symbol Min Typ Max Unit Notes

Receiver baud rate RBAUD 5.000-100ppm 5.0 5.000+100ppm Gb/s -

Uncorrelated bounded high RDJ - - 0.15 UI p-p -

probability jitter

Correlated bounded high RCBHPJ - - 0.3 UI p-p 1

probability jitter

Bounded high probability jitter RBHPJ - - 0.45 UI p-p -

Sinusoidal jitter, maximum RSJ-max - - 5.0 UI p-p -

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Table 98. QSGMII receiver AC timing specifications 2 (continued)

Parameter Symbol Min Typ Max Unit Notes

Sinusoidal jitter, high frequency RSJ-hf - - 0.05 UI p-p -

Total jitter (does not include RTJ s - 0.6 UI p-p -

sinusoidal jitter) -

1. The jitter (RCBHPJ) and amplitude have to be correlated, for example, by a PCB trace.
2. See Figure 51. on page 156.

The sinusoidal jitter may have any amplitude and frequency in the unshaded region of this figure.

5 UI p-p

Sinuosidal
Jitter
Amplitude

0.05 UI p-p

35.2 kHz Frequency 3 MHz 20 MHz

Figure 51. QSGMII single-frequency sinusoidal jitter limits

3.16.8 1000Base-KX

3.16.8.1 1000Base-KX DC electrical characteristics

This table describes the 1000Base-KX SerDes transmitter DC specification at TP1 per IEEE Std 802.3ap-2007. Transmitter DC
characteristics are measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N).

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Electrical characteristics

Table 99. 1000Base-KX transmitter DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Output differential voltage VTX-DIFFp- 800.0 - 1600.0 mV SRDSxLNmT

p ECR0[AMP_R
ED]=00_0000

Differential resistance TRD 80.0 100.0 120.0 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. SRDSxLNmTECR0[AMP_RED]=00_0000

This tableprovides the 1000Base-KX receiver DC electrical characteristics

Table 100. 1000Base-KX receiver DC electrical characteristics 1

Parameter Symbol Min Max Unit

Input differential voltage VRX-DIFFp-p - 1600.0 mV

Differential resistance TRDIN 80.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

3.16.8.2 1000Base-KX AC timing specifications

This table defines the 1000Base-KX transmitter AC timing specifications.

Table 101. 1000Base-KX transmitter AC timing specifications 2

Parameter Symbol Min Typ Max Unit Notes

Baud rate TBAUD 1.25-100ppm 1.25 1.25+100ppm Gbau -

Uncorrelated high probability jitter/ TUHPJ / - - 0.15 UI p-p -

Random Jitter TRJ

Deterministic jitter tolerance TDJ - - 0.1 UI p-p -

Total jitter TTJ - - 0.25 UI p-p 1

1. Total jitter is specified at a BER of 10 -12.

2. The AC specifications do not include Refclk jitter.

This table defines the 1000Base-KX receiver AC timing specifications.

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Table 102. 1000Base-KX receiver AC timing specifications 3

Parameter Symbol Min Typ Max Unit Notes

Baud rate RBAUD 1.25-100ppm 1.25 1.25+100ppm Gbau -

Total jitter tolerance RTJ - - Per IEEE UI p-p 1

802.3ap-clause
70.

Random jitter RRJ - - 0.15 UI p-p 2

Sinusoidal jitter (maximum) RSJ-max - - 0.1 UI p-p 1

1. The receiver interference tolerance level of this parameter shall be measured as described in Annex 69A of the IEEE Std
802.3ap-2007.
2. Random jitter is specified at a BER of 10 -12.
3. The AC specifications do not include Refclk jitter.

3.16.9 USXGMII interface (10G-SXGMII and 10G-QXGMII)

3.16.9.1 USXGMII DC electrical characteristics

This table defines the 10G-SXGMII transmitter DC electrical characteristics.

Table 103. 10G-SXGMII transmitter DC electrical characteristics 1

Parameter Symbol Min Typ Max Unit Notes

Output differential voltage VTX-DIFF 800.0 - 1200.0 mV LNmTECR0[E

Q_AMP_RED
]= 000000

De-emphasized differential output VTX-DE- 0.6 1.1 1.6 dB LNmTECR0[E

voltage (ratio at 1.14dB) RATIO-1.14 Q_POST1Q]=
dB 00011

De-emphasized differential output VTX-DE- 3.0 3.5 4.0 dB LNmTECR0[E

voltage (ratio at 3.5dB) RATIO-3.5d Q_POST1Q]=
B 01000

De-emphasized differential output VTX-DE- 4.1 4.6 5.1 dB LNmTECR0[E

voltage (ratio at 4.66dB) RATIO-4.66 Q_POST1Q]=
dB 01010

De-emphasized differential output VTX-DE- 5.5 6.0 6.5 dB LNmTECR0[E

voltage (ratio at 6.0dB) RATIO-6.0d Q_POST1Q]=
B 01100

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Table 103. 10G-SXGMII transmitter DC electrical characteristics 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

De-emphasized differential output VTX-DE- 9.0 9.5 10.0 dB LNmTECR0[E

voltage (ratio at 9.5dB) RATIO-9.5d Q_POST1Q]=
B 10000

Differential resistance TRD 80.0 100.0 120.0 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. LNmTECR0[EQ_AMP_RED]= 000000
3. LNmTECR0[EQ_POST1Q]= 00011
4. LNmTECR0[EQ_POST1Q]= 01000
5. LNmTECR0[EQ_POST1Q]= 01010
6. LNmTECR0[EQ_POST1Q]= 01100
7. LNmTECR0[EQ_POST1Q]= 10000

This table defines the 10G-SXGMII receiver DC electrical characteristics.

Table 104. 10G-SXGMII receiver DC electrical characteristics 1

Parameter Symbol Min Max Unit

Input differential voltage VRX-DIFF - 1200.0 mV

Differential resistance RRD 80.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

3.16.9.2 USXGMII AC timing characteristics

This table defines the 10G-SXGMII transmitter AC timing specifications. RefClk jitter is not included.

Table 105. 10G-SXGMII transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit

Transmitter baud rate TBAUD 10.3125 - 100 ppm 10.3125 10.3125 + 100 ppm GBd

Uncorrelated high probability jitter/ TUHPJ/TRJ - - 0.15 UI p-p

Random Jitter

Deterministic jitter DJ - - 0.15 UI p-p

Total jitter TJ - - 0.3 UI p-p

This table defines the 10G-SXGMII receiver AC timing specifications. RefClk jitter is not included.

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Table 106. 10G-SXGMII receiver AC timing specifications 3

Parameter Symbol Min Typ Max Unit Notes

Receiver baud rate RBAUD 10.3125 - 100 10.3125 10.3125 + 100 GBd -
ppm ppm

Total jitter TJ - - 1.0 UI p-p 1, 2

Random jitter RJ - - 0.13 UI p-p 1

Sinusoidal jitter, maximum SJ-max - - 0.115 UI p-p 1

Duty cycle distortion DCD - - 0.035 UI p-p 1

1. The AC specifications do not include Refclk jitter.

2. The total applied Jitter Tj = ISI + Rj + DCD + Sj-max, where ISI is jitter due to frequency dependent loss.
3. TX equalization and amplitude tuning is through software for performance optimization, as in NXP provided SDKs.

3.17 I2C

3.17.1 I2C DC electrical characteristics

This table provides the DC electrical characteristics for the I 2C interface.

Table 107. I 2C DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Output low voltage (OVDD = min, IOL = 2 VOL 0.0 0.36 V -

mA, OVDD ≤ 2V)

Pulse width of spikes that must be tI2KHKL 0.0 50.0 ns 3

suppressed by the input filter

Input current each I/O pin (input voltage II - ±50 μA 4

is between 0.1 x OVDD (min) and 0.9 x
OVDD (max))

Capacitance for each I/O pin CI - 10.0 pF -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min VIL and max VIH values are based on the respective min and max OVIN values found in Recommended Operating
Conditions.
3. See the chip reference manual for information about the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if the supply is switched off.

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3.17.2 I2C AC timing specifications

This table provides the AC timing specifications for the I 2C interface.

Table 108. I 2C AC timing specifications 3, 4, 5

Parameter Symbol Min Max Unit Notes

SCL clock frequency fI2C 0.0 400.0 kHz -

Low period of the SCL clock tI2CL 1.3 - μs -

High period of the SCL clock tI2CH 0.6 - μs -

Setup time for a repeated START tI2SVKH 0.6 - μs -

condition

Hold time (repeated) START condition tI2SXKL 0.6 - μs -

(after this period, the first clock pulse is
generated)

Data setup time tI2DVKH 100.0 - ns -

Data input hold time (CBUS compatible tI2DXKL 0.0 - μs 1

masters, I 2C bus devices)

Data output delay time tI2OVKL - 0.9 μs 2

Setup time for STOP condition tI2PVKH 0.6 - μs -

Bus free time between a STOP and tI2KHDX 1.3 - μs -

START condition

Noise margin at the LOW level for each VNL 0.1 x OVDD - V -
connected device (including hysteresis)

Noise margin at the HIGH level for each VNH 0.2 x OVDD - V -
connected device (including hysteresis)

Capacitive load for each bus line Cb - 400.0 pF -

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Table 108. I 2C AC timing specifications 3, 4, 5 (continued)

Parameter Symbol Min Max Unit Notes

1. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal)
to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When
the chip acts as the I 2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are
balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time
is not a concern.
2. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
3. The symbols used for timing specifications herein follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I 2C timing (I2)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time.
4. See Figure 52. on page 162.
5. See Figure 53. on page 162.

This figure shows the AC test load for the I2C.

Output Z0= 50 Ω OVDD/2

RL = 50 Ω

Figure 52. I 2C AC test load

This figure shows the AC timing diagram for the I 2C bus.

SDA

tI2DVKH tI2KHKL tI2KHDX

tI2CL tI2SXKL
SCL

tI2CH tI2SVKH tI2PVKH

tI2SXKL
tI2DXKL, tI2OVKL
S Sr P S

Figure 53. I 2C bus AC timing diagram

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3.18 JTAG
This section describes the DC and AC electrical specifications for the JTAG (IEEE 1149.1) interface.

3.18.1 JTAG DC electrical characteristics

This table provides the DC electrical characteristics for the JTAG (IEEE 1149.1) interface.

Table 109. JTAG DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0V or VIN = OVDD) IIN - -100/+50 μA 3

Output high voltage (OVDD = min, IOH = VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

3.18.2 JTAG AC timing specifications

This table provides the JTAG AC timing specifications as defined in Figure 54. on page 164, Figure 55. on page 165, Figure
56. on page 165, and Figure 57. on page 165.

Table 110. JTAG AC timing specifications 3, 4, 5, 6, 7

Parameter Symbol Min Max Unit Notes

JTAG external clock frequency of FJTG 0.0 33.3 MHz -

operation

JTAG external clock cycle time tJTG 30.0 - ns -

JTAG external clock pulse width tJTKHKL 15.0 - ns -

measured at 1.4 V

JTAG external clock rise and fall times tJTGR/tJTGF 0.0 2.0 ns -

TRST_B assert time tTRST 25.0 - ns 1

Input setup times tJTDVKH 4.0 - ns -

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Table 110. JTAG AC timing specifications 3, 4, 5, 6, 7 (continued)

Parameter Symbol Min Max Unit Notes

Input hold times tJTDXKH 10.0 - ns -

Output valid times: boundary-scan data tJTKLDV - 15.0 ns 2

Output valid times: TDO tJTKLDV - 10.0 ns 2

Output hold times tJTKLDX 0.0 - ns 2

1. TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.
2. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The
output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be
added for trace lengths, vias, and connectors in the system.
3. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)
(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the
tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to
the time data input signals (D) reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
function. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
4. See Figure 54. on page 164.
5. See Figure 55. on page 165.
6. See Figure 56. on page 165.
7. See Figure 57. on page 165.

This figure shows the AC test load for TDO and the boundary-scan outputs of the device.

Output Z0= 50 Ω OVDD/2

RL = 50 Ω

Figure 54. AC test load for the JTAG interface

This figure shows the JTAG clock input timing diagram.

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Electrical characteristics

VM VM VM
JTAG external clock
tJTGR
tJTKHKL
tJTGF
tJTG

VM = Midpoint voltage (OVDD/2)

Figure 55. JTAG clock input timing diagram

This figure shows the TRST_B timing diagram.

TRST_B

VM VM

tTRST

VM = Midpoint voltage (OVDD/2)

Figure 56. TRST_B timing diagram

This figure shows the boundary-scan timing diagram.

JTAG External Clock

VM VM

tJTDVKH

tJTDXKH

Boundary Data Inputs Input Data Valid

tJTKLDV
tJTKLDX

Boundary Data Outputs Output Data Valid

VM = Midpoint Voltage (OVDD/2)

Figure 57. Boundary-scan timing diagram

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3.19 Synchronous Audio Interface (SAI)

This section describes the DC and AC electrical specifications for the SAI interface.

3.19.1 SAI DC electrical characteristics

This table provides the DC electrical characteristics for the SAI/I 2S interface.

Table 111. SAI/I 2S DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (L1VIN = 0V or L1VIN = IIN - ±50 μA 3, 4

OVDD)

Output high voltage (OVDD = min, IOH = VOH 1.35 - V 4

-2 mA)

Output low voltage (OVDD = min, IOL = 2 VOL - 0.4 V 4

mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min VIL and max VIH values are based on the respective min and max OVIN values found in Recommended Operating
Conditions.
3. The symbol OVIN represents the input voltage of the supply referenced in Recommended Operating Conditions.
4. The symbol OVDD represents the recommended operating voltage of the supply referenced in Recommended Operating
Conditions.

3.19.2 SAI AC timing specifications

This table provides the SAI/I2S timing in slave mode (clocks input).

Table 112. Slave mode SAI/I2S timing 1

Parameter Symbol Min Max Unit

SAIn_TX_BCLK/SAIn_RX_BCLK cycle time tSAIC 20.0 - ns

(input)

SAIn_TX_BCLK/SAIn_RX_BCLK pulse width tSAIL/tSAIH 35% 65% BCLK

high/low (input) period

SAIn_TX_BCLK to SAIn_TX_DATA / tSAISLOV - 20.0 ns

SAIn_TX_SYNC output valid

SAIn_TX_BCLK to SAIn_TX_DATA/ tSAISLOX 0.0 - ns

SAIn_TX_SYNC output invalid

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Table 112. Slave mode SAI/I2S timing 1 (continued)

Parameter Symbol Min Max Unit

SAIn_RX_DATA setup before SAIn_RX_BCLK tSAIMVKH 10.0 - ns

SAIn_RX_DATA hold after SAIn_RX_BCLK tSAISXKH 2.1 - ns

SAIn_RX_SYNC input setup before tSAISFSVKH 10.0 - ns

SAIn_RX_BCLK

SAIn_RX_SYNC input hold after tSAISFSXKH 2.1 - ns

SAIn_RX_BCLK

1. See Figure 58. on page 167.

This figure shows the SAI timing in slave modes.

tSAIC
tSAIL
SAIn_Rx_BCLK tSAIH

tSAISFSLOV tSAISFSXKH

SAIn_Tx_SYNC
tSAISFSVKH tSAISXKH

tSAISFSLOV
SAIn_Rx_SYNC

tSAISLOX
tSAISFSLOV tSAISLOX
SAIn_Tx_DATA

tSAISVKH tSAISXKH

SAIn_Rx_DATA

Figure 58. SAI timing - slave modes

3.20 Serial peripheral interface (SPI)

3.20.1 SPI DC electrical characteristics

This table provides the DC electrical characteristics for the SPI interface.

Table 113. SPI DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0V or VIN = OVDD) IIN - ±50 μA 3

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Table 113. SPI DC electrical characteristics (OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

Output high voltage (IOH = -100 μA) VOH 0.85xOVDD - V -

Output low voltage (IOH = 100 μA) VOL - 0.15xOVDD V -

1. For recommended operating conditions, see Recommended Operating Conditions.

3.20.2 SPI AC timing specifications

This table provides the SPI timing specifications.

Table 114. SPI AC timing specifications 5, 6, 7, 8

Parameter Symbol Min Max Unit Notes

SCK cycle time tSCK tSYS x 2 - ns -

SCK clock pulse width tSDC 40.0 60.0 % -

CS to SCK delay tCSC tp*2 - 2.51 - ns 1, 2, 3

After SCK delay tASC tp*2 - 0.23 - ns 1, 2, 3

Slave access time (SS active to SOUT tA - 15.0 ns 4

driven)

Slave disable time (SS inactive to SOUT tDI - 10.0 ns 4

High-Z or invalid)

Data setup time for inputs tNIIVKH 9.0 - ns 1

Data setup time for inputs tNEIVKH 4.0 - ns 4

Data hold time for inputs tNIIXKH 0.0 - ns 1

Data hold time for inputs tNEIXKH 2.0 - ns 4

Data valid (after SCK edge) for outputs tNIKHOV - 5.0 ns 1

Data valid (after SCK edge) for outputs tNEKHOV - 10.0 ns 4

Data hold time for outputs tNIKHOX 0.0 - ns 1

Data hold time for outputs tNEKHOX 0.0 - ns 4

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Table 114. SPI AC timing specifications 5, 6, 7, 8 (continued)

Parameter Symbol Min Max Unit Notes

1. Master mode
2. Refer the CTARx register in QorIQ LS1028ARM for more details
3. tp is the input clock period for the SPI controller.
4. Slave mode
5. See Figure 59. on page 169.
6. See Figure 60. on page 170.
7. See Figure 61. on page 171.
8. See Figure 62. on page 172.

This figure shows the SPI timing master when CPHA = 0.

tCSC tASC

CSx

t SDC
t SCK

SCK Output
(CPOL = 0) t SDC

SCK Output
(CPOL = 1)

t NIIXKH
t NIIVKH

SIN First Data Data Last Data

t NIKHOX
t NIKHOV

SOUT

First Data Data Last Data

Figure 59. SPI timing master, CPHA = 0

This figure shows the SPI timing master when CPHA = 1.

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CSx

SCK Output
(CPOL = 0)
tNIIXKH

SCK Output
(CPOL = 1)

tNIIVKH

SIN First Data Data Last Data

t NIKHOX
t NIKHOV
SOUT

First Data Data Last Data

Figure 60. SPI timing master, CPHA = 1

This figure shows the SPI timing slave when CPHA = 0.

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Electrical characteristics

t ASC

t CSC

t SCK

t SDC

SCK Input
(CPOL = 0) t SDC

SCK Input
(CPOL = 1)

tA tDI
t
NEKHOV
t
NEKHOX

SOUT First Data Data Last Data

tNEIVKH
tNEIXKH

SIN First Data Data Last Data

Figure 61. SPI timing slave, CPHA = 0

This figure shows the SPI timing slave when CPHA = 1.

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Electrical characteristics

SCK Input
(CPOL = 0)

SCK Input
(CPOL = 1)

tNEKHOV
t DI
tA
tNEKHOX

SOUT First Data Data Last Data

t NEIVKH
t NEIXKH

SIN First Data Data Last Data

Figure 62. SPI timing slave, CPHA = 1

3.21 Universal asynchronous receiver/transmitter (UART)

3.21.1 UART DC electrical characteristics

The table below provides the DC electrical characteristics for the DUART interface.

Table 115. DUART DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0V or VIN = OVDD) IIN - ±50 μA 3

Output high voltage (IOH = -0.5 mA) VOH 1.35 - V -

Output low voltage (IOL = 0.5 mA) VOL - 0.45 V -

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Table 115. DUART DC electrical characteristics (OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

1. For recommended operating conditions, see Recommended Operating Conditions.

3.21.2 UART AC timing specifications

This table provides the AC timing specifications for the DUART interface.

Table 116. DUART AC timing specifications

Parameter Symbol Min Max Unit Notes

Minimum baud rate baud fPLAT/(2 x - baud 1, 2

1,048,576)

Maximum baud rate baud - fPLAT/(2 x 16) baud 1, 3

1. fPLAT refers to the internal platform clock.

2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
3. The actual attainable baud rate is limited by the latency of interrupt processing.

3.22 Low power Universal asynchronous receiver/transmitter (LPUART)

3.22.1 LPUART DC electrical characteristics

This table provides the DC electrical characteristics for the LPUART interface.

Table 117. LPUART DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (OVIN = 0 V or OVIN = IIN - ±50 μA 3

OVDD)

Output high voltage (OVDD = min, IOH = VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V -

0.5 mA)

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Table 117. LPUART DC electrical characteristics (OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

1. For recommended operating conditions, see Recommended Operating Conditions.

3.22.2 LPUART AC timing specifications

This table provides the AC timing specifications for the LPUART interface.

Table 118. LPUART AC timing specifications

Parameter Symbol Min Max Unit Notes

Minimum baud rate baud fPLAT/(2 x 32 x 8192) - baud 1, 2, 3

Maximum baud rate baud - fPLAT/(2 x 16) baud 1, 4, 3

1. fPLAT refers to the internal platform clock.

2. Every bit can be over sampled with a sample clock rate of 8 and 64 times (software configurable) and each bit is the majority
of the values sampled at the sample rate divided by two, (sample rate/2)+1 and (sample rate/2)+2.
3. The 1-to-0 transition during a data word can cause a resynchronization of the sample point.
4. The actual attainable baud rate is limited by the latency of interrupt processing.

3.23 Universal serial bus 3.0 (USB)

3.23.1 USB 3.0 DC electrical characteristics

This table provides the DC electrical characteristics for the USB 3.0 interface when operating at respective supply = 3.3 V.

Table 119. USB 3.0 PHY transceiver supply DC voltage (USB_HV DD = 3.3V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 2.0 - V 2

Input low voltage VIL - 0.8 V 2

Output high voltage (USB_HVDD = min, VOH 2.8 - V -

IOH = -2mA)

Output low voltage (USB_HVDD = min, VOL - 0.3 V -

IOH = 2mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min VIL and max VIH values are based on the respective min and max USB_HVIN values found in Recommended
Operating Conditions.

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Electrical characteristics

This table provides the USB 3.0 transmitter DC electrical characteristics at package pins.

Table 120. USB 3.0 transmitter DC electrical characteristics (USB_HV DD = 3.3V) 1

Parameter Symbol Min Typ Max Unit

Differential output voltage Vtx-diff-pp 800.0 1000.0 1200.0 mVp-p

Low power differential output voltage Vtx-diff-pp-low 400.0 - 1200.0 mVp-p

Transmit de-emphasis Vtx-de-ratio 3.0 - 4.0 dB

Differential impedance ZdiffTX 72.0 100.0 120.0 Ω

Transmit common mode impedance RTX-DC 18.0 - 30.0 Ω

Absolute DC common mode voltage TTX-CM-DC- - - 200.0 mV

between U1 and U0 ACTIVEIDLE-
DELTA

DC electrical idle differential output VTX-IDLE- 0.0 - 10.0 mV

voltage DIFF-DC

1. For recommended operating conditions, see Recommended Operating Conditions.

This table provides the USB 3.0 receiver DC electrical characteristics at the Rx package pins.

Table 121. USB 3.0 receiver DC electrical characteristics (USB_HV DD = 3.3V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential receiver input RRX-DIFF- 72.0 100.0 120.0 Ω -

impedance DC

Receiver DC common mode RRX-DC 18.0 - 30.0 Ω -

impedance

DC input CM input impedance for ZRX-HIGH- 25000.0 - - Ω -

V > 0 during reset or power down IMP-DC

LFPS detect threshold VTRX- 100.0 - 300.0 mV 2

IDLE-DET-
DC-DIFFpp

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Below the minimum is noise. Must wake up above the maximum.

3.23.2 USB 3.0 AC timing specifications

This table provides the USB 3.0 transmitter AC timing specifications at package pins.

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Hardware design considerations

Table 122. USB 3.0 transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Speed fUSB - 5.0 - Gb/s -

Transmitter eye TTX-EYE 0.625 - - UI -

Unit Interval UI 199.94 200.0 200.06 ps 1

AC coupling capacitor ACCAP 75.0 - 200.0 nF -

1. UI does not account for SSC-caused variations.

This table provides the USB 3.0 receiver AC timing specifications at the Rx package pins.

Table 123. USB 3.0 receiver AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 199.94 200.0 200.06 ps 1

1. UI does not account for SSC-caused variations.

This table provides the key LFPS electrical specifications at the transmitter.

Table 124. LFPS electrical specifications at the transmitter 2

Parameter Symbol Min Max Unit Notes

Period tPeriod 20.0 100.0 ns -

Peak-to-peak differential amplitude Vtx-diff-pp-lfps 800.0 1200.0 mV -

Rise/fall time trise/fall - 4.0 ns 1

Duty cycle DCLFPS 40.0 60.0 % 1, 2

1. Measured at compliance TP1. See the Transmit normative setup figure below for details.
2. See Figure 63. on page 176.

This figure shows the transmit normative setup with reference channel as per USB 3.0 specifications.

Measurement Tool SMP Reference Test Channel Reference Cable DUT

TP1

Figure 63. Transmit normative setup

4 Hardware design considerations

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Thermal

4.1 Clock ranges

This table provides the clocking specifications for the processor core, platform, memory, ENETC and GPU & LCD controller.

Table 125. Processor, platform, and memory clocking specifications

Characteristic Maximum processor core frequency Unit Notes

800 MHz 1000 MHz 1300 MHz 1500 MHz

Min Max Min Max Min Max Min Max

Core cluster group PLL 600 800 600 1000 600 1300 600 1500 MHz 1, 3, 4
frequency

Core frequency 300 800 300 1000 300 1300 300 1500 MHz 1, 3, 4

Platform clock frequency 300 300 300 400 300 400 300 400 MHz 1

GPU and LCD controller 400 400 400 500 400 650 400 700 MHz 5
frequency

Memory bus clock frequency 650 650 650 800 650 800 650 800 MHz 1, 2

ENETC frequency 400 400 400 400 400 400 400 400 MHz 6

Notes:
1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting core
frequency, and platform clock frequency do not exceed their respective maximum or minimum operating frequencies.
2. The memory bus clock speed is half the DDR3L/DDR4 data rate.
3. For supported voltage/frequency options, see the orderable part list of QorIQ LS1028A Multicore Communications Processors
at www.nxp.com.
4. The core cluster can run at cluster group PLL/1, PLL/2 and PLL/4. For the PLL/1 case, the minimum frequency is 600 MHz.
For PLL/2 case, the minimum frequency is 400 MHz. The minimum frequency provided to the core cluster after any dividers
must always be greater than or equal to the platform frequency. For the case of the minimum platform frequency = 300 MHz,
the minimum core cluster frequency is 300 MHz.
5. GPU will run on CGA_PLL2 for 700MHz.
6. For the case of the minimum platform frequency = 300 MHz, ENETC frequency will be a divide by option of CGA PLLn

5 Thermal
This table shows the thermal characteristics for the chip. Note that these numbers are based on design estimates.

Table 126. Package thermal characteristics

Rating Board Symbol Value Unit Notes

Junction to Case Thermal Resistance — RΘJC 0.54 °C/W 1

Notes:
1. Junction-to-Case thermal resistance is determined using an isothermal cold plate heat extraction model. Case temperature
is the surface temperature at the package lid top side centre.

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Package information

5.1 Recommended thermal model

Information about Flotherm models of the package or thermal data not available in this document can be obtained from your local
NXP sales office.

5.2 Temperature diode

The chip has temperature diodes that can be used to monitor its temperature by using some external temperature monitoring
devices (such as ADT7481A™).
The following are the specifications of the chip temperature diodes:
• Operating range: 10 - 230 μA
• Ideality factor over temperature range 85°C - 125°C, n = 1.006 ± 0.003, with approximate error ± 1°C and error under ±
3°C for temperature range 0°C - 85°C.

5.3 Thermal management information

This section provides thermal management information for the flip-chip, plastic-ball, grid array (FC-PBGA) package for air-cooled
applications. Proper thermal control design is primarily dependent on the system-level design-the heat sink, airflow, and thermal
interface material.
The recommended attachment method to the heat sink is illustrated in Figure 64. on page 178. The heat sink should be attached
to the printed-circuit board with the spring force centered over the lid.

FC-PBGA package (with lid)

Heat sink

Heat sink clip

Adhesive or
Die lid
thermal interface material

Die

Lid adhesive

Printed circuit-board

Figure 64. Package exploded, cross-sectional view-FC-PBGA (w/ Lid)

The system board designer can choose between several types of heat sinks to place on the device. There are several
commercially-available thermal interfaces to choose from in the industry. Ultimately, the final selection of an appropriate heat
sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method,
assembly, and cost.

6 Package information

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Package information

6.1 Package parameters for the FC-PBGA

The package parameters are as provided in the following list. The package type is 17mm x 17mm, 448 flip-chip, plastic-ball grid
array.
• Package outline - 17 mm x 17 mm
• Interconnects - 448
• Ball Pitch - 0.75 mm
• Ball Diameter (nominal) - 0.45 mm
• Ball Height (nominal) - 0.3 mm
• Solder Balls Composition - 96.5% Sn, 3% Ag, and 0.5% Cu
• Module height (typical) - 2.31 (minimum), 2.46 mm (typical), 2.61 mm (maximum)

6.2 Mechanical dimensions of the FC-PBGA

This figure shows the mechanical dimensions and bottom surface nomenclature of the chip.

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 179 / 184
NXP Semiconductors
Package information

Figure 65. Mechanical dimensions of the FC-PBGA (with lid)

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 180 / 184
NXP Semiconductors
Security fuse processor

Notes:
1. All dimensions are in millimeters.
2. Dimensioning and tolerancing per ASME Y14.5M - 1994.
3. Pin A1 feature shape, size and location may vary.
4. Maximum solder ball diameter measured parallel to datum C.
5. Datum C, the seating plane, is determined by the spherical crowns of the solder balls.
6. Parallelism measurement shall exclude any effect of mark on top surface of package.
7. Lid overhang on substrate not allowed.

7 Security fuse processor

This chip implements the QorIQ platform's trust architecture, supporting capabilities such as secure boot. Use of the trust
architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the trust
architecture and SFP can be found in the chip reference manual.
To program SFP fuses, the user is required to supply 1.80 V to the TA_PROG_SFP pin per Power sequencing on page 68.
TA_PROG_SFP should only be powered for the duration of the fuse programming cycle, with a per device limit of six fuse
programming cycles. All other times TA_PROG_SFP should be connected to GND. The sequencing requirements for raising and
lowering TA_PROG_SFP are shown in Figure 9. on page 70. To ensure device reliability, fuse programming must be performed
within the recommended fuse programming temperature range per Recommended Operating Conditions.

NOTE
Users not implementing the QorIQ platform's trust architecture features should connect TA_PROG_SFP to GND.

8 Ordering information
Contact your local NXP sales office or regional marketing team for order information.

8.1 Part numbering nomenclature

This table provides the NXP QorIQ platform part numbering nomenclature.

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 181 / 184
NXP Semiconductors
Ordering information

Table 127. Part numbering nomenclature

p ls n nn n x t e n c d r
Qual Status

Generation

Performance Level
Number of Virtual cores

Unique ID
Core Type

Temperature Range

Encryption

Package Type

CPU Speed1

DDR Data Rate

Die Revision
P="Pre-qual" LS = 1 02 = 8 A= S = Standard E = Export 7 = H = 800 N= A=
Layersc Two = ARM temp controlled FCPBGA MHz 1300 Rev
Blank="Qualifi
ape Cores G crypto C4 PbFree MT/s 1.0
ed" X = Extended K = 1000
P hardware
01 = temp MHz Q=
U enabled
One 1600
Core Y = High N = Export N = 1300 MT/s
Extended temp controlled MHz
C = AEC Q100 crypto P = 1500
Grade 3 hardware MHz
Stresses disabled

1. For the LS1028A family of devices, parts marked with "H" require 0.9 V operating voltage.
2. For the LS1028A family of devices, parts marked with "Y" are available with CPU speed 800MHz only.
3. For the LS1028A family of devices, parts marked with "C" require 1.0 V operating voltage.

8.1.1 Part marking

Parts are marked as in the example shown in this figure.

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 182 / 184
NXP Semiconductors
Revision history

LS1028XXXXXXX
AWLYYWW
MMMMM CCCCC
YWWLAZ

Legend:
LS1028XXXXXXX is the orderable part number
AWLYYWW is the test traceability code
MMMMM is the mask number
CCCCC is the country code
YWWLAZ is the assembly traceability code

Figure 66. Part marking for FC-PBGA chip LS1028A

9 Revision history
This table summarizes revisions to this document.

Table 128. Revision history

Revision Date Description

0 12/2019 Initial release

QorIQ LS1028A/LS1018A Data Sheet, Rev. 0, 12/2019

Data Sheet: Technical Data 183 / 184
How To Reach Us Information in this document is provided solely to enable system and software implementers to
use NXP products. There are no express or implied copyright licenses granted hereunder to
Home Page:
design or fabricate any integrated circuits based on the information in this document. NXP
nxp.com reserves the right to make changes without further notice to any products herein.
Web Support: NXP makes no warranty, representation, or guarantee regarding the suitability of its products for
nxp.com/support any particular purpose, nor does NXP assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. “Typical” parameters that may be provided in NXP data
sheets and/or specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be validated for each
customer application by customer's technical experts. NXP does not convey any license under
its patent rights nor the rights of others. NXP sells products pursuant to standard terms and
conditions of sale, which can be found at the following address: nxp.com/
SalesTermsandConditions.

NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,
EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE
CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT,
MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,
TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C‑5, CodeTEST, CodeWarrior,
ColdFire, ColdFire+, C‑Ware, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV,
mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play,
SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit,
BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower,
TurboLink, and UMEMS are trademarks of NXP B.V. All other product or service names are the
property of their respective owners. Arm, AMBA, Arm Powered, Artisan, Cortex, Jazelle, Keil,
SecurCore, Thumb, TrustZone, and μVision are registered trademarks of Arm Limited (or its
subsidiaries) in the EU and/or elsewhere. Arm7, Arm9, Arm11, big.LITTLE, CoreLink, CoreSight,
DesignStart, Mali, Mbed, NEON, POP, Sensinode, Socrates, ULINK and Versatile are
trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.
Oracle and Java are registered trademarks of Oracle and/or its affiliates. The Power Architecture
and Power.org word marks and the Power and Power.org logos and related marks are
trademarks and service marks licensed by Power.org.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12/2019
Document identifier: LS1028A/LS1018A

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