DIGITAL SYSTEM DESIGN

Number Systems
2
Boolean Algebra
11
Combinational Circuits
26
Sequential Circuits
68
Logic Families
104
Programmable Logic Devices
125
/D &D/A Converter 134
VLSI Design Flow
145

NOTE
MAKAUT course structure
and syllabus of 3 semester has been changed from 2019.
Digital Electronics Circuit was in 3 semester, EE Branch.
The subject organization
has been completely redesigned and shifted in 3 semester, EC Branch
in present
curiculum as DIGITAL SYSTEM DESIGN. Taking special care of this matter
we are
providing the relevant MAKAUT university solutions of Digital
Electronics Circuit
E and some model questions answers for
& newy introduced topics along with
the
Complete soutions of new university papers, so that students can get an
idea about
university questions pattems.
POPULARPUBLICATIONS

NUMBER SYSTEMS

Chapter at a Glance
of numbers are represented by numerals in a
system is a framework where a set
consistent manner. Ex: Decimal Number System, Binary Number System
(1V) Hexadecimal.
Ommonly used Number system: (i) Decimal, (ii) Binary, (ii) Octal and
ea Number System: The number system have the base of 10 (as it has
symbols 0,1,2,3,4,5,6,7,8,9).
10 unique

The weight positive powers of ten: 10* 10'10

Binary Number System: This number system has only two digits: and 0 (bits) so the base
1

is 2
Therefore, it is less complicated compared to decimal numbers.
Octal Number System: The octal number system has 8 digits 0,1,2,3,4,5,6 and 7.
t is a base 8 system.
Hexadecimal Number System: The hexadecimal number system has 16 digits 0, 1, 2, 3, 4, 5,
6, 7,8, 9 and first 6 alphabets A, B, C, D, E, F. [O, 1, 2,3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F]
The Alphabets signifies [A=10), [B=11], [C=12]. [D=13]. [E=14], [F=15].
-

It is a base 16 system.
Compliments of a Number: Complement is used in digital computers for simplifying the
subtraction operation and for logical manipulation. There are two types of complements for
each base-r-system. ()r's complement and (i) (r-1)'s compiement
When value of the base is substituted, the two types are received the names 2's and 1's
complement of binary number and 10's and °'s complement of decimal number.
Binary Coded Decimal (BCD): Binary-coded decimal (BCD) is a digital encoding method
for decimal numbers in which each digit is represented by its own binary sequence.
Ir BCD, a numeral is usually represented by four bits which, in general, represent the decimal
renge 0 through 9.
Alpha numeric Code: To represent alphabet letters, punctuation mark and other special
character in computer system we require codes. These codes are called Alphanumeric codes.
Two most popular Alphanumeric Codes
American Standard Code for Information Interchange (ASCI).
Extended Binary Coded Decimal Interchange Code (EBCDIC).
EBCDIC code: EBCDIC (Extended Binary Coded Decimal Interchange Code) is a character
encoding set used by IBM mainframes.
EBCDIC uses the full 8 bits avai lable to it, so parity checking cannot be used on an 8 bit
sysiem. EBCDIC has a wider range of control characters than ASC.
Gray Code: The reflected binary code, also known as Gray code after Frank Gray, is a binary
numeral system where two successive values differ in only one bit.
Fxcess-3 Code: It is a complementary BCD code and numeral system it is used on some
older computers that uses a pre-specitied number N as a biasing value. It is a way to represent
values with a balanced nmumber of positive and negative numbers. In XS-3, numbers are
represented as decinmal digits, and each digit is represented by four bits as the BCD value plus

DSD-2
 DIGITALSYSTEM DESIGN
Wesghted & Non-weighted
Code: Weighted
ned to each symbe position codei a code in which a 'weight' has been
in the code
eighted codes
are commonly word.
Weig used for representation
Exampl BCD, 7421 code, 5211 code, numbers.
eighted 2421 code, 8421
Not codes are detining as Codes in code, Excess 3 ctc.
itions. It is using arbitrary assignmentwhich there are no specific wei
weights assign to
of bit patterns.
Multiple Choice Type Questions
Which one
ne of the following is a reflected
1.

)8421 b) Excess-3 code? WBUT 2006, 2009, 2018]

c) Gray d) ASCI
AnSwer: (c)

2 How, many 1's are present in he binary representation of

x512+7x64 +5x8 +3?
a) 8 b) 9 WBUT 2006, 2007, 2009]
c) 10 )

11
AnsSwer: (6)

Gray code of 1011 (binary)=

a) 0101 b) 1101 WBUT 2008, 20171
c) 1110 d) none of these
AusSwer: (6)

4 An example of reflected code is

a) BCD
WBUT 2008, 2017]
b) ASCII c) GRAY d) Hamming code
ABSwer: (C)

&IF (212), = (23)where x is base (+ve integer), then the value of x is

WBUT 2008, 2010, 20171
a) 2 b) 3 c) 4 d) 5
Answer: (5)

6.8421 is a WBUT 2008, 2017]

a weighted code b) non-weighted code
complementary code d) none of these
Auswer: (a)

greatest negative number which can be stored in computer that has 8-bit
T.
The
ord length and used 2's complement arithmetic is WBUT 2009, 2011]
a)-256 b)-255 )-128 d)-127
Aaswer:
(c)
Theo
decimal number - 15 is represented in 8-bit signed 2's complement notation
WBUT 2010)
a) 11010001
b) 11100111 c) 11110001 d) 10001111
AuSwer:
(¢)

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9. The value of basex for WBUT 2011

which (128)10 = (1003), 1s d) 6
a) 3 b) 4 c)5
Answer: (¢)
10. The Gray Code of (1 1001100)2is WBUT 2011
a) 101 01010 b) c) 10111000 d) 1 1 10001
Answer: (b)
100 1
100

11. Which of the following codes is self complementing? WBUT 2012]

d) Excess 3 code
a) Gray code b) BCD code c) Hamming code
Answer: (d)
12. Which code is used in K-map? WBUT 2013, 2013]
a) Gray b) BCD c)Binary d) Hamming
Answer: (a)
13.Gray code of a number is 10110. What is its decimal number? WBUT 2013
a) 10 c) 27 d) none of these
) 15
Answer: (d)
14. What is Excess-3 Code of 27? WBUT 2013]
a) 0101 1001 b) 0010 0100 c) 0101 1010. d) none of these
Answer: (c)

15. (15)-(10)o is equal to (using 1's complement) WBUT 201M3

a) 0101 b) 1010 c) 1110 d) 0010
Answer: (a)
16. BCD coding of 12 is WBUT 2013, 2018]
a) 00001010 b) 00001100 c) 00010010 d) none of these
Answer: (c)

17. The result of the BCD addition of 00000111 00000011 is

& WBUT 2013]
a) 00001010 b) 00010000 c) 01000001 d) none of these
Answer: (b)

18. The equation

v213 =13 is valid for which one of the number systems with
base? [WBUT 2013]
a) base 8 b) base 6 c) base 5 d) base 4
Answer: (a)

19. The octal equivalent

(5EA)16 is WBUT 2013]
a) 6543 b) 2752 c) 5722 d) 3453
Answer: (b)

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 DIGITAL SYSTEM DESIGN
mple of self-complementing
AnAn
a)
BCD b) GRAY code is
[WBUT 2014]
AaSwer:(d) c) ASCII
d) Excess-3
auumber of bit
required to represent
an eight digit decimal number in BCD
a)8 b) 116 WBUT 2015]
c) 24
ABSwer:(d). d) 32
eGuivalent octal number of
hexadecimal number
a) 6272 b) 5262 AB216 is WBUT 2016]
c) 5268
AISWer: (6) d) 2562

even rity
detector code fails to
2. One bit detect
a) any even number of error WBUT 20171
b) any odd error
) both (a) and (b) number of
d) none of these
Answer: (c)

4.(170)1o is equivalent to
a) FD b) DF WBUT 2018]
c) AA d) AF
Aaswer: (6)

Short Answer Type Questions

LWhat do you mean by arithmetic overflow?
Aaswer:
WBUT 2008]
A
cary occurs when the result of an addition or subtraction, considering the operands
nd result as
unsigned numbers, does not fit in the result. Therefore, it is useful
t carry flag after adding or subtracting numbers that are interpreted as unsignedto check
g when added + 100 and +50, the decimal sum is +50 so, an overflow values.
occurs in MSB
stion, the overflow force to change the sign bit of the answer.
00-01100100
50-00110010
53010010110
ethe sign bit is negative despite the fact that we added two positive numbers.
elore the overflow has produced an incorrect answer.

sing 2's complement method subtract 1011012 from 10111012

WBUT 2012, 2015]
Aaswer:
1011101

0010
101111

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3. What is a BCD advantages and disadvantages ?[WBU

WBUT
2016
code? What are its
Answer:
BCD stands for the Binary Coded Decimal (BCD) and is one of the most widely us
name for the BCD code is 8421
Computer system. Another code
Sometimes 8421 code or the BCD code is also referred to as the Natural Binary Code
Decimal (NBCD).
Major advantages of using BCD code in the digital computer is the ease otrepresentation
and deciphering the coded information into original form. Due to ts simplicity, the Bcp
code finds wide applications in the digital field.
DCD has many different forms of representation and following are some of them.
8421 BCD code, sometimes referred to as the Natural Binary Coded Decimal
Code (NBCD)
Excess-3 code (X$3)
5421 code
8-4-2-1 code (+8, +4,-2,-1)
Biquinary code
The NBCD code is a handy and widely used code for the representation of decimal
quantities in a binary coded fomat. Table gives the list of the BCD codes
1

corresponding to the decimal equivalent.

Table 1: BCD (Binary Coded Decimal)

Decimal BCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
9 1001

Advantages of using BCD Code:

It is easy to encode and decode decimals into BCD and vice versa.
It is also simple to implement a hardware algorithm for the BCD converter.
It is very useful in digital systems whenever decimal information is given
as inputs or displayed as outputs.
u
ither

Digital voltmeters, frequency converters and digital clocks all use BCD a5
display output information in decimal.
Disadvantages of BCD code:
binary
BCD code for a given decimal number requires more bits than the
straignil
code and hence there is diftficult to represent the BCD form in high speea

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 DIGITAL SYSTEM DESIGN
omputers in arithmetic
internai registers are operations, especially their
restricted or limited. when the size and capacly
The arithmetic operations using
Arithmetic and Logic Unit BCD code require a complex n of
(ALU) then the straight
The speed of the arithmetic binary number syste
naturally slow due to operations that can be realized using BCD Couc
the complex hardware
circuitry involved.
Write short note on weighted and
swer:
non-weighted codes. WBUT 2016]
The BCD cods may be weighted
codes or non-weighted codes.
those which obey the position-weighting The weighted codes are
principle. Each position of the number
epresents a specitic weight. For each
group of four bits, the sum of the weights of those
nositions where the binary
digit is 1 is equal to the decimal digit which the group
resents. 8421, 2421, 84-2-1 are weighted codes.
ae not Non-weighted codes are codes whlCn
assigned with any weight to each digit
position, i.e. each digit position within the
number is not assigrned fixed value.
Excess-3(XS-3) code and Gray code are non
weighted codes. There are several
weighted codes.
s.(6 Convert the following decimal numbers into binary:
(a) 72.45
WBUT 2018]
(b) 2048.0625
Answer:
a Decimal to binary conversion: 72.45
72
236-0 0.45x2=0.90-0
2/18-0 0.90x2=1.30
219-0 0.80x2=1.601
24-1 0.60x 2=1.20->1
011100
212-0 0.20x2=0.40-0
1001000
210 0.40x2=0.80-0
0>1

Therefore (72.45)=(1001000.011100),

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b) 2048. 0625
2048
210240 0.625x 21.25->1
2512-0 0.25x 2 0.50->0
101

22560 0.50x 211

2128-0
2640
232-0
2160
218-0
240
212-0 100000000000
21-0
01
Therefore (2048.0625)=(100000000000.101)

(i) Convert the following binary numbers Into decimal: WBUT 2018
(a) 10001101
(b) 10111.1011
(c) 0.1101
Answer:
a) Binary to decimal conversion:
76 5
43210
10001101
=2'x1+2'>x0+2'x0+2' x0+2'x1+2'x1+2' x0+2° x1
=
128 +0+0+0+8+4+ ! 141
Therefore, (10001101),=(141)o

b) 10111.1011
43 210
101112xl+2'x0+2'xl+2xl+2"x
=16+4+2+1
23
1011

I*2"=0.0625
1x2 0.125
0.0625+0.125+0.5
Ix2=0.5
= 0.6875
Therefore, (10111.1011),-(23.6875)o

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 DIGITALSYSTEM DESIGN

0.1101

L Ix20.625
1x2=0.125
Ix20.5
Therefore,(0.1101),-(0.0625+0.25+0.5)
. (0.8125)ho

Long Answer Type Ouestlons

Design a Gray code to Binary converter.
WBUT 2007
Answer:
Gray code to binary
Procedural steps:
Step 1 MSB (left most) in the binary code is
Step 2
same as the corresponding bit of gray code.
Add each binary bit generated to the gray
bit in the reset adjacent position Discard
caty.

Circuit Diagram for gray code to binary conversion

gray I/P

binary o/p

2.
2's complement representatlon has better acceptability than 1's
a) Why
complement representation?
Perform the addition of two negative numbers (8) and (-9) using 2's complement
arithmetic.
Perform the addition of the 91 and 81 using BCD arithmetic. WBUT 2019]
Answer:

2's complement. representation has better acceptability than l's complement

Pesentation because 1's complement has no special usage for negative integers. 2's
on subtraction
ement makes sense because it can be used in natural addition and
DSD-9
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Providing that no overilow occurs

without any need to change the bits.
representation
etic the result is just the right value. In Two's Complement
compleement
vol bits set to zero. And 2's
by having all
ro Is uniquely
rTepresentation represented
is easy to manipulate in hardwarc

b) (8) = (1000),
91 (1001),
9ho in 2's complement= (0110)+ 1l =0111
(8)10-(9=(1000),-(0111)
1000 (0001), = (-1) Proved.
0111
0001
[0-1=1* (*- borrow)]

c)Addition of 91 and 81l using BCD arithmetic:

(81)1000 0001
(91)1001 0001

+1 (Carry)
1000 0001
1001 0001
100100010
Final answer = (81)+ (91)=(172) =(10010 0010)

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 DIGITAL SYSTEM DESIGN

BOOLEAN ALGEBRA

Chapter at a Glance
Boolean Algebra: Boolean algebra
logic variable having is an algebraic logic
only two values I
which deals with logic variable. 1nis
Boolean Logic and 0 alternatively "TRUE"
Operations: or FALSE
AND Operations: AND
gate is a digital logic
gate that implements logical conjunctio
AND Gate
INPUT A
INPUT -oUTPUT
OR Operations: OR gate is a
digital logic gate that
implements logical disjunction.
OR Gate
INPUT A
INPUTB ouTPUT
NOT Operations: It is called
unary operator. NOT Operation
of A is denoted by A.
NOT Gate
INPUT O-OUTPUT
De-Morgan's Theorem: It is state
that complement of the sum
product of the complements of the variable. of variable is equal to the

i.e. A+B =A.B

Representation of SOP (Sum of Product)
form:
MA,B,C)-ABC+AC+BC is known to be in
sum of product form. For a'n variable
if each product term contains all the n variables function
(complemented or uncomplemented), the
function is said to be in Standard Sum
of Product Form and each such product is known
as a
"mintem" (denoted by m), eg. f(A, B, C) ABC +
BC+Bc.
This function is in standard SOP form and it consists of minterms
3 ABC, AB and ABC.

.
In a standard
SOP form, for each minterm an un-complemented variable or literal
is treated as
T' and a complemented literal is treated as *0'. It is denoted by
Representation of POS (Product of sum) form:
FA, B, C) = (A+B +C)(A+C)( B +C) is known to be in product
of sum form. For a n
variable function, if each sum term contains all the n variables (complemented
or un-
complemented), the function is said to be in Standard product of sum form
and each such
Sum is known as a "maxterm" (denoted by M),

CgFA, B, C)= (A+B+C).+B+)(+B+C).

This function is in standard POS form and it consists of 3 maxterms (A+B+C), (A+B+)
and(A+B+C).
astandard POS form, for each maxterm an un-complemented variable or literal is treated as
and a complemented literal is treated as 1'. It is denoted by I1
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 POPULAR.PUBLICATIONS
nent of Bool
management Boolean aigeh
K-map: "The Karnaugh map is a tool to facilitate
only one variabie changes value
expressions. A Karnaugh map is unique in that according to the principles
squares, in other words, the rows and columns are ordered
ofGtz
code.
Functions of K-map: minimal expression of a Boole
() Minimization of Boolean express ession. To obtaining the
reduce the complexity.
n require extensive calculations. Karnaugh mapelimination of potential race hazards,
ha.
(i) K-maps permit the rapid identification and
something that Boolean equations alone cannot do enco
Binary-coded decimal (BCD) is a digital ncoding meho
Binary Coded Decimal (BCD):
by its own binary sequence.
or decimal numbers in which each digit isbyrepresented
four bits which, in general,
represent the decima
In BCD, a numeral is ually represented
range 0 through 9.

LMultiple Choice Type Questions

WBUT 2008, 2017
1.(4 + B+ A'B)C ="
c)C d) C
a) 1
b) 0
Answer: (¢)

2. The minimum number of NAND gates required to design one X-OR gate is
WBUT 2008, 2017
a) 3 b) 4 c)5 d) 6
Answer: (b)
3. A minterm is [WBUT 2010
a) the minimum term in a Boolean function b) a prime implicant
c) always smaller than a maxterm d) a square on a Karnaugh map
Answer: (b)

4. Which gates are used as an array of a programmes in ROM1? [WBUT 2010

a) AND gates b) OR gates
c) Both (a) and (b) d) None of these
Answer: (c)

5. The output of a logic gates is 1 when all its input are at logic zero. The gate
either WBUT 2010, 2018)
a) a NAND or an EX- OR b) an OR or an EX-OR
c) an AND or an EX- OR d) a X-OR or an EX- NOR
Answer: (d)

6. A+A'B +A'BC+A'B'C'D+. WBUT 2010, 2011

a) A+ B+C*... b) A'+B'+C'+.
c) 1 d) 0
Answer: (c)

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 DIGITALSYSTEM DESIGN

output of a gate is low if

The or
7. and only if all its inputs aro high. l WBUT 2011]
a) NOR gate b) AND gate d)X-NOR gate
(d)
c) NAND gate
Answer:

8. [(+ xyz) +x(y + x')N= WBUT 2010]

a) 1 b) 0
c)x d)r
Answer: (d)

The operation which is commutative but not associative is

9. WBUT 2012]
a) AND b) XOR c) NAND d) NOT
Answer: (C)

10. (A+ B+C+D)' equals WBUT 20121

a) A'B'CD b) A'B'CD c) AB'C'D d) AB'CD
Answer: (6)

11.The SOP form of logic expression is most suitable for designing logic circuits
using only WBUT 2012]
a) XOR gates b) NOR gates c) NAND gates d) OR gates
Answer: (d)

12. The simplified form of the Boolean expression (X+Y*Z}(X+Y+z) (X+Y+2) is

WBUT 2014]
a) XY+Z b)X+ Y'ZZ c) X'Y+Z d) XY +Z
Answer: (6)

13. The code used for labeling cell of the K-map is WBUT 2014]
a) natural BCD b) hexadecimal c)gray d) octal
Answer: (c)
[WBUT 2015]
14. All Boolean expression can be implemented with
b) NOR gate only
a) NAND gate only
c) Combination of all basic gates d) Any of these
Answer: (d)

15. The minimum number of NAND gates required

to implement the Boolean
function A+ AB+ ABC is WBUT 2015]
b) two c)one d) zero
a) three
Answer: (c)
HIGH if WBUT 2016
16, The output of a two input NAND gate is
a) both inputs are LOW
D) one of the input is HIGH and the
other one is LOW
c) both inputs are HlGH
d) none of these
Answer: (a), (b), (d)

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WBUT 2016
17 All Boolean expressions
a) AND
can be implemented witn
gates only
b) NOR gates only
c) Combination of AND and OR gates
d) none of these
Answer: (6)

18. In AND-OR relation is equivalent to WBUT 2016)

a) SOP c) K-mapP d) none of these
b) POS
Answer: (a)

T In the figure shown the input condition, needed to produce X= 1 is [WBUT 2018

D
=
a) A 1, B 1, C=1 b) A 1, B= 1, C = 0
c) A 1, B 0, C =0 d) A 0, B 1, C 1
Answer: (6)

20. How many gates would be required to implement the following Boolean
expression before simplification? XY + X (X+Z) + Y (X+Z) WBUT 2018
a) 1 b) 2 c) 4 d) 5
Answer: (¢)

LShort Answer Type Questions

1. Implement the following Boolean expression using decoder WBUT 2013]
=
F(A,B,C,D) zM(1,2,5,7,8,10,12,13).
Answer:

4x16
Decoder
D

2
3

DSD-14
2.
implement
ent the following DIGITALSYSTEM DESIGN
expression
using NOR gate
Answer:
ate only F(4,B,C)- mo 4.6)
WBUT 2014
00
1 10

DD- Jmin

3.Minimize the following

function using K-map:
FIA,B,C,D) = Zm{0,2,3,5,7)
+ Za(8,10,11,15) WBUT 2014]
gates. and implement the circuit using basicc
Answer:

CD
AB0 01 11 1
00
01

11
min

Jmin AC + BD

4. What are the difference between minterms and maxterms? WBUT 2015]
Answer:
A
sum term contains all the K variables of the functions in either complemented or not is
called Max term & complement of max terms called Min term.
Each individual term in a standard (canonical) SOP form is called minterm and each
Representing the
individual term in a standard (canonical) POS form is called maxterm.
us to ntroduce a very convenient
50olean expression in terms on minterms allowS
shorthand notation.
representation of three variables A, B and C.
et us consider the minterm and maxterm

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1abie: Minterm and maxterm representation of three varialbles, A, and

5
No. Variables Mintermss Maxterms
M
A.BC=m=m, A+B+C= M,
A.B.C = m A+B+C =M,|
0 A.B.C=m, A+B+C= M,
=
A+B+C M,
0 A.B.C
m A+B+C= M,
A.B.C
m,
A.B.C=m, A+B+C=M,
1
A.BC =m, A+B+C=M,
A.B.C=m4 +B+C=M,]|
5. Prove that (4+ B)(A +c(B+C)=(A+ B)(A+C). WBUT 2015]
Answer:
LHS RHS
(44+AC+BA+ BC)(B+C) (4+B)7+C)
AAB +ABC + BBA + BBC +AAC+ACC+ BAC +BCC AA+ AC+BA + BC
ABC+ BA+BC+ AC+ BAC + BC = AC + BA+ BC
=(4+1) BC+ BA(1+C)+BC+ AC
BC+BA + BC + ACC
= BC+ BA +AC

6. Using the K-map method, simplífy the following Boolean function and obtain
minimal POS expression: WBUT 2017]
Y=2.(0,2,6,7)+2(3,8,10.11,15)
Answer: CD
DO
AB

12

10
10

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 DIGITAL SYSTEM DESIGN

'ABCD+ ABCD
BCD44)
BC[:(4+)-1 =]
7.
plity the
Simplit Boolean expression Y = AB ABD ABcD BC using K-mapP
method.
Answer: WBUT 2018]
oolean expression, Y = AB +ABD+ ABCD +
BC
UsingKmap method,
K- Map:
B C D
A

Y AB+ABD
ABCD+BC

8.Simplify the Boolean function F =A'C+ A'B AB'C-BC. WBUT 2018]

Answer:
FA'C+BA'BC + AB'C=
A
BC

Map to
the minimum
Reduce the following Boolean function using Karnaugh
possible number of WBUT 2019
B,C,D) m(0,2,3,4,6,7,8,10,12,14,15)+d(1,5,13) literals.
F(4, =

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Answer:
= 10,12, 14, 15) + d(1,5, 13)
(4, B,C, D) m(0, 2,3, 4, 6, 7, 8,

00 O1
0 AB
00
4B

13

-CD

CDAB+ AB+ B+CD+C)

BC
= A(B+) +B + DC + )
= A+ BC + D

Long Answer Type Questions

1. What do you mean by Prime implicant? Simplify the following Boolean
axpression using K-map:
F(4,B,C,D) = m(0,2,3,6,8,11,12,14) +d(1,4,9,10) WBUT 2010
2
Answer:
A prime implicant of a function is an implicant that cannot be covered by a more
general (more reduced meaning with fewer literals) implicant. w.v. Quine defined
a
prime implicant of Fto be an implicant that is minimal - that is, if the removal of any
literal from P results in a non-implicant for F. Essential prime implicants are prime
implicants that cover an output of the function that no combination of other prime
implicants is able to cover.

Using the example above, one can easily see that while xy (and others) is a prime
implicant, xyz and xyzw are not. From the latter, multiple literals can be removed to make
it prime:
x. y and 2 can be removed, yielding w.
Aitemaiiveiy, 2 and w can be removed, yielding xy.
Finally, x and w can be removed, yieldingjyz.

The process of removing literals from a Bóolean term is called expanding the term.
Expanding by one literal doubles the number of input combinations for which the term i
DSD-18
 DIGITAL SYSTEM DESIGN

e (in binary Boolean algebra).

Using the example function
and
expar xyz to y or to yz without
changing the cover off
a0
The sum ofa all prime implicants of a Boolean
function. function is called the complete sum of that
s

CDYB
00 01 11
10
00 0 TOI
01
1 119
11
0Px 13x 150jt
10
OLTO
rCD+CD+ AB + AB=DC+C}+ B{4+4)-D+ B

2. Draw a network using only NAND gate to

generata the function Y ={4+ BC
WBUT 2010)
Answer:

3. a) Simplify the following function using K-map: WBUT 2011, 20151

f=2m(0,5,8,10,11,14,15)+d(3,13)
b) Simplify the following function using tabular mathod: WBUT 2011]
f4,B,C, D)=2m(0,2,3.6,7,8,10,12,13).
Answer:
a)F m(0, 5, 8, 10, 11, 14,15)+24(3,13)

CD
AB 00 01 11 10

00

01

F(4, B.C, D)= BCD+ BCD +AC =C{BOD)+ 4C.

DSD-19
OPULAR PUBLIGATIONS

CD CD
CD CD
AB

AB

12
AB

AB

BD+AC+ABC
Booloan exprossion:
4 Find the minimai sum of product for the WBUT 2013
f=2m(l,3,4,5,9,10,11)+ d(6.8) using K-map
Answer: CD
00 01
AB
00

10

Jmin BD+ AB+ ABBC

using NOR gateonly: WBUT 2012, 2014
5. Implement the following expression
F(4,B,C)=m(0,1,4,6)
Answer:
Given function: F(4. B,C)=2m(0.1,4,6)
K-Map: BC
BC BC BC BC
A 00 11 10

DSD-20
 DIGITAL SYSTEM DESIGN
F = BC + AB+ AC
=(A+ A)BC+
= ABC+ABC+ AB+AC
= ABC+
AB+ AC
AC + ABC+AB
AC[B+1)+ ABC+1)
=
AC+ AB
:1B-1,1+C=1
A+B AB

AC

6. Prove Distributive law

and Absorption law.
Answer: WBUT 2015
Distributive law
. (B+C)= A.B+A.C
2. A+(B.C) = (A+B). (A+C)

Redundancy/Absortive
law
1. A+A.B
=A
2. A.(A+B) = A

A (btcF ab +ac This is called the Distributive Law. Distributivity

is a property of binary
operations that generalizes the distributive law.

7. a) Using k-map method, simplify the following function:

WBUT 2016]
F(w,x.y,z)-2(13,4,5,6,7,9, 12,13)
b) What do you mean by SOP and POs?
c)What do you mean by Maxterm and Minterm?
d)State DeMorgan's theorem.

DSD-21
 POPULARPUBLICATIONS

Answer:
a) 7 11 0
00
MSBWX
00

14

10
=x(W+ )+z(7+w={r+2)
+T(x+z)
F=Wx++17+W
product
logical expression is' logical
a
which each term of the
b) A SOP form is one
are logicaly added (OR)
(AND) of some literals and all the terms logical expression is a logical sum (OR) of
is one in which each term of the
A POS form
multiplied (AND).
some literals and all the terms are logically
Type Questions.
c) Refer to Question No. 4 of ShortAnswer

d) Demorgan's
1*" Theorem
variable is equal to the product of
Statement: It is state that complement of the sum of
the complemenis of the variable.
In general ie. A+B = A.B

A+B+C+D+
.... =A.B.C.D..

Demorgan's 2" Theorem

sum
Statement: It state tha the complement of the product of variable is equal to the
of the complements of the variable ie.,
A.B=A+B

Ingeneral A.B.C.D... = A + B+C+ D+.

8. a) Express De-Morgan's
NAND gate.
theorem and prove that negative logic of an OR gate is
equivalent with
b) What are the limitations of K-map? How can we overcome such limitations?
c) The application of two ways Switch used in stair case is an example of what type
of logic gate? Express the expression f AB + BC +CA using NAND gate only.
WBUT 2019]

DSD-22
AnSwer: DIGITALSYSTEM DESIGN
1" Part: Refer 1o Question
No. 7(d)
of Long Answer Type Questions.
2eMorgan's
Part:
Firsi iheoremproves that
and negateded, they are when two (or more)
equivalent input variables
variables.
Thus the cquivalent to the OR of
of the the comp
mplements
ar D'ed
of the individua!
roving thatA B
A +B and we can NAND
pro *
function and is a negative-OR
show this using the following uno on
Verifying DeMorgan's tabieC.
First Theorem using
Inputs Truth Table:
Trth Table Outputs For Each Term
A.B
(A B) AB

DeMorgan's First Law

Implementation using
Logic Gates:
NAND

AB
B A:B

A-

AB
B~*

Negative-OOR

AB can be implemented using a NAND gate with inputs A and B. The lower logie gate
arangement frst inverts the two inputs producing A' and B' which become the inputs to
ne OR gate. Therefore the output from the OR gate becomes: A' +B"
Thus an OR
gate with inverters (NOT gates) on cach of
its inputs is oquivalent to
can be represcated in this way as
AND gate function, and an individual NAND gate
cquivalency of a NAND gate is a negative-OR

DSD-23
 POPULARPUBLICATIONS

b) The limitations of K-map are:

simplification process increases with the increase in the
*Opiexity ofK-map method for simplification of up
ot variables. A Karnaugh map is an excellent
Oer or six variables, but more than six variables it becomes hard ana complex.
ve
The minimum expression obtained might not be unique

to overcome these types of limitations, use Quine-McClusky method.

e) 1s"
Part:
example of XOR gate. A two-
C appiIcation of two ways switch used in stair case is an
nput AOR gate produces a HIGH output whenever the inputs
are at opposite levels. This
to control passage
oncept of XOR functionality makes it applicable at home/offices
ights, fans, night lamps, staircase lights etc.
being at the ground
Suppose A floor lamp in a staircase has two switches, ane switch
B). The bulb can be turned
Toor (switch A) and the other one at the first floor (switch of the other switch. The
UNOFF by any one of the switches irrespective of the state
Ogic of switching of the lamp resembles an XOR gate whose
Boolean expression is Y =
A'. B + A.B' (Read as: A bar B+ AB bar).

XOR gate Based Staircase-Light Control

5V

Gnd Floor
TL Y=A eB
Ist Floor
R (current limiting)

XOR Logic Implementation

DSD-24
 DIGILALSYSLEM DESICGN

tUsingNAND Gatex the R-map

for the tollowing
llows: flunetion n

A+ BtCA is
SoP((Is)

Circuit Diagram forthe following function

f= AB+ BC+CA

DSD-25
POPULAR PUBLIÇATIQNS

COMBINATIONAL CIRCUITTS

Chapter at a Glance
inputs called
output depends up on the present state of
the IS
Circuit in which
combinational circuit.
Adder: Digital system required adder circuits for addition of two binary digits and
the adder
() Half adder
rcnt gives out two outputs, Sum and Carry. There are 2 types of adder:
(i) Full adder.
A combinational circuit performs the addition of two Boolean variables.
adder:
uenerate the results 'SUM' and 'CARRY' according to the truth table shown. sUM S = A'B
+ -
AB CARRYC AB. We can use Ex-OR gate to implement the circuit for SUM, and using
a AND gate to implenment the circuit for CARRY.

Half
Adder output
input

Full adder: It is combinational circuit which adds three binary digits. it consist three input
and two output bits. Out of three input variable two are denoted by A & B represent two
significant bits. Third input Ci represents the cary from the previous lower significant
position.
Binary parallel adder: A two 4-bit binary adder circuit can be designed by using 4 full
adders. The resulting circuit is called parallel binary adder.
BCD adder: In Binary Coded Decimal 0-9 are valid and 10-15 arc invalid.
Subtracior: Subtractor circuits take two binary numbers as input and subtract one binary
number input with other binary number input. Similar to adders it gives out two output,
difference and boow (Cary in the case of Adder). There are 2 types of Subtractor. (i) Half
Subtractor (ii) Full Subtractor.
cne input line can be egual to I at any
Encoder: In encoder circuit, it is assumed that only
time. An encoder convert an active input signal into a coded output signal. An encoder has 2
numbers of input & n number of output line. The output line generate the binary code fer 2'
input variables.
Decoder: Decoder is a combinationai circuit which convert binary information of n inpt
lines to the maximum of 2" unique output lines.
Multipiexer: Multiplexer is a combinational circuit which transmits multipie number ot
infomation signal over a single signal line A multiplexer circuit having multiple numbers of
input signals & one output signal.
Demultiplexer: The Demultiplexer performs the reverse operation of a multiplexer. It accepts
a signal input and distributes it over several outputs. Demultiplexer is a combinationai circut
which transmit a single line signal over multiple line information signals.
two
Comparator: A digital comparator circuit is a combinational circuit which compare
input digital signal and gives the output as per result. eg. Let A and B are two input signas,
B.
the circuit compare with A and
DSD-26
 If
A B
A> B output1 DIGITALSYSTEM DESIGN
output
A <B
Barrel Shiter: output
=1
number ot bits A barrel shifter is a Otherwise
without the use any digital circuit that output 0.
Universal logic
gates: By thisof
digital system can
sequential logic, can shift a data wordoy
only pure combinational
gate
be implemented. all the Boolean
NAND and NOR function can be implementea
gate are two universal 1.e. a he
galcs.
Multiple Choice
. Type Questions
A decoder with
a) encoder
enable input can
be used as
c) multiplexer WBUT 2009, 2011, 2012
b) parity generator
Amswer: (d) d) de-multiplexer
Parity checker is
2.
used to detect
a) 1- bit error b) 2-bit error WBUT 2010]
Answer: (a) c)3- bit error d) 4- bit error
3. The carry look ahead adder is frequently
a) is faster used for addition because, it
c) uses fewer gatees b) has more accuracy WBUT 2010]
Answer: (a) d) costs less
4. add two m-bit numbers, the
To
number of required half added is
a) 2m-1 b) 2m WBUT 2010]
c) 2
Answer: (a) d) 2m+1
5. The
minimum number of NAND gates required to
design one full adder circuit is
a)5 b) 9
WBUT 2012]
c)6 d) 10
Answer: (b)

The parity of the binary number 100110011 is

6.
WBUT 2012]
a) even b) odd c)2 d) 1
Answer: (b)

1.A decoder with enable input can be used as WBUT 2014]

a) encoder b) parity generator c) multiplexer d) de-multiplexer
Answer: (d)

. The minimum no. of NAND gates requlred to design one full adder circuit ie
WBUT 20141
a) 6 b) 9
9
c) 6 d) 10
Answer:
(b)

DSD-27
POPULAR PUBLICATIONS
ara de
construct m Dit paau BUT 20141
9. How many full adders are required to
d) m+1
a) m/2 b) n c) m-1
Answer: (6) WBUT 2015
10. A full adder can be made out of adder and an inverter
b) two half and a AND gate
two half adder
a)
d) two half adder
c) two half adder and a OR gate
Answer: (c) WBUT 2016]
11. A 4 bit serial adder requires b) 4 half adder
a) a half adder d) a full adder
c) 4 full adder
Answer: (d)
only one output to be activated at one
allows WBUT 2016]
12. Which of the following devices
time? b) Demultiplexer./
decoder.
a) Multiplexer d) none of these
Encoder
c)
Answer: (6)
serial converter?
can be used as parallel to
13. Which one of the following b) Digital Counter WBUT 2018]
a) Decoder d) Demultiplexer
c) Mult lexer
Answer: (c)
having two points A and B the correct set of logical
14. For a binary half adder WBUT 2018]
(=A+ B) and (= carry) are
expression of the output b) S = A'B+ AB'& C AB
AB+ A'B &C= A'B
a) S d) S AB+ A'B'& C = AB'
A'B+ AB' & C= A'B
c) S
Answer: (¢)
2 :1 MUX required to realize a 2-input AND gate is
15. The minimum number of WBUT 2019]
c)3 d) 4
a) 1 b).2
Answer: (a)

16. The minimum number of 2:1 MUX required to realize a 4:1 MUX isWBUT 2019
1 b) 3 c) 2 d) 4
a)
Answer: (6)

17. Without any additional circuitry,

an 8 :1 MUX can be used to' obtain
a) Some but not all Boolean functions of
3 variables WBUT 2019
b) All functions of 3 variables but none of 4 variables
c) All functions of 3 variables and some but not all of 4 variables
d) All functions of 4 variables
Answer: (b)
DSD-28
 DIGITALSYSTEM DESIGN

Short Answer Type 9uestions

1. eian a
Design full-subtractor using
only NOR gates. WBUT 2010
Answer:
NOR logic
Boolean expression

d ADBb,
(AB)b, +(A®B)b
I(A®B)+(A®B)b,] [b, +(ADB)b,]
(A®B) + (AGB)+b, + b, + (A®B)
+b,
=(AB) + (ADB)+b, +b, +(ADB) + b,
b AB+b, (A®B)
A (A+B)+(AOB)[(A®B) + b,]
=A+ (A+B) + (A®B) + (A®B)+b,
Circuit Diagram

bi
Fig: Logic diagram of a full subtractor using only 2 input NOR gates

2.
Prove thatthe NAND gate is called a universal gate. Implement an EX-OR
(2-input) logic using NAND gates. WBUT 2010]
Answer:
All
gates/functions can be implemented by NOR or NAND gates. so they are called
other
universal
gates. In fact, in chips, entire logic maybe built using oniy NAND (or NOR)
ates. e.g: inverter NAND with inputs shorted. And NAND followed by an inverter
Using NAND).
Or giving inverted inputs to NAND gate. If you delve deep into realms of
VLSI
you may be able to understand the reason. Implementing with NAND is easier
nen considering power and area of the chip.

DSD-29
POPULARPuBLICATIONSs

EX-OR Gate using NAND Gate

Y ADB

BAB

Y= A.AB.B.AB
Using Demorgan's 2d theorem
or, Y=A.AB +B. AB
B) +B(A + B) =AA + AB + BA + BB
=A4+
AB+ AB =A®B

3, Design a 4 to 16 decoder by using two 3 to 8 decoders. Write down the

WBUT 2010, 2018]
corresponding truth table.
Answer:

3:8

D
EN

Da

o Ds

EN

Implement 4 x 16 Decoder using two 3 x 8 Decoders.

4. Design acircuit using logic gatos which will generato

binary number. What is the function of a parity checker? the odd parity of 3-bit
WBUT 2010]

DSD-30
Answer: DIGITALSYSTEM DESIGN
lowing is the truth table
and K-map
P(even)
for even parity
0

0
1

K-MAP:
00 01
11
10

Hence the equation

we get is P (even)= x xor y xor
OR z
P.(even)= x xnory xnor z
Following is the truth table andK-map
for odd parity
a P(odd)
0

0
i 0

K-MAP:

00 01 1 10

Ce the equation we get is P (odd) = x xnor y xor 7* XXor y xnor z = (X Xor y xor zy
xnor y xnor z)
DSD-31
POPULAR PUBLICATIONS
number of variables,
change with odd or even
Hence we see that equations for Parity

For odd number of variables xnor y Xnor z

P(even parity) = x xor y xor z =x xor y xnor z= (x xor y xor z) (* Xxnor y xnor z)'
xnor y xor z=x
tOdd panty)= x
Parity Checker parity bit for even parity checker there
with the
checks the bits in the message along
tshould checker there should be odd
number of
be even number of I and for odd parity
in the received bits. Otherwise error will
occur.

Truth Table for 4 bit even parity checker Check

Received bits

P
wX
0
00
11

10

C w x®y®P

DSD-32
 DIGITALSYSIEM DESIGN

Circuit Diagram

DD -c

Fig: 4 bit even parity checker

.Obtain the logic expression for a 3-input majority function and hence implement
t using only NAND gates. WBUT 2011, 2015]
Answer:
Truth table of full adder

From truth table we have

S m(1,2,4,7)
C- m(3,5,6,7)

K map for S
BCi 01 11 10
00

ABC
ABC, +ABC, + ABC, +
S

DSD-33
POPULAR PUBLICATIONS

K map for C.
BC 00 01 10

C =AB+ BC, +AC, D-

D-

6. Design a using two half-subtractors and one extra gate, if necessary.

WBUT 2011]
Answer:
Bar in

D D -D

Bar out

Full subtractor using two half subtractor

7. Design a 4-bit comparator. Show the output functions only. WBUT 2011
Answer:
The logic for a 4-bit numbers be A = 4,444, and B = B,B,B.B,
=
1. If
4 =1;B, 0then A> Bor
2. If 4, and B, coincide and if 4, =], B, =0 then A> Bor
3. If A, and B, coincide and
if A, and B, coincide and if A, =1, B =
Othen A> B
or
4. If 4, and B, coincide and if 4, and B,coincide and if A
and B coincide and
A =1,B, =0 then A> B.

DSD-34
 DIGJAL SYSIEM DESIGN
Prom above statements, logic statements
ABG4,8,*(4,0B,)4,B, for A> Bcan be written as,
+(4,OB,)4,0B,)4B
Similarly
dy
(40B,4,0B,)(4OB)4,B,
for A < B, above expression
can
A<B: G A4,B, be written as,
+(4,0B,) 4,B,+ (4, B,)(4,OB,)
O 4B
(4,0B,M4,0B,)(4
Aand B,
coincide and if OB)4B,
4, and B, coincide and
nd B, coincide then A =B. if A and B coincide and it
A
sothe expression for
A= B can be written
as,
M=(4,0B,)(4, B,)(AOB)(4,O
0 B,).
Design a carry look aheead
adder.
OR, WAUT 2012]
Mhat is Carry Look Ahead Adder?
Answer: WBUT 2018]
Alook carry adder is a type of adder used
ged by reducing the in digital logic. A look carry
amount of time required to determine adder improves
CAntrasted
with the simpler, but usually carry bits. It can be
calculated alongside the
slower, ripple carry adder for which the carry bit
sum bit, and each bit must wait
en calculated to begin calculating its until the previous carry has
own result and carry. The look
alculates one
or more carry bits before the sum, which carry adder adder
te result reduces the wait time to calculate
of the larger value bits.
he serial
binary adder is a digital circuit that performs binary
2mal full addition bit by bit. The
adder has three single bit inputs for the numbers
here are
to be added and the carry in.
two single bit outputs for the sum and carry out.
PEviously calculated The carry in signal is the
carry out signal. The addition is performed by adding
west to highest, each bit,
once each clock cycle.

Given the logical

NAND expression U =(4 + BCXB+ CA). Design the circuit using
gates.
WBUT 2013)

DSD-35
POPULAR PUBLIGATIONS

Answer:

D
AC D u-(AB+AC Bc)

BC

10. Draw and explain the circuit of 8*1 MUX using two 4*1 MUX and one 2x1 MUX.
[WBUT 2013]
Answer:

Ds 4:1 MUX
Fa
D
D

2:1 MUX

Output

Do -
D 4:1 MUX

D O-
D
Selects

DSD-36
 DIGITALSYSTEM DESGN
Can adecoder be used as
should be present with the a demultiplexer?
11.
If it is possible what harawar
feature
decoder? WBUT 2014]
Answer:
decoder, this circuit takes
As a d an n-bit binary number
MAutput lines. we and produces an Output on one of
If use this circuit as a demultiplexer,

=D-
IN
OUT

OUT

OUT

OUT

b)
Cascade two 2-to-4 decoders to form 3-to-8 decoder. WBUT 2014]
Answer:

2-to-4 Decoder

Ao

C
C

2-to-4 Decoder

E
C

Ci

121
plement a full adder circuit using
3 to 8 decoder with all active high outputs
WBUT 2014, 2017]
other necessary Iogic gates.
OR,
WBUT 2018
gn a Fullaaddercircuit using 3: 8 Decoder.

DSD-37
 OULARPuaLtCATIONS

Auxwerr Carry Sum_

Inputs
C

3-to-8
Decoder

13. Design 4:1 multiplexer using 2:1 multiplexer. WBUT 2015]

Aaswer:
are two inputs then in 2: 1
MUX, output, Z will be,
If D and D
Z DS+ Ds
For 4:1, MUX, if D, D, D and D, are four input then
4:1 MUX output will be,
Z=35,D,+SS, +S5,D, +S,5,D,
So,4:1 MUX can be realized by two 2:1 MUX.

DSD-38
 DIGITALSYSIEM DESIGN
De

MUX
D 2:I
D
D
2:1 MUX
oz
D
D
MUX
D
4:1 MUX
14. Implement a full adder circuit
Answer: by using two 2:1 multiplexers.
WBUT 2017]
Eqv.
Decimal
0

0 0 0

Truth Table
Let us assume a, b, c are the inputs and s is the sum and c is the carry adder.
of
Now, S=abc
C= ab +bc +ca
Cireuit Diagram using MUX For Sum (S) output

MUX

DSD-39
POPULAR PuBLIGATIONS

Circuit Diagram using MUX for Carry output (C)

MUX

4x1

16. Design a full adder using minimum number of NAND gates. WBUT 20171n
Answer:
Truth table of ful adder

From truth table we have

S m(1,2,4,7)
C 'm(35,6,7)

DSD-40
 DIGITALSYSTEM DESIGN
map for S
BC,
00 11
10

S A BC,+ AB,+ ABC, + ABC,

K map for C.
BCi 00 01 11 10
o

Co =AB+ BC +AC,

D-

are logic gates? Why are they called so? Realize the expression
What universal wBUT 2019
AC+ BC' using NAND or NOR gates only

DSD-41
 POPULAR PUBLICATIONS

Answer: NOT gates

" Part: basic OR, AND and are
gate because
NAND and NOR gates are universal
mentioned gales.
designed with the help of the above

2nd
Part:
= gate
S AC + BC' using NAND
A

C-

LLong Answer Type Questions

one 2 to 4 and four 3 to 8 Decoder IC.
1. Design a 5 to 32 Decoder using WBUT 2007
OR,
block
decoder with four 3x8 decoder and a 2x4decoder. Show
Construct a 5x32 WBUT 2007
diagram only. OR,
decoder and 2 :4 decoder. WBUT 2016
Design 5:32
a decoder using 3:8
Answer: here A is the MSB & E is the LSB.
ABCDE
Let us consider 5 input lines are
are A & B and output D,D,D,D3 are enable
1s we have to use 2:4 decoder whose inputs each
3x8 decoder respectively. CDE are the 3 input line of the 3x8 decoder,
signals of 4 lines.
of the decoder produces 8 output

DSD-42
 DIGITAL SYSTEM DESIGN

-Yo
3 :8
N -Y7

s
3:8
A (M.S.B D D Yis
D
B
2:4

Y16
3:8

D Y23

Y24

Y31

E.LSB)
2. Design a odd parity generator for sending
instructions/data of 8-bits.
WBUT 2010]
Answer:
A serial parity bit generator is a two terminal circuit which received
coded message
and adds a parity
bit to every m bits of the message, so that resulting outcome is
an error
detecting coded message.
The parity bit
are inserted in the appropriate spaces so that resulting outcome is a
continued string of symbols without spaces. For even parity, a parity bit 1 is inserted if
and only if the number of ls in the preceding string of three symbols is odd.
For odd
parity a parity bit 1 is inserted and only if the number of Is in the preceding
string of
three symbols is even.

Odd parity bit Generator

late diagram and state table of an odd parity bit generator are shown below.

DSD-43
 POPULARPUBLICATIONS

PS NS
x0
B,0 C.0
D,0 E,O
E,0 D,0
F.0 G,0
D
G,0 E,0
A,I A,I
A,0 A,0

State table

B
o0
D
o0 10 o/0

State

3. Design a full adder using two half adders and necessary gate. WBUT 2010
OR,
Construct a full substructure by using two half substructures and an OR gate.
WBUT 2017
Answer:
Full Adder Circuitfrom HalfAdder Circuit
Block diagram
A2
S2 S
falf Half
adder adder
B- B Co
B Co2

Fig: Block diagram of full adder circuit using half

adder circuit

DSD-44
 DIGITALSYSTEM DESIGN
Circuit diagram

Co

Ci

Boolean expression
S=A®BOC, (1)
C= A.B + (A B).C,
C = AB+(AB + AB)C;' = AB(1+C,)+(AB + AB)c,
AB+ ABC, + ABC, + ABC, + ABC,
= AB + BC,(4+4)+ AC,(B+B)
=AB+ BC, + AC, (2)
The equation I & 2 are representing the sum (S) Carry (C.)
of a full adder circuit.

4.a) What are the differences between the Decoder and Demultiplexer?
WBUT 2010, 2017]
b) Form a multiplexer tree to give 4x1 MUX from two 2x1 MUX. [WBUT 2010]
Answer:
a) A decoder is a device which does the reverse of an encoder, undoing the encoding so
that the original information can be retrieved. The same method used to encode is usually
Just reversed in order to decode.
A demultiplexer (or demux) is a device taking a single input signal and selecting one of
many data-output-lines, which is connected to the single input.
They are different as most decoder will use multiplexer instead of demultiplexer to do the
job.
A decoder rearranges a single signal into a more usable signal.
A demultiplexer splits one compound signal into many signals.

DSD-45
 POPULAR PUBLICATIONS

D) We can implement 4 to 1
MUX from 2 to
1
MUX as shown below

DO
2t01
MUX

2101
MUX

0 2t1
MUX

5. a) What is MUX? What are its applications? WBUT 2012

b) Design a full subtractor using 4 to 1 MUX.
Answer:
a)

D
4:
MUX -oD

Application of Multiplexers:
Multiplexers find numerous and varied applications in digital
systems of all types. These
applications include data selection, data sorting, operation sequencing,
parallel to seria
conversion, waveform generation and logic function generation.

b) Binary Full Substractor

4:1 MUX
D

4:1 MUX
B

DSD-46
 DIGITAL SYSTEM DESIGN

0
0

D=xy'z+Xyz +yz+ xyz

D=xy+x'z + yz = x'yz+x'yz +xy'z+xyz
D.y)=21.24,7) :
B(zjz) = 2(2,3,1,7)
Table forD
Do Di D Da

Table 1
forB
Do D DD3
0O
45 6O
6. Design BCD to excess-3 decoder using suitable logic gates. WBUT 2012]
Answer:

0
0 0
0
0 0
0
0
0

0
0
0 0

,-m(5,6,7,8,9)
-m(1,2,3,4,9)
E-m(0,3,4,7,8)
DSD-47
POPULAR PUBLICATIONS

E -m(0,2,4,6,8)

D
A

4:16
Co 0- decoder
DO

Es

7. a) Design a Full Adder circuit sing 3:8 Decoder.

b) What is priority encoder? Write the truth table of 4-input priority encoder.
c) Implement the following function using 8:1 MUX:
WBUT 2013]
F(4,B,C,D) = 2 m(0,1,3,4,8,9,15) + d(5,10,13).
Answer:
a) Sr, y, 2)=2m1,2,4,7) = sum
C(r, y, )=m(3,5,6,7) = carry
Since there are 3 inputs and a total of 8 minterms we need a 3 to 8 decoder. The
implementation is shown in figure below.

8
decoder

b)
Inputs Outputs
Fo F F
0 PA.
0
B

0
0 0 0
x
X X

DSD-48
 DIGITAL SYSTEM DESIGN

A D D D D
A
5 6 715
13 14
+5V 0 A

D,
D
D. F(A, B, C, D)

B C D

8. a)Draw and explain the BCD adder circuit

using commercially available IC-7483
and other necessary logic gates.
Answer:
WBUT 2014]

BA BA BA BoAo

C
Cout 4 Bit Adder
S3 S So -CN

From next lower

digit C= 0 for
L.S. digit

Bit Adder
CN

To next higher
digit
S0

Design Binary to gray code converter using logic gates. WBUT 2014]
Answer:
INPUT OUTPUT

B B,B,| B, |GGGG
00000000
000
100
O01||0
DSD-49
POPULAR PUOLICATIONS

INPUT OUTPUT

000 L0
0 0
I00
0 0

All the entries of B, A and G are same in truth table.

G B
BB
B,B
00 01 10

00

10

G, =B, B,
BBy 00
BaB
01
10
01

1
10

G B, 9B
B,Bi D0 01
B,B 10
00

10

G, = B, ®B

DSD-50
 9. a) What is the difference DIGITALSYSTEM DESICN
Answer: between full-adder
A full adder and full-subtractor wBUT 2015
dinar numbers
subtractoris a combinational and accounts
circuit, which for values carried in as well as out
b)Show is used to perform subraction ru
how a full-adder ot S Da
an inverter circuit. can be
converted to a full-subtractor
Answer: with the ado

D B

c) Design a full
D-
subtractor using two half-subtractors
necessary. and one extra gate, if
Answer: WBUT 2015]
Bar in

-BeT

Full subtractor using two half subtractor

10. a) Design the following function using suitable MUX: h: WBUT 2016)
F(4,B,C,D)=2(1.3,4,11,12,13,14,15)
b) Design a 16:1 MUX using 4: 1 MUX.
) Design full substractor using two half substractor.

DSD-51
POPULARPUBLICATIONS

Answer:
a)
CD
11 10
AB 00 01

00

11

10

F AB+ BD+ABD+ACD
or F AB+BCD+ ABD + BCD.

b)
Do
Y
D 4:1
2
MUX

sS
Dy

0SI So

Ds 4:1
D MUX
D-

4:1 Y
MUX

4:1
Dio MUX
Du
S S2

Di2 oSSo
Dis 4:1 Y4

Diu MUX

Dis

DSD-52
 DIGITAL SYSTEM DESIGN

Subtractor Cìreuit from Halfsubtractor Circuit

D Bar out

ull subtractor using two half

subtractor

11.Draw and explain the BCD

adder using 7483. WBUT 20171
Answer:
iP iVP O/P
Y
D D Z
0

11 10
YY 00
00 01 01 11 10

D +x

Y 00 01 11 10

DSD-53
POPULAR PUBLICATIONS

Y
D
X
Do

CLK

10 00 01 11 10
00 01 11 X

=m++2 D +X +2 *Hy2

12. Form a multiplexer tree to give 8:1 MUX from two 4:1 MUX and 2:1 MUX.
WBUT 2017

DSD-54
 Answer: DIGITALSYSIEMDESIGN
-1 MUX using two 4:1
MUX and 2:1
Data input MUX

MI

N A (MSB)
Logic 0 So S

BO

Co
Output

Logic 0
CN
Logic 0

13. Draw and explain the circuit of BCD

adder. ls it possible to replace the
correction circuit of this adder by comparator
(digital)? Explain. WBUT 2018]
Answer:
part:
BCD stands for binary coded decimal adder circuit. This circuit shows the 4 bit adder
circuit which have two input and one output.

Input
4 bit
BCD Output
Adder Cireuit

DSD-55
eoPULAR POLICATIONS

C
4 bit Adder
Carty
S' S S

Binary sun

n' 4 bit Adder BCD sum

S S2
S

Ss S2 S
Fig: 4 bit BCD adder

The logic circuit that detects the necessary correction can be derived from the entries in
the table. It is obvious that a correction is needed when the binary sum has an output
cary k 1. The other six combinations from 1010 through 11l1 that need a correction
have a 1 in position zs to distinguish them from binary 1000 and 1001, which also have a
I in Zs. The condition for a correction and an output carry can be expressed by the
Boolean function,
C-K+Z,2, +Z,2
When c=1, it is necessary to add O110 to the binary sum and provide an output cary for
the next stage.
A BCD adder that adds two BCD digits and produces a sum digit in BCD is shown in the
figure.

2d part:
It is possible to replace the correction circuit of the Binary coded
adder by comparator.
Without a carry, it can be possible. If c' is I then it replaces from BCD
to the comparator.
14. Draw and explain 4-bit parallel adder circuit. What are the differences between
serial and parallel adder circuit? Also draw and explain the
serial adder circuit.
WBUT 2019)

DSD-56
 Answer: DIGILALSYSIEMIDESICN
1" Part:
A parallel adder is an
one bit of data arithmetic
simultaneously. combinational logic circuit
However, to add more A full adder that is used mor than
than one adds two 1-bits and carry to add
parallel adder
A bit
of data in length, a togve av
Simultaneousiy, adds corresponding a parallel adder is usea.
bits simultaneously
significant bit to it keeps generating a carry using full acde
be added. An and pushing it towards
with each full n-bit parallel the next n
adder adding the adder uses n full adders
two corresponding connected in Caxo
Bn An
Bn-1 An-I
bits of both the numbers.
B3
2

FAn
FAn-I
FA3 C3 FA2
Cn-1 FAI C
Cout

Sn Sn-1
3 S2
Fig. 4 bit parallel adder
Working principles of
1. As shown
parallel Adder -

in the figure, firstly the full

carry Cl to generate the sum adder FAl adds Al and B1
along with the
Si (the first bit of the output
which is connected to the next sum) and the camy C2
2. Next,
adder in chain.
the full adder FA2 uses this carry bit
C2 to add with the input bits A2
to generate the sum S2(the second bit and B2
of the output sum) and the carry C3
again further connected to the next adder in chain which is
3. The process continues and so on.
till the last full adder FAn usés the carry bit
its input An and Bn to generate the last Cn to add with
bit of the output along last carry bit
Cout.
2sd
Part:
Difference between Serial Adder and Parallel Adder:
Serial Adder Parallel Adder
1. It is used to add two binary numbers in. It is used to add two binary
numbers in
Serial form. parallel form.
2. A serial adder uses shift registers. 2. A parallel adder uses registers with
parallel
loads.
8. It requires single full adder. 3. It requires multiple full adders.
Carry flip-flop is used in serial adder. 4. Ripplecarry adder is used in parallel adder.
5. S
5. Parallel adder is a combinational circuit.
adder is a sequential circuit.

DSD-57
POPULAR PUBLICATIONS

3rd Part: digits of arbitrary length, starting

serial strings of as itS output. (The
adder accepts as input two streams
senatthe low order bits, and
produces the sum of the
two bit
simultaneously). This
n
put dit streams could come from, say, two
shift registers
clocked

device can be easily described as a state machine. case of an adder, thie is easy; all that
"remembered" - in the
We first decide what must be
carry to be added into the next highest
is a
must be remembered is whether or not there = 0(C), and carry=1(C),
as
have two states, cary
order bits. Therefore, the device will
states, and the
identify the transitions between the
shown in the Figure. We next
necessary outputs, also shown in Figure shown below. inputoutput
11/0 01/0
00/0 10/0
01/1
11/1
10/1 00/1
as follows:
We can derive a state table from the state diagram state Output_
Present state| Inputs Next
Co
C
C
C

Co

C C
Circuit Diagram:
Serial input

Full Adder

Serial input
Serial input

Memory
Element

15. Write short notes on the following:

a) Even Parity Generator & Checker
WBUT 2007, 2008, 2013, 2016
b) Parity checkerlgenerator
c) Two-bit Comparator WBUT 2011]
WBUT 2013, 2014
DSD-58
 DIGITALSYSTEM DESIGN
d) Encoder
Shift registers WBUT 2015]
4 bit Parallel Binany adder
Answer:
WBUT 2017]
WBUT 2018]
a)Basicidea
B
0
B, B,
0 0
00 01 10
01 0
011
I00
1

ii
P B, B, B, +B, B, B, + B, B, B
B, B B + B, B, B, + B, B B, +B, B,B
B, (B,B, + B, B)+ B, (B, B, +B, B,)
B,(B, B)+ B, (B, B,)

Parity Checker
t checks the bits in the message along with the parity
bit for even parity checker there
should be even number 1
of and for odd parity checker there should be odd
in the received number of1
bits. Otherwise error will occur.
Truth Table for 4 bit even parity checker
Received bits Check
0

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POPULAR PuBLICATIONSs

wx00 01 11 10
00

C=wr®y®DP

Circuit Diagram

Fig: bit even parity

b) Parity checker/generator:
1: Parity Generator circuit which received coded
message
A serial parity bit
generator is a two terminal an error
so that resulting outcome is
-

every m bits of the message,

and adds a parity bit to
detecting coded message. spaces so that resulting outcome
is a
inserted in the appropriate
The parity bit are For even parity, a parity bit is
1
inserted if
symbols without spaces.
continued string of string three symbols is odd. For odd
Is in the preceding of
and only if the number of Is in the preceding string of
I is inserted and only if the number of
parity a parity bit
even.
three symbols is

Odd parity bit Generator

an odd parity bit generator are shown below.
State diagram and state table of
PS NS
x 0
B,0 C,0
D,0 E,0
D,O 0/0
C E,0
F.O G,0
D
G,0
A,I
F.0
A,I
O
o0 I000
A,0 A,0
State table
State Diagram

DSD-60
 Even Parity
Bit Encoder DIGITAL SYSTEM DESIGN
B B B
0 0 0
0 0 1
0
B
Bo 00 01
10 0
oO
11

0
p B, B, B,+B, B,
B, + B, B, B, =
B,(B,B, + B, B,)+ B, B, B, B, +B, B,B,
(B, B, + B, + B, B, B,+B, B, B,
B,)=B, (B, 9 B,)+ B,
(B, O B,)
2: Parity Checker
It checks the bits in the message
should be even number of l along with the parity
and for bit for even parity checker
odd
in the received
bits. Otherwise error parity checker there should be odd numberthere
will occur. of i
Truah Tablefor 4 bit even parity
checker:
Received bits
Check
0

0
P
WX 00 01 11 10
00 101
11
010T
1oT00
wr®yO P
.C =

DSD-61
POPULAR PUBLICATIONS

Circuit Diagram

D
D
Fig: 4 bit even parity checker

c) 2-bit comparator:
A<B
AL A>B 0

Using K-maps AAo

BBo 00 01 11 10
AA
BBo 00 01 11 10 00
00
01 0 0 01 0

110 0 0 11
O
00
10 00 0
O
(4>B)- 4+4,5,+44
(A=B)=AB, +44,BB, +44,8,4, + 44,3B,
A(4,+A,B,)+ 4B,(4,B, + 4,8,)=(4, 0B)4O,)

DSD-62
 DIGITAL SYSTEM DESIGN
A1Ao
B,B, 00 01 11 10
00
01 0
10

A<B A,B, + A,B,B, +A,A,B,

Bi

EDA (A B)

DO- -(A = B)

Checking A =B
IfA XNOR Bo = 1
and A1 XNOR B =1 then A=B
Checking A >B
A is
greater then B if Aj AND B, =1 OR Ag AND B, AND (B, OR Aj)= 1

Checking
A<B
AND B, =1 OR A, AND B, AND (B, OR,) =
1
Ais less than B if A,
Ihis conductions are implemented in above circuit indicate X NOR operation.

d) Encoder:
to the function performed by a decoder.
n encoder performs a function which is inverseoutput Iine. The output line generate the
encoder has 2" nos. of input & n nos. of
Dinary
code for 2" input variables. I at any time.
line can be equal to
encoder circuit, it is assumed that only one input

DSD-63
 POPULARPUBLICATIONS

Shows block
convert an input signal into a coded output signal. Fig.
Cncoder active
which is active. Intemal
agram of a encoder. In this fig. 2" nos. of input line only one ofoutput witn n nos. of bits
OgIC Circuit of the encoder convert the active input to a binary

Block diagram

2 input Encoder

n nos of output

e) Shift registers:
a shift let
A shift register moves the stored bits left or right. The block diagram of
register is shown in the following figure:

Block diagram

D,

Clock

Explanation
When Din = 1;Q= 0000
The arrival of the first rising clock edge sets the stored word as
Q 0001. This new word means Di now equals as well as Do. When next positive
1

clock edge hits, Q, flip-flop sets and register contents become

Q0011
The positive clock edge results in Q=0111 and fourth rising clock edge gives Q=1111.
Hereafter, the stored word is unchanged as long as Di=1
A shift register can be used in for different configurations depending upon the way in
which the data is entered into and taken out of it. These four categories are: Serial Input
Serial Output; Parallel Input Serial Output; Serial Input Parallel Output; Parallel Input
Parallel Output.

Types of Shift Register

Serial input, Serial output (SISO)
The data can be moved in and out of the register, one bit at a time.

Parallel inpa, Serial ouput (PISO)

Data can be loaded simultaneously but data can be removed from the register one bit at a
time by clock pulse.

DSD-64
Serial input, Parallel DIGITAL SYSTEM DESIGN
output (SPO)
Da is loaded serially one
bit at a time
Parallel input, but the data stored
Parallel output can be rread simultaneously.
Data can be loaded into (PIPO)
simultaneously. stages simultaneously
and an also be taken out or read
Serial in -
Serial out Shift
A basic four-bit shift
Registers
register can be
The operation or constructed using four
the circuit is as follows. D flip-flops, as shown below
outputs to zero. ne T The register is first cleared, forcing
input data is then
flop on the left (FF0). applied sequentially
to the
al tour
During each clock pulse, D input of the first tiup-
right. Assume a data one bit is transmitted frórm let
word to be 1001.
shifted through the
register from FF0 to The least significant bit of the data has to be
FF3.
Block diagram
Data
FFO
Inpup SET D
FF2 FF3
Q SET D SET Q D Data
SET9Output

CLR CLR Q LCLR Q CLR Q

CLK
CLEAR

Timing diagram
Parallel in - Serial out Shift Registers
A four-bit parallel in serial out shift register is shown below.
-
The circuit uses D flip-
flops and NAND gates for entering data (i.e., writing) to the register.
DO, DI, D2 and D3 are the parallel inputs, where DO is the most significant
bit and D3 is
the least significant bit. To write data in, the mode control line is taken to LOW and the
data is clocked in. The data can be shifted when the mode control Iine is HIGH as SHIFT
is active
high. The register performs right shift operation on the application of a clock
pulse, as shown in the animation below.

DSD-65
 POPULAR PUBLICATIONS

Block diagram
D3
D2
D

SA

CLK a2

CLEAR

Serial in - Parallel out Shift Registers

manner as discussed in
for tis kind of register, data bits are entered serially in the« same
the last section. The difference is the way in which the ta bits are taken out of the
registr. Once the data are stored, each bit appears on its respective output line, and all
bits are available simultaneously. A construction of a four-bit serial in parallel out
register is shown below.

Block diagram Q

Input FF2 FF3

FFO FFL
DataD
SET SET
D

SET Q SET

CLR Q CLR O CLR

CLK CLEAR

Paralel in - Parallel out Shift Registers

For parallel in - parallel out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits. The following circuit is a
four-bit parallel in parallel out shift register constructed by D flip-flops.
-

The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is
clocked, all the data at the D inputs appear at the coresponding Q outputs
simultaneously.

DSD-66
 DIGITALSYSTEM DESIGN
Block diagram
Do
Di
D

D SET
D SET D
SET Q D SET QF

LCLR
CLEAR
CLR CLR Q CLR Q

CLK
Qo
Q Q2 I

4 bit Parallel Binary adder:

By using full adder Circuit
any two bits can be added with
of bits are more than one, third input as carry. If numbers
then full adder circuits are cascaded. Addend
are applied simultaneously & Augend bits
at inputs to the full adders carry generated
significant stage is transferred to in the Lower
the next higher stage so that it can be added there.
A B B2
A B Ao Bo

Ca FA EA

Ss 2 S 0

Fig: 4 bit Parallel Binary Adder.

DSD-67
POPULARPUBLICATIONS

SEQUENTIAL CIRcUITS

Chapter at a Glance
on
depend on the present state but also depend
sequential circuits, the output not only flip-flops. () Eage-triggered
flip-flop.
Thethe past state of the system. There are two types of
(ii) level- triggered flip-flop. the brief instant the clock
switches fronm
responds only during
An Edge triggered Flip Flop clock, it
triggering occurs on the positive going edge of the
one voltage level to another when it is called
Positive-edge triggering and when triggering occurs in the negative edge,
IS called
Negative-edge triggering.
responds only a particular stage i.e. either high or low switching
A Level triggered Flip Flop
for a time.
Flip Flop, JK Flip Flop and Master
Slave
Ex: Flip Flop can be divided into RS Flip Flop, D
JK Flip Flop.
RS Flip-flop: RS Flip-flop used as restoring
information. It has two stable states, which can
S inputs. The flip-flop will assume one of
its
be achieved by giving proper inputs to R and
two stable states depending upon any asymmetry in the circuit.
RO

CLK

Block diagram
JK Flip-flop: JK flip-flop is modification of SR
S -
Logic diagram
flip-flop. Here we overcome the race
condition which occur in JK flip-flop JK fip-flop is called an universal flip-1lop because the
other flip-flops like D, R-S and T can be derived from it.

CLK-
SLK

Block diagram

Logic diagram
D lip-lop: D Flip-Flop is a flip-flop with a delay (D) equal
to exactly one cycle of the
In D flip-flop input to R is through an inverter from
S, so that input to R is always
clo
complement of S and never same.
T lip-flop: A T Flip-flop has a single control input, labelled
T for toggle. When T is HIut
the flip-flop toggles on every new clock pulse.

DSD-68
 uistert A tegister ia
Regis DIGITALSYSIEM DESIG
group of
inds namely Tter
regisler and memory elements that
Shin teri A shin register Shin register
regixter work ugether as a unit. It is of two
ether a* *

registets. moves the

e stored
9107ed bits lefi or right.
0)Serinl input sertal output (81sO» There are 4 types of shift
a time. The data
canmoved in and out of the regso bit a
)Parallel input serial
TOVed from the output (PISO): data
regisler one bit can be
lt) Serinl iput at a time by clock loaded simultaneously Du o can be
stored can be read paralel output (SIPO); data is loaded
pulse
simultaneously serially one hit al a time but he aaa
(v) Parallel input parnllel
d an
also he laken out or output: (PiP0): data can be loaded into
read simultaneously. stages simultanieou
Universnl silft register;
A register which
PIPO, SIPO) with bi-directional is capable to operate all modes
4
shining (1e. SIO,
Ring counter: A serial output
of a shift
of data is known as "Universal
regjster ""
feedback pulse will register is connected back to the serial
keep circulating. This input then ue
Counter: A counter is a special kind circuit is referred to as ring counter,
arriving at an input. (0) Asynchronousof register, designed to count the number of clock pulses
counter (2) Synchronous counter
Finite state machine; In finite state
1. Input: State machine
machine have following properties:
huve inputs which is called
2. States: For example; light symbol,
switch-on, heat sensor
3. Transitions: When the state machine changes its off
state, it is called
a transition.
Actions: An action is a rather generic description for
4.
anything that can happen in a
state machine.
There are two types of Finite state machine.
(i) Moore Machine
(i) Mealy Machine.

LMultiple Cholce Type guestions

1. The characteristic equation of the T-F/F is given by
WBUT 2006, 2008, 2009, 20171
=
'T0+T b) Q' T+0T d) Q=TØ
Answer: (a)
2.A ring counter consisting of 5 flip-flop will have WBUT 2007, 2008, 2013]
a) 5 statess b) 10 states c) 32 states d) infinite states
Answer: (c)
WBUT 2008, 2017]
that marks output equals to input after clock
&. FTE is
c) T FIF d) none of these
a) J-K FIF D F/F b)
Answer: (b).
WBUT 2010]
flip-flop is called a latch when it is
.A)edge trigger b) level trigger
d) without any trigger
c)both (a) and (b)
Answer:
(a)
DSD-69
POPULAR PUBLUICATIONS
BST
5. A flip-op is also known as
muitivibrator
b) bistable
a) astable multivibrator these
c)a switch
d none of
AnSwer: (b)
WEUT 2011
mod-16 ring counter
is
number of flip-fiops required for a ) 16
he a) 4 b)8
c) 15
Answer:(a)

by using a single D flip-fop. The resulting

Switch-tail ring counter is made WEUT 211
.A
circuit is d) T flipfio
a) SR flip-fiop b) JK flip-fiop c) D flip-flop
Amswer: (d)
WBUT 2011, 2012
8. A decade counter counts up to d) 12
a)9 b) 10 c) 11
Answer: (b)
WBUT 2012, 2014
9. A flip-fiop has
a) One stable state b)two stable states
d) none of these
c) no stable states
Answer: (u)
gWBUT 2012
10. The unversal register
a) accepts serial input b) accepts parallel input
) gives serial and parailel outputs d) all of these
Answer: (d)

11. How many flip-flops are required to design Mod-10 Counter?

WBUT 2013, 2013]
a) 3 b) 4 c)5 d)6
Answer: (b)

12. you want to convert a JK FF to a D-FF then which gate is to be connected

between J &K terminals of the JK FF? WBUT 2013
a) AND b) OR c) NOT d)EX-OR
Answer: (c)

13. an asynchronous counter have three flip-flops with identical, tpd =

50ns then
what is the total propagation delay and the maximum
frequency? WBUT 2013
a) 150 ns &6.67 MHz b) 160 ns & 5.67 MHz
c) 140 ns & 2.23 MHz d) none of these
Answer: (a)

DSD-70
 DIGITALSYSIEMDESIG
ster slave configura
uration ls
used in flp flop
increase its clocking rato to WBUT 2014
iminate race around conditlon b) reduce power dissipation
AnSwer: (c)
d) Improvo its reliability

adulus 10 Johnson counter

A mod
ten flip-flops requires wBUT 2014
i
a) five flip-flops b) four flip-flops
c)
d) twelve flip-flops
Answer: (c)

hich
Whicof the following flip-flop
&

flip-flop ls used as a latch? WBUT 2015]

a) J-K b) S-R flip-flop c) D flip-flop d) T flip-flop
AaSwer: (b)

.
An asynchronous counter is also known as
counter
a) ripple wBUT 2015
b) multiple clock
counter
decade counter
c)
d) modulus counter
Answer: (a)

18, A MOD 13 counter must have [WBUT 2015]

a) 13 flip-flop b) 3 flip-flop c) 4 flip-flop d) 2 flip-flop
Answer: (c)

9. Which of the following is an invalid state of an 8241 BCD counter? [WBUT 20151
a) 0010 b) 0101 c) 1000 d) 1100
Answer: (c)

20. A ring counter is WBUT 2016]

shift register
a) b) synchronous counter
c) up-down counter d) none of these
Answer: (d)

21.
Number of flip-flop required for a mod 15 ripple counter is WBUT 2016]
a) 3 b) 4 c) 5 d) 6
Answer: (b)

2. Asynchronous counter differs from a synchronous counter in WBUT 2016]

a) the mod number b) the method of clocking
c) the type of flip-flop used d) the number of states in a sequence
Aaswer:
(6)

4.A master slave configuration consists of two ldentical flip-flops connected in

ch a way
that the output of the master is input to the slave. Which one of the
ollowing
is correct ? WBUT 2018]
triggered
Master is level triggered and slave is edge
9 Master is edge triggered and slave is level triggered

DSD-71
 POPULAR PUBLICATIONS

and slave is negative odge triggered

Casterisis positive edge triggered
triggered and slave is positive edge
triggereod
ESTer hegative edge
Answer: (a)
37 clock
24. The initial state of MOD-16 down counter is 0110. What will be after
it
pulse?
WBUT 2018]
a) Indeterminate b) 0101 c)0001 d) 0110
Answer: (c)

25. An n-stage ripple counter can count upto WBUT 2019]

d) 2"1
a) 2"
Answer: (6)
b) 2- c)

26. A 4-bit modulo 16 ripple counters uses J-K flip-flops. If the propagatlon delay of
each flip-flop is 50ns, the maximum clock frequency that can be used is equal to
WBUT 2019]
a) 20 MHz b) 10 MHz c) 5 MHz d) 4 MHz
Answer: (c)

27. Flip flops are WBUT 2019]

a) combinational circuit b) sequential circuit
c both (a) and (b) are true d) none of these
Answer: (6)

LShort Answer Type Questions

1. Discuss the difference between combinational and sequential circuit.
WBUT 2007
OR,
Differentiate combinational logic circuit and sequential logic circuit. WBUT 2014
OR,
Write down the difference between combinational circuit and sequential circuit.
WBUT 2016]
Answer:
L Combinational Logic Circuit Sequential Logic
combinational logic circuit is one that
1. A
Circuit
the output depends only on the current Output
1. A sequential logic circuit is one that the
depends both on the current input,
input, not on any previous inputs. as well as previous inputs.
2. Combinational logic do not have 2.
Sequential Logic Circuit have memory.
memory
3. Combinational logic circuits
implement| 3. Sequential circuits compute their output
Boolean functions, so they are
functions| based on input and state, and that the state
only of their inputs, and are not based on is
updated based on a clock.
clocks.
4. Propagation delay 1s more._
4 Propagation delay
is less.
DSD-72
 DIGITAL SYSTEM DESIGN
c<plain the circuit
operation of a Master-Slave
AOwn
write downi
the corresponding truth JK flip-flop using all NAN04
table. WBUT 2010, 2012]
Answer:
glock diagram of Master-Slave
N

J-K Flip-Flop

Master
Slave

K
,
CLK

Logic Circuit
Logic diagram

CLK-

Master Slave
The Master-Slave Flip Flop is level clocked. When clock is high; therefore any changes
inJ and K can affects and R outputs. For this reason, normally we keep J and K constant
during positive half cycle of the clock. After clock goes low, master becomes inactive
and we allow J and K to change. The truth table is shown below.

Truth Table for the Master-slave J-K Flip-flop

PR CLR CLK K Q

Toggle
i
Timing diagram
master-slave J-K flip-flop as shown in Figure
et us now examine the operation of the
below

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 PoPULAR PUDLICATIONa

SET
RESET
RE SET
Fig: Operation of master-slave J-k flip-flop

3. Dosigna mod-7 ripple counter using CLR lines of JK flp-flops. WBUT 2011]
Answer:
For designing arbitary sequence Counters, first we determine the number of flip flops
required in this case, since maximum count is 7.So 3 flip flop will be required.
We prepare a table of present state and next state and then find at JK input required for
desired transition according to excitation table.

Present State Next State JK Flip Flop TFF DFF RS FF

K R
0
0

The state transition 7- 4-6-0-5 are below

Present State |Next State Flip Flop2 Flip Flop1 Flip Flop 0
Q Q1 Qo Q Q QoJa K2
J Ki Jo Ko

0 0
I0 0 X

0 x
0 0 0
101
11 1
K map for J2 K map for K2

Q01LL
011 1 0001 11 10-
0 X

xx
J1 K Q1Q
DSD-74
 DIGITALSYSTEM DESIGN

Q Qo
Q000 11 10 Q2 00 O1 11 10
0 x 0 x

Ki

0001 10 O0 0111
X X

0 X X

Jo KoQi

FF2 FFi
FFo

CLK

Counter, which cycles

Logic diagram of the synchronous
through the 7-4-6-0-5-7 using J-K flip- flops

D flip-flop. WBUT 2012]

Design a JK flip-flop using
Answer:
for D Flip Flop is shown in Table
ne truth table of JK Flip Flop and characteristic table
I and 2. D

0-0
01
10

1 Table 2
Table
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ne K map for D F/F final implementation is shown in Table

3 and ig
10
KQ, 00 01 11

1
00
D KO, +
JK Table 3

D J+ Q K

D
J-

Conversion of D Flip-Flop to JK Flip-Flop

5. What is race around condition? How can we overcome the race around
condition? WBUT 2013, 2018]
OR,
Explain race around condition of JK flip-flop. Show how this condition can be
avoided. WBUT 2016]
Answer:
Race around condition occurs when both the input are high And the output thus
undergoes a transition state. For example, Consider the input values in a J-K flip flop;
i.e.; J=K=1 ,the Output q0=0 in normal case will change to l and vice vesa.
The remedy for race around problem can be eliminated by using a master slave J-K flip
flop.

6. Find the characteristic equation of a JK flip-flop. WBUT 2013

Answer:
Excitation table for JKFF
Characteristics, e,. =Je, +KO,
QnQn+1
0 X

7. Explain parallel in serial out shift register with block diagramn. WBUT 2014

DSD-76
 swer: DIGITAL SYSTEM DESIGN
Afr
Refer 10Question No.
17(6) of Long
Answer Type Questions.
Convert J-K flip-flop
to D flip-flop.
Answer:
flip-flop can WBUT 2015]
ersion be
operate as a
from J-K to D D flip-flop as
flip-flop shown in Fig. 1. The truth
inputt data will be transferred is shown in Table table o
Inpical at the 1. It is depicted
de in table that the
expressions tor J and output
K is derived Jwhen clock is applied
ied. Using this table, the
as = D, K
=
D.
Trath table of conversion
D flip-slopp from JK to T flip-flop
Output JK flip-flop
inputs
D inputs
0
CLK
0

Fig: 1
Conversion JK flip-flop
to D flip-flor
9.Briefly describe Johnson counter with proper
Answer: diagram. WBUT 2016]
Refer to Question No. 17(a) of Long Answer Type Questions.
10.
Realize aD flip-flop by using aT flip-flop and
other required logic gates.
Answer: WBUT 2017]

D=TQ, +TO, =Te,

Truth table
QnQn1
0.
0

0 0

ruth table for D Flip-flop and characteristic table for

1T
flip-flop is shown below.
D Qnsl

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Q+Qat
0- 0
0-

So it can be written as, T = Q,D +Q,D implementation 1s

D
D CLK

11. What do you mean by edge triggered and level triggered flip-flop. [WBUT 2018]
Answer:
Refer to Chapter at a Glance
12. Draw the circuit diagram of a J-K flip flop and explain its operation.
WBUT 2019
Answer:
Characteristic Table of J-K Flip-Flop
As we have already discussed about the characteristic equation of S-R flip-flop, we can
similarly find out the characteristic equation of J-K flip-flop. The characteristic table of
JK nip-lop is given in table shown here. From the characteristic table we have to find
out the characteristic equation of the J-K flip-flop.

Flip-flop Inputs Present Output Next Output

the
Now we will find out the characteristic equation of the J-K fip-flop from
characteristic table with the help of Karnaugh map given in Figure.

DSD-78
 DIGITALSYSTEM DFSIGN

00 KQ.
10

From the Karnaugh

map, we obtain
Hence the characteristic

Circuit diagram:
Q, = J2, + KQ,
equations of J-K
flip-flop is, = JQ, + K2,

CLK

K
-
Long Answer Type Cuestions
1.
Write down the characteristic equation of J-K flip-flop.
WBUT 2007, 2012]
Answer:
Excitation table for J-K flip-flop
Qa Qnt

Characteristic equation for J-K. flip-flop

eJ,+ KQ,
2.What is the major difference between the two classes of finite state machines
and proper state diagram? WBUT 2010]
Answer:
every type of State Machine has all or
late Machines exhibit some basic properties. Not
nem, but they always have at least one of them:
DSD-79
 eOPULARPUBLICATIONSs

nput: State Machines have input. These are usually called symbols.
States: For example: lightswitch-on, heatsensor-oft, etc
changes its state, this is called
nsitions: When the State Machinescondition,a The condition is determined
transition usually requires
nsionA
by the input, the current state or a combination of both.
can happen
Acttons: An Action is a rather generic description for anything that
a state Machine. Actions may be performed when entering or exiting a state,
when input is read, when a state transition occurs, etc.

Types of State Machines

There are two types or Finite-State Machines which are typically used in computer
programs:
Acceptors / Recognisers
Transducers

The Acceptors/Recognisers read bits of input and in the end tell you only if the input
was accepted or not. One example would be a State Machine that scans a string to see if it
has the right syntax. Dutch ZIP codes for instance are formatted as "1234 AB". The first
part may only contain numbers, the second only letters. A State Machine could be written
that keeps track of whether it's in the NUMBER state or in the LETTER state and if it
encounters wrong input, reject it.
Transponders on the other hand continuously read pieces of input and for each piece of
input produce either some output or nothing. What it produces can depend on the input
and the current state of the machine. A good example of this is a string parser that alows
the user to enclose a part of the string in quotes so that it is treated as a single item. On
the Unix shell this is used to refer to file names with a space in them. The State Machine
reads one character at a time. When a space is read, it assumes a new element is starting.
If it encounters a quote, it enters the QUOTED state. Any characters read while in the
QUOTED state are assumed to be part of the same
non-quote char
element. When another quote is encountered, the State
Machine transitions to the UNQUOTED state.
A State Diagram is a visual method of describing a
State Machine. There are many varieties of State UNQuOTED
Diagrams, each with different rules. The basic form
though can be seen in figure I, which describes the
state machine from the previous example. quote char
quote har
In this example diagram the start state (UNQUOTED)
is indicated by the arrow coming out
of nothing going QuOTED
into the UNQUOTED state. The "quote char"
arrows
are transition conditions. Whenever a quote character
is encountered, the State Machine
changes state. It is
debatable whether we should include
the "non-quote nen-quote char
char" arrows, since they do not Fig. 1:Quoted string parser
indicate a state
transition. However, since we want State Diagram
to model all the
DSD-80
input we can re
receive,
action of adding we will DIGITAL SYSTEM DESIGN
include
are internal Words to them.
nem. This
to the This particular
a state are list when a partic
te Machines
use of UML State
as implemented en in classical
State
not modelled white space occurs.Diagram does not modei
This is because actions
Diagrams. in computer
Omputer programs, State Diagrams. When odeling
you may therefore
3. What is preset want to make
cOunt sequence table counter?
8aDistinguish from 000 to 100. Design a MOD-5
between a counter that counts
ripple counter its natural
What is the
th difference and a synchronous
OR, cour
ounter. WBUT 20101
counter? between
Answer:
the synchronous
counter and asynchronou8
a)A MOD-5 counter WBUT 2012
The flip flops will go through
will be required. the following states 000-001-010-011-100-000
below: The truth table
and the flip flop
inputs are shown in
Present State table
Next State
Flip-lop Inputs

Q%
00 01 11 00
00 0 0 00 01 11 00

TQ%

Q10
Q 00 01 11 10

0X
To-
D Q

DSD-81
 POPULAR PUBLICATIONSs

b) Ripple counters with its D (data) input fed

from
D-type flip flop,
Simplest counter circuit is a single zero to
C store one bit, and hence can count irom
s own itnverted output. This circuit can once for every
(starts from 0). This counter will increment
one before it overflows over It will alternate
clock cycles to overflow, so every cycle
COCK Cycle and takes two to 0. Notice that this creates a
betweena transition from 0 to
1
and a transition from
frequency of the input clock. If this
new clock with a 50% duty cycle at exactly half the (remembering
as the clock signal for a similarly arranged D flip tlop
output is then used that counts half as
get another bit counter
1

tO invert the output to the input), you will

fast. Putting them together yields a two bit counter:
cycle Q1 Q0 (Q1:Q0)dec
0000
1011
2102
3
113
4000
always inverting the output to its own
You can continue to add additional flip flops,
flip flop as the clock signal. The result
is
input, and using the output from the previous
counter, which can count to 2n-1 where n is the number of bits (flip flop
called ripple
a overflows
in the counter. Ripple counters suffer from unstable outputs as the
stages) application as dividers for clock
"ripple" from stage to stage, but they do find frequent
is.
where the instantaneous count is unimportant, but the division ratio overall
signals,
(To clarify this, a 1-bit counter is exactly
equivalent to a divide by two circuit the output
train of clock pulses)
frequency is exactly half that of the input when fed with a regular

Synchronous counters
bits, which is the case in most
Where a stable count value is important across several
also use flip-flops, either the D-
counter systems, synchronous counters are used. These
stage is clocked simultaneously by a
type or the more complex J-K type, but here, each
control data flow
common clock signal. Logic gates between each stage of the circuit
counters
from stage to stage so that the desired count behaviour is realised. Synchronous
and may be
can be designed to count up or down, or both according to a direction input,
are ot
presettable via a set of parallel "jam" inputs. Most types of hardware-based counter
this type.
is
4. a) Explain race-around condition in SR flip-flop. Explain how this condition
avoided in JK flip-flop.
b) Draw the timing diagram of a 3-bit ring counter. WBUT 2011(EE)]|
Answer:
tnus
a) Race around condition occurs when both the input are high And the output
undergoes a transition state. For example, Consider the input values in aj-k flip flop; Le
j=k=1, the Output qo=0 in normal case will change to 1 and vice versa.
The remedy for race around problem can be eliminated by using a master slave j-k IP
flop.
DSD-82
Timing diagram of DIGILALSYSIEMDESIGN
The timing diagram 3-bit ring
of 3-bit counter
ring counter
is shown below.
UUUuUUUtL
L
Q-

5. a) Design a
4-bit up/down
other necessary logic synchronous sorial counter
counter will count gates. Use one using flip-flops and
up and for D = direction control input, JK
D. If D* o
b) Draw the
circuit diagram of a 1, the counter will count down.
output waveforms mod-8 ripplo counter
state diagram.
also. Obtain the state table and using JK flip-flops. Draw the
hence show the corresponding
Answer: WBUT 2011(EE)]
a) 4-bit up counter
Step 1: Determine the number of flip-flops
A 4-bit
up counter requires 4 flip-flops. required
0011, 1000, 1010, ... The counting sequence is 0000,
0001, O010,
Step 2: State diagram is to
be drawn.
Step 3: Select the type of
flip-flops and excitation table is to
JK flip-flops are be drawn.
selected and excitation table is to be drawn.
Step 4: Minimal expression is to
be obtained
Minimization is to be considered by considering K-maps.
Similarly 4-bit down counter is to be considered.

b) MOD-8 ripple counter

MOD-8 ripple counter can be formed by connecting one
MOD-4 counter and one MOD-
Z counter
in cascade. The connection is shown below.
-***

MOD-4 Counter
Q991 Q9

F I' F
CLK
CLR
CLR

MOD-2 Counter

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WBUT 2012
6. Convert an SR F/F to a TF/F.
Answer:
SR to T flip-flop
The excitation täble for above conversion is shown bejow
Present StateNext State Flip flop Inputs
Input
Qnt

K-map simplification For R

For S Qn

R-TQ
S=TO,

CP

SR to T flip-flop conversion

If we apply clock pulses to the circuit, the circuit output will toggle from 0 to & to 0.
1 1

Thus we can build 1-bit counter using SR flip-flop by converting it to T flip-flop.

7. a) Design a mod 6 ripple counter. WBUT 2012]

b) Design a mod 3 synchronous counter
Answer:
a) Design of MOD-6 ripple counter:
1. Here N=6 and the number of FFS required is n=[log, 6]=3. The use of 3 JK flip
flop is necessary and they are named as A, B & C. Assume that these three flip-flop are
negative edge triggered flip-flop.

DSD-84
 DIGITAL SYSTEMDESIGN
The state dagram otthe MOD-6
counter iN

(000)
Temporary
states

001)

T00) (O10

011

f we assume a starting count

of 000, the diagram shows that the states of the counter
change normally until the count
of 101. When the next clock pulse occurs, the counter
temporarily goes to the 10 count betore going to thhe
stable 000 count.
The dotted lines indicate the temporary nature
of the 110 state. The direction of this
temporary state is sO short that for most purposes
we can consider that the counter goesS
directly fiom 101 to O00 (solid arrow). 111
state was never reached, not even
temporarily.
The logic diagran for the MOD-6 counter is
shown below.
AL.SB)
C(MSB)

_ Ke_

Logic Diagram

he inputs to the NAND gate are the outputs of

the flip flops B & C, so, the NAND gate
=1, until that the NAND gate output is HIGH (which
Utput is low when O, =
1

& Q.
Oes not affect the clear input of
any flip flop). The condition will occur when the counter
pulse).
Soes from 101 state to the 110 state (6 clock

DSD-85
 POPULAR PUBLICATIONS
(gcnerally a few
output will immediately cieared, the
ne LoW signal at the NAND000gatestate. Once the flip flops have Deen exists.
dnoseconds) clear the counter to =1 & Q. =I condtion no longer
the 0, temporary state)
NAND output goes back to HIGH, since 011, 100, 101 & (110
sequence is therefore 000, 001, 010,
Counng since its natural count has
000. counter
called 'permuting
nis type of counter is sometimes
before it
been permuted (changed). remains for only few nanoseconds
goes to the 110 state it counts from 000 to 101 and
Atnough the counter this counter
we can essentially say that 111 so that it goes through only six
eycles to O00.to Thus 110 &
nen recycles 000. It essentially skips MOD-6 counter.
different (000 to 101) states, thus it is called
is shown in figure.
The timing diagram of MOD-6 counter

eiioT7ejo
NAND output o
naia
Fig: Timing diagram of MOD-66 ripple
counter

mnomentary
B output contains a "*spike or glitch" caused by the
The waveform at the not
clearing. This glitch is narrow and so would
occurance of the 110 state before
visible indication on numerical displays. It could cause a problem if the
produce any counter. C flip flop output has a
used to drive other circuitry outside the
output is being is
equal to the 1/6 th of the input frequency. The waveform at flip flop output
frequency for 4
symmetrical square wave, because it is HIGH for only two clock cycles & low
not a
clock cycles.

b) MOD-3 Synchronous counter

A MOD-3 counter requires two flip flops. The
counting sequence (22) of MOD-3
counter would be 00 0110

the nex
Each input clock cycle advances the counter to the next state. After 00, =10,
clock cycle resets the counter back to 00. When counter changes state from
changes state from > 0 and hence require clock transition. However,
1

change state and hence cannot provide such a clocking transition. So a ripple counter
,
10 to 0,
does n0

une
not possible in this case because in it one of the flip flop receives the clock input from
DSD-86
 DIGITAL SYSTEM DESIGN
gate output of the other flip
MOD-3 counter. An flop. So a synchronous
to synchronous
analysis clock«operation is necessary to design
Aiagram of MOD-3 excitation table
counter reveals for JK flip flop and state
that transio
J= K =1
K, =1
The resulting MOD-3 counter
circuit is given below:

FF-1
FF-2
CK CK

Clock input
MOD-3 synchronous counter

8. a) What is
lock out state?
b) Write a short note on Ring [WBUT 2013]
c) Design Mod-6
Counter? WBUT 2013, 2018]
synchronous counter using JK fiip-flops and other
gates.
Answer: WBUT 2013]
a)
Data Lock-Out Flip-flops The data lock-out flip-flop is
similar to the pulse-triggered
(master-slave) flip-flop except it has a dynamic
clock input. The dynamic clock disables
(locks out) the data inputs after
the rising edge of the clock pulse. Therefore,
do not need the inputs
to be held constant while the clock pulse is HIGH.
The master
section of this flip-flop is like an edge-triggered device. The
becomes a pulse-triggered device to produce a postponed output
slave section
on the falling edge of the
clock pulse.
The logic symbols of S-R, J-K and D data lock-out flip-flops are shown
below. Notice
they all have the dynamic input indicator as well as the postponed
output symbol.
Again, the above data lock-out flip-flops have same the truth tables as
that for the edge-
nggered flip-flops, except for the way they are clocked.

9 The simplest shift register counter is essentially a circulating shift register connected
So that
last flip-flop in the shift register is in some way connected back to the first flip
op. Most widely used shift register counters are ring counter and Johnson Counter.

DSD-87
POPULAR PUBLIGATIONS

Block diagram

cik
CIA

FLlTiLTL 4 5 6

Timing diagram

Ki J K2
c) Q2 Q Qo Jo Ko J
0 x x
So 00 00
0
1 x

0 0 0
1
S3
0 0 0
S4
1 0 x

S
X

0 0 0

DSD-88
 DIGITAL SYSTEM DESIGN
QQ1
Qo
00 01

1)

000 01
0

Ko= 1
(2)

00 01 10
0

Q:01
J, = , (3)

Qo 00 01 10
0

K = Q2 + Qo 4)

00 11 10

0 0

(5)

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POPULAR PuBLICATIONS
Q:01 10
Qo O0

..(6)

waveform and state diagram of J-K flip-

.a) Write the truth-table, circuit diagram,
flop. WBUT 2014
b) Convert D flip-flop to J-K flip-flop.
Answer: .Hear we overcome the race condition
flip-flop
aJK fip-flop is modification of SR called an universal flip-flop because the other
flip-flop is
which occur in JK flip-flop .JK
from it.
flip-flops like D, R-S and T can be derived

Block diagram,

CLK

Block diagram of JK Flip-Flop

Logic diagram

-Q

Logic diagram

Truth Table Operation

J [K
Rising edge Hold (no change)
|ee
E Rising edg
Rising edge 0
Reset
Set
Rising edge Toggle

DSD-90
 Timing diagram DIGITALSYSTEM DESIGN
Let us now consider the J-K
in Figure
below. Again, flip-flop
we assume operation as illustrated by the waveform
that Q is HIGH initially. alagra

SET HOLD
RESET
TOGGLE
Fig. for J-K waveform
diagram
State Diagram:
JK 1,0 or 1,1
J.K 0,0
J.K 0,0

Q-0

J,K 0,1 or 1,1

QnJK
00 0
D
0 01 0
101
100
010
101
D=KQ,+JQ.

DSD-91
 eOPULAR PvoLICATIONS
WBUT 2014, 2018]
differonces betwoon LATCH and flip-flop?
0. a What are the
tlip-flop state
Answer:
and are used to store binary data but inoccurs without
Both nip-flop and lateh are bi-stable in latch, change
state
edge or pulse whereas are not.
change only occurs on a clock that Flops are clocked but latches
concluded Flip
cing clocked. So can be
it
Construct an Ex-OR gate using only NOR gates (two npuis)

AB AB

WBUT 2014, 20181

b) Deelgn MOD-3 aynchronous counter using J-K flip-flop.
Answer:
PS NS Excitation /P

Q.01 Q:0
0x 1x K, =1
00
01 10 xI J
10 00 0x

CIk
E
) Design MOD-6 ripple counter using negative edge trigger J-K flip-fop
WBUT 2014, 2018

DSD-92
 DIGITAL SYSTEM DESIGN
Answer:
CIk
Q001 ResetR
0
000 0 R ,0,0, +0,0,0
00 1 0
010

100
101 0
6
110

000 0
000

CIk-

11.What is ripple counter? Design a presentable 4-Bit up asynchronous counter

using J-R FF. A binary ripple counter is required to count to (16383)0. How many
FFs are required? If the clock frequency is 8.192 MHz, what is the frequency at the
output of the MSB? WBUT 2016]
Answer:
" Part:
Asynchronous (ripple) counters:
The simplest counter circuit is a single D-type flip flop, with its D (data) input fed from
S Own inverted output. This circuit can store one bIt, and hence can count from zero to
one before it overflows (starts over from 0). This counter will increment once for
every
ciOck cycle and takes two clock cycles to overflow, so every cycle it will alternate
etween a transition from 0 to I and a transition from to 0,. Notice that this creates a
I

frequency of the input clock. If this

Dew clock
with a 50% duty cycle at exactly halt the
Output is then used as the clock signal for a similarly arranged D flip flop (remembering

DSD-93
 eOPULARPUBLICATIONS

to the input), vou will get another

1
bit counter that counts half as
nvert the output
fast. Putting them together yields a two bit counter:
cycle Ql Q0 (Q1:Q0)dec
0000
1011
2102
3113
4000

Ou can continue to add additional flip flops, always inverting the output to its own
mput, and using the output from the previous flip flop as the clock signal. The result is
called a ripple counter, which can count to 2n-1 where n is the number of bits (flip' flop
stages) in the counter. Ripple counters suffer from unstable outputs as the overflows
"ripple" from stage to stage, but they do find frequent application as dividers for clock
signals, where the instantaneous count is unimportant, but the division ratio overall is
(To clarify this, a 1-bit counter is exactly equivalent to a divide by two circuit - the output
frequency is exactly half that of the input when fed with a regular train of clock pulses).
2nd
Part:
The 4-bit counter needs four flip-flops. The circuit for 4-bit up/down ripple counter is
similar to 3-bit up/down ripple counter except that 4-bit counter has one more flip-flop
and its clock driving circuiting. The Fig. 1 shows the 4-bit up/down ripple counter.
M

High-

CLK

Fig: 1
4-bitasynchronous up/down counter
3rd Part:
The nurnber of FFs n is to be selected such that the number of states N<2". With
n FFs, the largest count possible is 2"-1. Therefore,
2"-1=16,383
or, n=log, 16,384 = 14
So, the number of FFs required is 14.
Frequency at the output of last stageis
MHz
8192 500Hz
h 16,384

DSD-94
12. Design MOD
OD 10 asynchronous DIGITAL SYSTEM DESIGN
Up/Down counter
v with JK fip-flop.
Answer:
WBUT 2016]

1 cr o
Clock
input clr C

Control
up/down
1/0 logic
deactivated
We are considering
active low preset
& clear 1/P

00 01
10
00
01

10

=0,0 +Q,2
T-represented disallowed states in counter
13. Draw the timing diagram of a D flip-flop & D-latch for the given input signals.
WBUT 2017]

aUUUUL
CLK

INPUT LUL

DSD-95
POPULAR PUBLIGATIONS

Answer: Regular D-atch response

D
m
L

Outputs respond to input (D)

during these time periods

Fig: Timing diagram of a D latch

Ck D Q(+1) Q

CIK

(b) Graphical Symbol

(a) Characteristic Table

CIk

D L

(c) Timing diagram Time

Fig: Timing diagram of a D flip-flop

DSD-96
 DIGITAL SYSTEM DESIGN
Design a sequential
14.
lD-type flip-flops circuit that
implements
for the design. the following state diagram. Using
WBUT 2017]
I/0
O/0

O/0

I0

O/1
Answer:
State Table:
Present state Next State Output
X=0 X=1| X=0 X=1
S 0

So
So

D
F/F

D
Ck

counter using J-K flip-flop and necessary

15. Design a 5 Mod synchronous binary WBUT 20171
logic gates.
Answer: below
counter is shown in figure
The state diagram of mod-5

DSD-97
POPULARPUBLICATIONS

O-
State diagram
is shown below.
Three flip-flops are required to implement it. The circuit diagram

CLK

Qo

16. Design a counter with the following binary sequence

T-Flip Flop.
(0, 1,3,7, 6, 4) and repeat
using WBUT 20181
Answer:
1" part:_
Present State Next State Filp-Flop state
B A
0
0
X

0
x
0 0
0 0 0

DSD-98
 DIGITALSYSTEM DESIGN
TA=A B ;
TpBC
BC 00 01 11
10
oToto 010
Tc=AC + A'C'

010
A Not self correcting

A
BC 00 01 1 10
Tc AC + A'B'C'

(101 010 100

self correcting

1. Write short notes on the following:

Johnson Counter WBUT 2007, 2013, 2014, 2017]
Parallel-In-Serial-Out (PISO) WBUT 2007, 2013, 2014, 20181
c Switch-tail ring counter WBUT 2011 (EE)]
Lock-out phenomena in counters WBUT 2011(EE), 2015]
e)
Irregular counter WBUT 2015]
Master-slave JK flip-flop WBUT 2017, 2018]
Aaswer:

Johnson Counter:
lhnson counter, inverted output of last state Flip-Flop is fed back to the input of the
ist state Flip-Flop. After that an unique sequence is generated due to feed back. The
gIcuit diagram
of the above counter is shown below.

D
QP
CLK
FF FF FF3
FFo

_CLR CIR CLR Q

CLR
-CLEAR
counter
Fig: Four bit Johnson

DSD-99
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counter is shown below.

The counting sequence of 4-bit Johnson
ClockQaQQ2 |Q:
00I

sequence of 4 bit Johnson Counter

Fig Counting
is shown in figure.
The timing diagram of 4 bit Johnson counter

fully
Th major disadvantage of the counter is that the
maximum available states are not
states.
utilized and only eight states out of the sixteen used

b)Parallel-In-Serial-Out (PISO):
Basic ldea D
A four-bit parallel in serial out shift register is shown below. The circuit uses flip
flops and NAND gates for entering data (i.e., writing) to
the register.
DO, DI, D2 and D3 are the parallel inputs, where DO is the most significant
bit and D3 is
is taken to LOW and the
the least significant bit. To write data in, the mode control line
as SHIFT
data is clocked in. The data can be shifted when the mode control line is HIGH
is active high. The register pertorms right shift operation on the application of
a clock*

pulse, as shown in the animation below.

DSD-100
 Block diagram DIGITAL SYSTEM DESIGN
Do
D
WRITE D D
SHIFT

D SET Q
CLK- D SET
Q D SET Q D SET Q
Output
CLR data
CLR Q

CLEAR.

cSwitch-tail ring counter:

Switch-tail ring counter is
a serial-in, serial-out
ring counter. shift register but it is called a Switch-tail
The logic diagram of a
4-bit Johnson counter using
The state diagram and sequence D flip-flips is shown below.
table of a ring counter are shown
below.

D Q
T

CLK

Fig: Switch-tail ring counter

0001
After clock pulse
0011
0
0000 2
0111 0

1000
6
1111

(1100
9
1110

DSD-101
 POPULAR PuBLIGATIONS

counter be 0000. After each

Let initialy all the flip-flops be reset i.e., the state of the
to Q4 and Q, to Qi. This
clock pulse, the level of Q, is shifted to Q, Q to Q, Q.
is shown below.
Sequence is reflected after eight clock pulses. The trimming diagram

JUUUUUtUL
L

Q4

Fig: Timing diagram of twisted ring counter

d) Lock-out phenomena in counters:

Some flip-flops (mainly JK flip-flop) in counters here a feature called Datalock-out,
which allows the flip-flip to load next state data on the edge of the clock, after which
allows input change are locked at of the flip-flop until the next state clock edge.

e)Irregular counter:
The state diagram is as follows:
Present State Next State
Q2
Q Qo Q2 Q1 Qo
0 0
0 0 1

0 0

Next state table:

Output Transitions Flip Flop Input
QN QN1 K
X

The transitions table for JK flip flop is

Ko Q

DSD-102
 DIGITALSYSTEMDESIGN

ex. for
J and K input taken from
J K, =1
Ihe

Master JJK fip-flop

-Q

-Q

Master Slave JK Flip-Flop

The Master Slave JK flip-flop in the above figure is designed using 2 S-R flip-flop.
Here a clock pulse is applied to both the flip-flop. When the clock goes
high then one or
the flip-flop ( one) is activated and the other is deactivated. Just the reverse situation
agcurs when the clock goes low. This can remove the Race condition in simple JK flip-

1op.

DSD-103
POPULAR PUBLICATIONS

LOGIC FAMILIES
Chapter at a Glance
many families'. Each
All these logic circuits are available in IC modules and are divided into
Tamily is classified by abbreviations that indicate the type of logic circuit
used. They are of
the following
Resistance- Transistor Logic (RTL),
Diode Transistor Logic (DTL),
Transistor-Transistor Logic (TTL),
Emitter Coupled Logic (ECL),
Integrated.-Injection Logic (IC),
Complementary metal oxide semiconductor (CMOS) etc.
MOS Families: In MOS category, the following families are included.
PMOS P channel MOSFETS
NMOS N channel MOSFETS
CMOS Complementary MOSFETS
PMOS, the oldest and slowest type is nowadays obsolete. NMOS is used in LSI field but
CMOS is used where low consumption is very much needed.
Characteristics of a Logic Family:
a) Logie nexibility: Logio flexibility of a digital IC is a measure of its utility in meting the
various system needs. The following factors are usualy included in the comparison of
logic flexibility of diferent digital ICs
b) Wired logic Capability: Connection of gate output terminals together are using them
directly to perform additional logic function without any extra hardware.
c)Availability of complement output: This avoids the need for additional inverters.
d) Capability to drive non-standard loads such as long lines, lamps etc.
e) Input/output facilities
Ab to drive other logic family circuits.
g) Ability to have many types of gates in the same family
Voltáge and current parameters:
Fan in: The fan in of a logic gate is defined as the number of inputs that the gate is designed
tohandle.
Fan out: The fan out is the maximum number of standard loads that the output of a gate can
drive without impairing normal operation. It is also called loading factor.
Propagation delay: The delay in between input and output signals is called propagation
delay.
Speed power product: The product of gate propagation delay and gate power dissipation is
called Speed power product.
Noise Immunity: The noise immunity of a logic circuit refers to circuits ability to tolerate
voltages on its inputs.
Noise Margin: The quantitative measure of noise immunity.

DSD-104
 DIGITALSYSIEM DESIGN

ogic Circuit: In Ssl and

Logic
ITL MSI devices, TTL
al TTL logic family uses NAND family members are wIa enext phase
o
Schottky
y transistors were circuit
incorporated to improve
at the
its
building
speed and 74
n
block.
series is
nroved 74S
improv
but propagation delay is being and
dissipation.
reduced by a factor 3 at the xpense of doubling power
Os Inverter: The basic NMOS N-channel
NA inverter shown
Shown in figure below contains two
MOSFE IS. Li 1s called the load MoSp
fom ON to OFF in response to ,. MOSFET and the witching MOSFET. Q will
swite
These two MOSFETs can be considered as resistors and
the circuit
as a potential divider.

Multiple Choice Type Questions

. The fastest logic family is WBUT 2007, 2010, 2012, 2014, 2016]
a) TTL b) ECL c) CMOS d) DTL
AasSwer: (b)

which
2W logic family has the better noise margin? WBUT 2011(EE), 2014]
a) ECL b) DTL c) MOS d) TTL
Aaswer: (c)

WBUT 2015
The fan out of a logic gate refers to number of
al input device that can be connected
b) input terminal
c) output terminal
d) circuit that can be connected at the output
Answer: (d)

4 The main advantage of Schottly TTL logic family is its least

WBUT 2016]
a) Power dissipation b) Propagation delay
c) Fan-in d) Noise immunity
Answer: (b)

5. CMOS circuits, which type of power dissipation

In
occurs due to switching of
transient current and charging and discharging
of load capacitance? [WBUT 2019]
b) Dynamic dissipation
Static dissipation
a)
d) None of these
c) Both (a) and (b)
Answer: (6)

following functions are performed by MSI category of IC

B.Which among the WBUT 2019]
technology? b) Microprocessor, A/D
a) Gates, Op-amps d) Memory, DSP
c) Filters
Answer: (c)

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 POPULAR PUBLICATIONS

7. In pull-down network, NMOS transistors are connected in parallel with the

provision of conducting path between output node and Ground yielding.
Output. WBUT 2019
a) 1 b) 0 c) both (a) and (b) d) none of these
Answer: (a)

8. CMOS logic dissipates .... power than TTL Iogic circuits. WBUT 2019
a) more b) less c) equal d) very high
Answer: (6)

S.In enhancement MOSFET, the magnitude of output due to an

current..WBUT
increase in the magnitude of gate potentials. 2019
a) increases b) remains constant
c) decreases d) none of these
Answer: (a)

10. Among DTL, TTL, ECE and CMOS logic families, the logic family having
minimum propagation delay is WBUT 2019]
a) DTL 5) TTL c) ECL d) CMOSS
Answer: (c)

Short Answer Type Questions

1. What is Schmitt Trigger? WBUT 20101
Answer:
In electronics, Schmitt trigger is a generic name
of threshold circuits with positive
feedback having a loop gain> 1. The circuit is named "trigger" because
the output retains
its value until the input changes sufficiently to trigger a
change: in the non-inverting
configuration, when the input is higher than a certain chosen threshold,
the output is high;
when the input is below a different (lower) chosen threshold, the
output is low; when the
input is between the two, the output retains its value. This
dual threshold action is
called hysteresis and implies that the Schmitt trigger possess
memory and can act as
a bistable circuit (latch). There is a close relation between
the two kinds of circuits that
actually are the same: a Schmitt trigger can be converted
into a latch and v.v., a latch can
be converted into a Schmitt trigger.
Schmitt trigger devices are typically used in open
loop configurations for noise immunity
and closed loop negative feedback
configurations to implement bistable regulators,
triangle/square wave generators, etc.

2. Design a 2-input NAND gate using CMOS inverter.

WBUT 2007

DSD-106
 Answer: DIGITAL SYSIEM DESIKGN

A y- (4B

3. Design a 2-input NAND

Answer: gate using CMOS
2 input NAND transistors. WBUT 2008]
gate using CMOS
transistor shown
below.

PMOS

Y-(ABY

4. What are the differences between static and

the CMOS SRAM.
dynamic RAM? Draw and explain
[WBUT 2019
Answer:
Refer to Question No. 6 (a) & (b) of Long Answer Type
Questions

Long Answer Type Questions

1.
Describe the operation of a 2-input TTL NAND gate using a neat diagram.
WBUT 2006, 2012]
OR,
Draw
the circuit diagram of a 2 input TTL NAND gate and explain how itworks.
WBUT 2018]

DSD-107
 POPULAR PUBLICATIONS

Answer:
The diagram of a standard TTL NAND gate is shown in Fig
YVc+5V

R2

inp uts

D output

Transistor Q1 has two emitters, thus it has two emitter-base (E- B) junctions that can be
used to turn Q ON.
This multiple emitter input transistor can have upto eight emitters for an eight input
NAND gate.
Transistors Qs and Q are in a totem-pole arrangement. In normal operation either Q or
Q4will be conducting depending on logic state of the output.

2. Discuss the totem pole output configuration of TTL logic family. WBUT 2009
OR,
Write short note on Totempole configuration of TTL. [WBUT 2011]

DSD-108
 DIGITAL SYSTEM DESIGN
AnSwer:
eeiit diagram of
ecire totem-Output
is shown below:

Ra
R
Totem
Pole

o Q OP

Rs

Fig: Totem Pole output

Description of the circuit
In circuit of two outputs TTL NAND
the
gate, transistor Q, sits above transistorQ3
Both of the transistors
are connected in totem pole fashion. Both
simultaneously but at any one of the cannot ON or OFF
turn will be contracting.
If Q, is ON, Q, must be ON because
drive of Q, comes from Q,. Vcs sat) = 0.3V So,
V 0.7 +0.3V = 1V.For Q, to be ON, in base emitter
junction must be forward
biased. When Q, is considered diode has
to be ON for Q to be ON simultaneously. So
the base

when ,
volume of 2 must be V = 1+.7 = 1.7V for it to be ON. Since
is ON. cannot be ON. So Q
V is only, 1 V
&Q, do not conduct simultaneously.
Advantages of totem Pole
I. The inclusion of diode and, keeps circuit Power dissipation low.
2.In the output high state, Q acts as an emitter, follows with low output impedance.
This action is referred as active pull up and it points very fast rise time waveforms at
TTL output.

Disadvantages
Transistor: transistor logic suffer from internaly generated current transients of
Totem-pole condition.

DSD-109
POPULARPUBLICATIONS

a number or gates cannot

pole output cannot be wire AND i.e. output of
otem tied together to obtain AND operation of those output.
De

totem pole? WBUT 201M0

3.a) What are the advantages and disadvantages of NMOS NAND gate.
D) With proper Circuit diagram, explain the operation of

Answer:
a)Refer to Question No. 2 (advantages & disadvantages) of Long Answer Type

Questions.

b) NMOS NAND Gate

An NMOS two-input NAND gate and its equivalent circuits for different possible
combinations of inputs in terms of resistance values of transistors in ON and OFF
position shown in the figure below.
+SV

+SV
Q
o Vout 100 ka 100 k

-O Vo=5v
AO
10n 10

BO- I k2

(a) Two input b) A LOW (c)A LOW

NMOS NAND gate BLOW BHIGH

DSD-110
 DIGITAL SYSTEM DESIGN
+5V
t5V

100 kO
100 kO
O Vu5V -o Vou0v
Ik
1k

100n k

(d) A HIGH (c) A HIGH

BLLOW BI HIGH
Fig: Circuit diagram and equivalent circuits
for
various inputs of the NMOS NAND gate

In the NMOS NAND gate shown, Qi is acting as a load resistor and Q and Qs as
switches controlled by input levels A and B,
respectively.
When both A and B are 0V, both Q and Qs are OFF. So, the equivalent circuit
(6) results with V =+5 V.
When A=0V and B = +5V, Qa is OFF and Q is ON. So, the equivalent circuit
(c) results with Voa = +5 V.
When A = +5V and B =0V, Q2 is ON and Qs is OFF. So, the equivalent circuit
(d) results with Vo +5V.
When A=+5V and B =+5V, both Q and Qs are ON. So, the equivalent circuit
(e) results with V = 0V.
Thus, the above circuit works as a positive logic two-input NAND gate.

4. a) What is the significance of the logic family with reference to

digital Integrated
WBUT 2015]
Circuits (ICs)?
Answer: another IC belonging to a different
Belonging to a certain family feeds the inputs of
techniques to ensure compatibility.
family, we must use established interface
logic families is very important
Understanding the features and capabilities of difterent
an optimum choice for his new digital design
for a logic designer who is our to make
from the available logic family
alternatives. A not-so-well thought our choice can easily
overkill the design with either inadequate or excessive capabilities.
underkill or
of circuit configurations or more appropriately various approaches
There are a variety such fundarnental
types of digital integrated circuits (ICs). Each
used to produce different
"The idea is that different
logic functions, when
family.
approach is called a logic same approach, or in other words belonging to
an IC with the
fabricated in the form of electrical characteristics. These characteristics
have identical
the same logic family, will
DSD-111
 POPULAR PUBLICATIONS

ncude supply voltage range, specd of response, power dissipation, input and output
OgIC levels, current sourcing and sinking capability, fan-our, noise margin, etc. In
other
words, the set of digital ICs belonging same logic family are
to the electrically
compatible with each other

Significance
A digital system in general comprises digital ICs performing different logic functions
and
choosing these 1Cs from the same logic family guarantees that different ICs are
compatible with respect to each other and that the system as a wholee performs the
intended logic function. In the case where the output of an 1.

6) What ies
the totem-pole output stage? What are its advantages? WBUT 2015
Answer:
Refer to Question No. 2 of Long Answer Type Questions.
5. With the help of block diagram explain the basic operations
of a semiconductor
emory How can we expand the word size and memory size of a memory chip?
Expand the word size of a 2048 x 32 memory using 256 x 4 memory chips.
WBUT 2019]
Answer:
1 " Part:
Semiconductor memory is the main memory element of a microcomputer-based system
and is used to store program and data. The main memory elements are nothing but
semiconductor devices that stores code and information permanently.
The semiconductor memory is directly accessible by the microprocessor. And the acces
time of the data present in the primary memory must be compatible with the operating
time of the microprocessor. Thus semiconductor deviues are preferred as primary
memory. ROM, PROM, EPROM, EEPROM, SRAM, DRAM are semiconductor
(primary) memories. The fabrication of semiconductor memories is done through CMOS
technoloEy.
The semiconductor memory offers high operating speed and has the ability to consume
low power. Also, these are fabricated as IC's thus requires less space inside the system.

DSD-112
 glock diagram of semiconductor DIGEIAL SEIEM DEHAA
memory:

Input Huffer

Memory
address Array
ine 2m
bits
inputs

Column Decoder

inputs

Functional Block Diagram

of Semiconductor Memory
The block diagram consists of a row and a column
array and IO buffer. These
address decoder along with memorY
buffers hold the data for a certain period time.
The total number of
of address lines i.e., n is divided into q and r and are separately
provided as input to row and
a column decoder. The output from these two decoders
iorms a matrix array having
size 2" x2" having 2" crossing points.
2Columns
Memory
cell

2rows
inputs

inputs

Memory Aray

DSD-113
 POPULAR PUBLICATIONS
memory cell holds the
referred to as memory cells. And each
nese croSsing points are the procesor senas
an address to the
to store one-bit of binary data. So, whenever
aolity accordingly select one line, which
memory IC then the row and column decoder
correspondingly selects a memory cell from the matrix. sent by the processor. Further,
selected by the address
n this way, the memory cells are according to the
the data can be read or written in a
particular selected memory cel
generated control signal.
memory semiconductor memory were fabricated of passive
ninalny, the cells of
diodes were also used. But with the
components like resistor and capacitor. After that
transistors took the places of diodes,
aavent of new technologies, bipolar and MOS
resistors and capacitors.
CMOS and HMOS technology that
And now-a-days the memory cells are made using
possesses high operational speed with low power consumption.

2nd
Part:
Expanding memory Size:
a memory with the desired number
Memory chips can be combined together to produce
m words each, the number of chips
of locations. To obtain the memory of capacity
required is an integer next to the value m/M.
These chips are to be connected in the following way:
. Connect the corresponding address lines of each chip
individually.
2. Connect the RD input of each chip together.
Similarly, connect the WR inputs.
3. Use a decoder of proper size and connect each of its
outputs to one of the CS
a3-line-to-6-line
terminal of memory chip. e. g. if eight chips are to be connected,
decoder is required to select one out of eight chips at any one time.

Expanding word Size:

The word size of a computer generally indicates the largest integer it can
process in a
necessarily
single instruction, and the size of a memory address, which is usually, but not
memory
the same as the integer size. The main indication of the word size is how much
the processor can address.
3rd
Part:
Obtain a 2048 x 32 memory using 256 x 4 memory ICs:
The number of chips required in 2048/256 =8.
At any time, only one of the 2048 location is to be accessed which will be in one
of the eight chips.
For selecting one out of 2048 locations, the number of address lines required is
1 (2=2048.
The lower order eight bits of the address A7- A0 will be same for each chip and
the higher order three bits of the address A10 A8 must select one out of the
eight chips.
For the purpose, a 3-line-to-eight-line decoder is required.

DSD-114
 DIGITAL SYSIEM DESRG

3-lune-to-8
ine

RI
Decoder M,
M, M
(MSB)

RW
D,-
Data bus (8)
D,-
6. Answer the following:
a) What are the differences WBUT 201n9
between static and dynamic RAM?
b) Draw and explain the CMOS
SRAM.
c) Draw and explain the CMOS DRAM.
Answer:
a)The differences between statie and Dynamic RAM::
Static RAM Dynamie RAM
I Such kind of RAM retains the stored 1 Loses its stored information
in a vey
information as long as the power supply is short time (a few milliserands) even
on. though the power supPPly is on
Circuit consists of multiple transistors 2 Circuit consists of
lesser number ef
generally 6) and two cross-connected (generally I) transistors and a capacitor.
inverters (latch).
Retaining of infomation depends on the 3 Depends on how long can the
capacitor
power supply. It holds information in flip retain its charge. Holds information as
flops. charge on a capacitor.
Costlier due to the requirement of multiple 4 Comparatively Cheaper.
transistors.
S Less packing density 5 High packing density
6 Faster 6 Moderate speeds but slower
than static
RAMs
Power consumption is high. 7 Consume less power
3.
Don't need refreshing of the circuitry. 8 Needs refreshing of the circuitry
9. Storage
capacity in a single memory chip is torage capacity in a single memory chip
is more.
less.
0 Has 10 Has a larger read and write eyce.
and write cycle.
a shorter read
I1 More user-friendly. 1 Less user-friendly.
12 12 Denoted as DRAM
Denoted as SRAM
DSD-115
POPULAR PUBLICATIONS

b)
WL

BL

BL
p-left p-right
access
left

Vr.m access
right
1, out
1,in JTL
r,out

n-left n-right

Static random access memory (SRAM) can retain its stored information as long as power
is supplied. This is in contrast to dynamic RAM (DRAM) where periodic refreshes are
necessary or non-volatile memory where no power needs to be supplied for data
retention, as for example flash memory. The term "random access" means that in an array
of SRAM cells each cell can be read or written in any order, no matter which cell was last
accessed.
The structure of a 6 transistor SRAM cell, storing one bit of information, can be seen in
Figure. The core of the cell is formed by two CMOS inverters, where the output potential
ofeach inverter is fed as input into the other This feedback loop stabilizes the
inverters to their respective state.
The access transistors and the word and bit lines, WL and BL, are used to read and write
from or to the cell. In standby 'mode the word line is low, turning the access transistors
off. In this state the inverters are in complementary state. When the p-channel MOSFET
of the left inverter is turned on, the potential K, is high and the p-channel MOSFET of
inverter two is turned off, V, ou is low.
To write information the data is imposed on the bit line and the inverse data on the
inverse bit line, BL. Then the access transistors are turned on by setting the word line to
high. As the driver of the bit lines is much stronger it can assert the inverter transistors.
As soon as the information is stored in the inverters, the access transistors can be turned
off and the information in the inverter is preserved.

DSD-116
 DIGITAL SYSTEM DESIGN
RAS ROW
CLOCKS
VBB
GENERATOR
CAS BEFORE RAS
ROW RAS -CAS
ADDRESSs
BUFFERS
ROW DECODER
REFRESH
COUNTERS

COLOUMN
ADDRESS I M BIT
LBUEFERS CELL ARRAY

ADDRESS
TRANSITION
DETECTOR READWRITE
AMPLIFIER OUTPUT
BUFFER
WE-
WRITE
CAS cONTROL INPUT
WE CAS
(CS) BUFFER
(CS)

ASYNCRONUS CIRCUIT

Block diagram of 1-Mbit

CMOS DRAM
1
Write short
notes on the following:
Propagation Delay
NTr-State gates in TTL WBUT 2007, 2013]
family
CMOS and its operation WBUT 2007, 2014]
TTL WBUT 2015, 2018
Noise margin WBUT 2016]
WBUT 2017

DSD-117
 POPULAR PUBLICATIONS

Answer:
a) Propagation Delay:

Logic

50%

Logic 0 (a) Input pulse

Logic

50%

Logic 0

(b) Output pulse

Propagation delay in an inverter
Fig:

is called propagation delay.

The delay in between input and output signals
A pulse through a gate takes a certain amount of time to
propagate from input to output.
This interval of time is known as the propagation delay of
the gate. It is the average
transition delay time ipds expressed by
PLH TPHL
2 1

where puH is the signal delay time when the output goes from a logic 0 to logic
a state

delay time when the output goes from a logic I to a logic 0 state
and is the signal
(Fig)

b) Tri-State gates in TTL family:

Tristate Logic
Normally there are two output states in a normal logic circuit namely Low and High but
in complex digital systems, a number of gate output may be required to be connected to a
common line, referred to as a bus which in may be remained to drive a number of gate
input when a number of gate inputs are connected to a bus, some difficulties are being
faced.
a) Totem-pole output cannot be connected together because of very large current drain
from the supply and subsequent heading of the ICs that may get damaged.
b) Open collector outputs can be connected together with a common collector resistor
that is connected externally. This causes the problem of loading and speed of
operation.
For overcoming above difficulties, special circuits have been developed in which there is
one more output state, referred to as third state. These circuits are known as TRI state or
three state logic.

DSD-118
 DIGITALSYSIEM DESIGN
In Tristate logic, the
result is
functions economically. otanot a Boolean
Boolean function
function but an ability to multiplex many
Tristate Inverter logic
The circuit agram
of a TSL is shown
below.
cc

Data Input
Control
Data output

Control
Q
Data Input
Fig: Logic Symbol of TSL
oY
Data output

Fig: Tristate Logic Inverter

The table of the above inverteris shown below.
Data Input Control
0
Data Output
High z
0
High-z

c) CMOS and its operation:

The CMOS logic family uses both P andN channel MOSFETs
realize several advantages over in the same circuit
the PMOS and NMOS families. The to
faster and consumes less power CMOS family is
than the other MOS families. These advantages
Somewhat by the increased complexity are offset
of the IC fabrication process and a lower
density. The CMOS can be operated packing
at higher voltages resulting in improved
immunity. It is widely used for general-purpose noise
logic circuitry.
The CMOS technology
has been used
to construct small, medium and large scale ICs for a wide variety
applications ranging from general-purpose logic to of
microprocessors. Because of its
extremely small power consumption, it is userul for applications
in watches and
calculators. The CMOS, however, cannot yet compete
with MOS in applications
requiring the utmost in LSI. The CMOS, however, cannot yet
compete with MOS in
applications requiring the utmost in LSI. The CMOS has very high input
resistance. Thus,
draws almost zero current from the driving gate and therefore, its fan-out is very high.
Output resistance is small (I k2) compared to that of NMOS (100 k). Hence, it is
bter than NMOS. The speed of CMOS decreases with increase in load. In CMOS, there

DSD-119
POPULARPUBLICATIONS

the Vn terminal and ground, because of the

IS always a very high resistance between

Hence, its power consumption is very low. The noise

MoSFET in the current path.
LOW and HIGH states and it is 30%% of Vp.
margin of CMOS is the same in both the
in
an increase in power supply voltage. So
margin increases with
nacating that noise an increase in Vp
V is preferred. However,
noisy environments, CMOS with large
its advantages at
resuns in the corresponding increase in The CMOS loses some of
P.
high frequencies. process is
the CMOS is also competitive with TTL. The CMOS fabrication
In MSI,
and it has greater packing density, thereby permitting more
Simpler that of the TTL uses only a
a given area and reducing the cost per function. The CMOS
Circuitry in
power needed even for low power TTL and is, thus, ideally suited for
Iraction of the
requiring battery power or battery backup power. The CMOS 1s, however,
applications
generally slower than TTL.

CMOS Inverter
circuits for different iumputs. It consists
Figure shows a CMOS inverter and its equivalent
Q2. The input is connected to the gates
of an NMOS transistor Qi and a PMOS transistor
both the devices. The positive supply
of both the devices and the output is at the drain of
transistor Q2 and the source of Q1 is
voltage is connected to the source of the PMOS
grounded.
and Q is OFF.
When =0V (LOW), Vs2 = -5 V and Vas=0V. So, Q2 is ON
in
Therefore, the switching circuit (b) results with Vu =5 V.
Q2 is OFF and Q is
When Vn = +5 V (HIGH), Vas =0V and Vos=+5V. So,
.
ON. Therefore, the switching circuit (c) results with Vu 0V.
DD
+YDD
+ VDD (5 V)
Vos2

G Va=OVo- -Vou5v
OV
Vin5Vo -OVou
VinO OV
S
Q
LG
D
(6)

(a) CMOS inverter ()

Fig: Circuit diagram and equivalent circuits
for various inputs of the CMOS inverter

DSD-120D
 DIGITAL SYSTEM DESIGN
the above circuit acts
as an inverter.
CNOS NAND Gate
e shows a CMOS two-input
nbinations. Here, NAND gate
and its equivalent
Q andQ are parallel-connected
are ies-connected NMOS transistors PMOS transi
ransistors and Qs an Q
When A=OV
and B =0V,
Va =Vss =
Q is OFF, Q is ON
and Q is OFF. -5V. Fas =Vs = 0V. So, Q is ON,
V.
Va+5 Thus, the switching circuit (o) with
When A=OV and
B=+5V,
Q is ON,
Qs is OFF, Q. V =-5V, V =0V, Fss =0V, Vos So
results with Va is OFF and O. is ON. Thus, the switching
=+5V. circut
When A=+5V and B=0V,V
Qi is OFF, Qs is ON, =0V, V =-5V, Vas =5V,Ves =0V. o
Q is ON and Q is OFF.
results with Thus, the switching circuit
V = +5V. (a
When A=+5V and B = +5V, Va Va
Qs is ON, Q is OFF
=
=0V, Vas =Vs =5V. So, Qi is OFF,
and Q4 is ON. Thus, the switching circuit (e) results win
o0V.
+Vo(5V) +VoD

-oV«

AO-

BO

(a) Two-input NAND gate

DSD-121
POPULAR PUBLICATIONS
+VoD
+Vpo
+Vp»

o V
-o Ve AO
-o V AO

BO--
BO BO

(¢)
(d)
(c)

B Q OFF 5 V
(b) OV 5V ON ON ON
OV ON OFF ON ON 5V
(c) 0V OFF 5V
OFF ON OFF
(d) 5V 5V
OV_ OFF OFF OFF ON 0V
(e 5V_
(0 Truth table
circuits for
Fig: Circuit diagram and equivalent
various inputs of the CMOS NAND gate
works as a two-input NAND gate. The truth table is shown in Fig. (1)
Thus. the circuit

CMOS NOR Gate

and its equivalent circuits for various input
Figure shows a CMOS two-input NOR gate
Q4 are connected in parallel and the
combinations. Here, the NMOS transistors Qs and
PMOS transistors QI and Q in series.
The operation of the CMOS NOR gate
can be explained as follows:
Vas =Vese = 0V. So, Q and Q
When A =0V and B=0V, Vas =Vas2 =-5 V,
results with
are ON and Qs and Q4 are OFF. Thus, the equivalent çircuit (b)
V.
ou+5
When A=0V and B= +5V, Vas=-5V, Vas = 0v, Vas
0V, Vass = 5 V. So,
=
Q and Q4 are ON, and Q2 and Qs are OFF. Thus, the equivalent circuit (c) results
V.
with =0 =
When A=+5V and B 0V, Ka =0V, Vas = -5V, Va = 5 V, Vas =0V. Sa
Q and Q are ON and Q and Q, are OFF. Thus, the equivalent circuit (d) esults
with 0V.

DSD-122
 When A=
+5V and DIGITAL SYSTEM DESIGN
are OF
OFF and B=+5V,
Qs and Vn
Qi are ON. GSN0V,
ou0V. VEs, =
Thus, Vs =5V. So, Q, and Q
hus, the equivalent
+Voo circuit (e) results with
(5V)

+VpD

Q AO

BO-

BO-

DL
OVo0Ov

(a) Two-input NOR

gate
(6)
+VDD
*VDD
+VDD

AO AOH
Q AO -~~-* Q

BO+ BoT
BO -
-OVouOV OV 0V
-oVou5

C) (d) (C)

DSD-123
POPULAR PUBLICATIONS

OV OV ON ON
OFF 0V
OV SV ON OFF ON
OFF ON OFF ON V
(d SV V
SV OFF OFF ON ON9
n Troh tsbe
Fig Circuit diagram and equivalent circuits for
various inputs of the CMOS NOR gate

The above analysis shows that the circuit works as a two-input NOR gate. The truth table
is shown in Fig. ().

d) TTL:
In SSI and MSI devices, TTL family members are widely used.
Original TTL logic family uses NAND circuit at the building block. In the next phase
Schotky transistors were incorporated to improve its speed and 74 series is improved 74
series but propagation delay is being reduced by a factor 3 at the expense of doubling
power dissipation.
After that delay power product is improved over 74 and 74S series and the series converts
into 74LS series. Preferably Advanced Low power Schotky series is denoted by 74 ALS.
74ALS series is actually a derivative of 74LS series whose design is used to minimize
power distribution. Since propagation delay is reduced here. This series has best delay
power product of any logic family. Power consumption is also reduced become its
resistance values are increased and current is reduced here. Speed of the device also
increases before the inclusion of additional active elements such as emitter followes.
Finally improved processing techniques permit fabrication of smaller devices.

Totem Pole Output: Refer to Question No. 2 of Long Answer Type Questions
e) Noise margin:
The noise margin of a logic circuit refers to circuits ability to tolerate voltages on its
inputs.
High state noise margin,
VNHVodmin) - V»dmin)
Low State noise margin,
VNL= Vu(max) - Vu(max)

DSD-124
 DIGITALSYSTEM DESIGN
PROGRAMMABLE
LOGICDEVICES
Chapter at a Glance
A Programmable
implemented. logic device
Basically it
different Ways. a
is a general
general purpo
contains a collection
PLD can dns
purpose chip by which logic circuits can be
of logic
programmable switches. thought to logic elements that can be customizea
be a black box tta
that contains and

Logic gates

Inputs
and
(Logicvaniables)
Outputs
(Logic

Programmable functions)
Switches

Programmable logic array:

PLA is
Programmable Logic Design. PLA consists the first developed commercially availabie
to a set of OR gates. of a collection of AND gates which are being
As depicted in figure fed
buffers into a circuit block, the PLA's inputs Y1, Y2,Yn pass through
called an AND plane. a set of

y yn

Input buffer
and
inverter

yn

AND Plane OR Plane

Programmable array logic: In PLA both AND and OR planes are programmable
which has
some problem in fabricating these devices. 1his drawback is being overcome in a new device
in which only the AND plane is programmabie but the OR plane is fixed as Programmable
array logic (PAL) device.

DSD-125
 OPULAR PUBLICATIONS
guestions
LMultiple Cholce Type
WBUT 2008, 2017]
1.
Full tom of FPGA is Field Programmable Gated Array
b)
a) Full Programmable Gated Array
d) Field
Peripherai Gated Array
c) Full Peripheral Gated Array
Answer: (b)
WBUT 2015
2. A PLA can be used memory
b) as a dynamic combinational circuit
a) as a microprocessor d) to realize a
c) to realize a sequential circuit
Answer: (b)

LLong Answer Type guestions

WUT 2009, 2013]
1.What are the types of PLD?
Answer: Progrs amable Logic
Design.
developed commercially available
PLA is the first OR gates. As
collection of AND gates which are being fed to a set of
PLA consists of a
pass through a set of buffers
into a
PLA's inputs Y1, Y2, .Y
depicted in figure the product terms
an AND plane or AND array which produces a set of
circuit block, called as inputs to OR plane
which produces
serve
P. Pa..
Outputs f,
, ......
P. These product
fCommercially
terms
available PLAs come in larger
and 8 outputs.
sizes. Typical

parameters are 6 inputs, 32 product terms

Block diagram

Input buffer
and
rtcr

AND Plane
e OR Plane

DSD-126
 DICTAL SYSTEM DESIC
Can a ROM be used to realize
3code converter using Q ROM aBoolean
Boolean function? Realise a BCD to excess
ANSer WBUT 2005
onal logic Circuit implementation
functions in the canonical aton
using ROM is expressed in minterms of
sum of product from
bes the implemeTiation of om. The following rcuit diagram
a Boolean functions.
-iy+++Y.R =zy+yF =z j+y+

14
-35
Lame
Decder

F
Fig Implementation of Boolean
function using ROM
2.What are RAM and ROM? What
EEROM?
is the basic difference between EPROM
and
AaSwer: WBUT 2010]
RAM: The simple view of
RAM is that it is made up of registers
that are made
number of flip-flops in a "memory register" up of flip-
fops (or memory elements). The
he size of the memory word. determines
ROM: ROM essentially
is a memory (or storage) device in which
a fixed set of binary
iformation is stored. Once a pattern
is established for a ROM, it
when power
is turned off and turned on again i.e. this is a remains fixed even
oncept of an ROM is extremely simple, user nonvolatile memory. The
supplies address and ROM
ouput of the word prewritten provides data
at the address.
MOMs are
internally implemented using diode, bipolar transistors
mput and of MOSFETs between
output lines.
Difference between
EPROM and EEROM
major advantage of E PROM over EPROM 1S the ability to electrically
rogram individual words in the memory aray. erase and
Anotheradvantage is that a complete E PROM can be in 10 ms
or an EPROM (in circuit) 30 minutes
in external. An E PROM can also be programmed
quires only a 10 ms programming pulse for each data more rapidly, it
an EPROM. word as compared with 50 ms
for

DSD-127
 POPULAR PUBLICATIONS
ROM?[WBUT 2013
BCD to Excess-3 using
4. a) Design a code converter circuit
for
Answer: converter using ROM:
Logic Diagram of BCD to Excess-3 code

B 4 to
Decoder

Di Do
D

Di Do

0
0 0

i
0

b) Design a circuit which find the square of a three-bit number using ROM.
WBUT 2013]
Answer:
/P

0 0

0
0
0

DSD-128
 DIGITAL SYSTEM DESIGN

O/P
B Bs
Bs Bs Bs
Decimal

0
0

1
0
0 16
25
36

A A

8x4 ROM

Bo

5. Implement the following functions using 3x4*2 PLA;

F(4,B,C)= 2m(4,5,7)and F,(4, B,C) -2m(3.5,7) WBUT 2012]
Answer:
K-maps
AB AB
00 01 11 10 00 01 11 10

=AB+AC =AC+BC

PLA program table

Variable Function
A B C
Product term
0
AB
AC
BC
TIC

DSD-129
 POPULARPUBLICATIONS

D
accepts 3-bit number and
6. Design a' combinational circuit using ROM that input number. WBUT 2014]
generate the output binary number equal to square of
Answer:
Bo
ABC Bs B4 B3
B B
0 0 o -2m(1,3,5,7)=Cc
000
0 0 B = 0
001

010 0 0 B m(2,6)
011 0
1
0 B,-m(3,3)
100 0 1 0 0 0 B-24,5,.7)
101 0
B, m(6,7)
110 010
111 1 1
0 0 0

B2

8x4 3

ROM

7.Implement the following functions using PROM: WBUT 2015]

F1(4, B, C) =2(0,2) and F2(4, B, C)=2m(1,4,7)
Answer:
F(4.B,C)-2m(0.2)
For 3 input, 2 output we need (2' x2) PROM i.e., (8x2) PROM.

DSD-130
 DiGITAL SYSTEM DESIGN
Ao

D
D
Da
A
3:8
Decoder

8.Explain the operation of PROM and EPROM.

Answer: WBUT 20177
PROM:
When ordered, PROM units contain all
0's (or all 1's) in every bit of the stored words.
Once it is programmed no change is possible.
For small quantities, it is more economical
to use a second type of ROM called a programmable
read-only memory or PROM. When
ordered, PROM units contain
all0's (or all 1's) in every bit of the stored words. The links
in the PROM are broken by application
of current pulses through the output terminals. A
broken link defines one binary state and an unbroken
link represents the other state. This
allows the user to program the unit in his own
laboratory to achieve the desired
relationship between input addresses and stored words. Special units called
PROM
programmers are available commercially to facilitate this procedure. In any case, all
procedures for programming ROMs are hardware procedures even though the word
programming is used.

EPROM:
An EPROM, or erasable programmable read only memory, is a type of memory
chip that
retains its data when its power supply is switched off. In other words, it is non-
volatile. It is an array of floating-gate nsistors individually programmed by an
electronic device that supplies higher voltages than those normally used in digital
circuits, Once programmed, an EPROM can be erased by exposing it to strong ultraviolet
are easily recognizable by the
ght from a mercury-vapor light source. EPROMS
through which the silicon chip is
transparent
quartz window in the top of the package, erasing.
S1ble, and which permits
exposure to UV light during

DSD-131
 POPULAR PUBLICATIONS

9. Write short notes on the following:

a) PLD WBUT 2008, 2011 (EE), 2016
WBUT 2008, 2016]
b) EEPROM WBUT 2015]
c) PAL
Answer:
a) PLD:
Many PLDs include one or more of the following end part
of their architectures Flip
these
Latches, input registers and output registers. The operating characteristics of
lops, to the other devices on the chip.
devices can be made programmable as are the connecting
It makes two logic designed a great deal of flexibility
counter and other sequential logic
Programmable Logic Sequencer.
Circuit designing. This type of PLDs is sometime called
Programmable Logic Array
Normally there are three types of PLDs available namely (i)
(11) Programmable Array Logic (PAL) and ii)
Field Programmable Gate Array
PLA)
FPGA).
chip area and speed of chip is being
The drawback of PLD is that it consumes valuable
limited.
custom or semi custom chips are being
So to overcome the above difficulties the use of
applications and are called
evolved. Such chips are intended in use in specific
Application Specific Integrated Circuit (ASICs).
manufacturing a custom chip takes a
The disadvantage of custom design approach that
is
considerable amount of time.
are so many integrated circuit chips and each type of chip is
In the market there
types of PLDs are widely used in
appropriate for specific types of applications. Various
like PLAs and PALs are used for
many type of applications. Simple PLDs
low cost and high speed. CPLDs are
implementation of small logic circuits. SPLDs offer
having more number of gates. For larger
used for implementation of larger circuits
gate array, standard cell and custom chip
circuits FPGAs can also be used. The
appropriate.
technologies are used in cases where PLDs are not

b) EEPROM:
in contents of this memory unit is
EEPROMs are electrically erasable PROM. Change
less than' erasing of an EROM. Erasing and
made in milliseconds, which is much
EPROM. As the name suggests
programming of E* PROM is much easier as compared to
in the memories, data can be written any number
of times i.e. they are reprogrammable.
erasing the contents of
Reprogramming of ROM is possible only in MOS technology for
the memory.
A major advantage offered by
EEPROMs over EPROMs is the ability to electrically
memory array.
erase and reprogram individual words in the
instant 10 ms about 30
Another advantage is that a complete EEPROM can be erased
light. An EEPROM can also be
minutes for an EPROM in external of ultraviolet
each data word
programmed more rapidly it required only 10 ms programming pulse for
EPROM.
as compared with 50 ms for an

DSD-132
 DIGITALSYSTEM DESIGN
Programmable Array
Logic:
PLA both
Ahricating
AND and OR
these devices. planes are programmable
This drawback which has son
anly the AND
on plane is programmable is being overcome P uhich
logic(PAL)ddevice. Since but the OR plane is fixedinaas ammable array
mparatively it has Programma
less expensive only one prograr grammable part, it easier to fabricate and
is
Programmabie than PLAs.
which each
read only memories discussed
and every input combination earlier are suitable for applications
n
other applications, generate
where all input combinations the output function. There are severd
a type of programmable need not be programmable. The FAL
logic device. The I
aP PRON
he PAL has AND gate architecture of PAL differ slightly from that or
with the sight
difference, that in theand OR gate arrays similar to that of the PROM, but
whereas inputs to the OR PAL the inputs to AND gates are all
gates are hard-wired. programmaDIe,
programmed to generate Thus each and every AND gate can oe
ant desired product
Each OR gate is
hard-wired to a number of the variables and or their complements.
inputs. This limits each of AND gate outputs, equal to the number or
output function to as many
product terms as is the number inputs.

DSD-133
POPULAR PUBLICATIONS

&D/A CONVERTER
A/D
Chapter at a Glance
output code
conversion: An analog to digital converter produces a digital
Analog & Digital ADC is shown
an analog input votage after a certain amount of time. The block of
from
below
Conarol Start Command
OpAmp
-Clock

End of Conversion

DA Register
Converter

Types of A/D Converter: There are several types of ADC namely

1. Successive approximation ADC.
2. Flash type ADC
Up/Down Digital-ramp ADC.
Dual slope ADC.
5. Digital Ramp ADC.
Dual Slope ADC: The advantage of Dual-slope ADC is in relatively low cost but it has one
of the slowest in conversion times. It is also in low sensitivity to noise.
.Flash type ADC: It is the highest speed ADC but it is much more circuiting then other type.
Successive Approximation ADC: This type of ADC has more complex circuiting but it hasa
much shorter conversion time. It has a fixed value of conversion time.
Digital to Analog convertor: Basically, D/A conversion is the process of taking a value
represented in digital code and converting it to a voltage or constant which is proportional to
the digital value.
The analog output voltage Vo of.an N bit straight binary D/A converter is related to the digital
input by the equatic
V K{2bN-1 +2*by-2t.2b, +2b1 +bo]
K =proportionality factor.
b, =1 ifn- th bit of digital input is I
= 0 ifn-th bit of digital
input is 0
Types of D/A Converter
1. Weighted resistor D/A Converter
2. R-2R ladder D/A Converter.
3. The R/2nR DAC-
4. 6-bit binary weighted DAC

DSD-134
 Sample and DIGITAL SYSTEM DESIGN
Hold circuit:
the voltage of a continuously A sample
and hold circuit is
specitied minimum
period of
varying analog
signa
an an onstant samples
gnal and holds its value constant level
time. at a for a

Multiple Cholce
Type Questions
1.The total conversion
time need for
Successive Approximation type
a) (Nx1) clock time BUT 20071
period
b) (2 x1) clock time period
c)2-1)clocktimeperiod
Answer: (a) d) None of these

2 The number of comparisons

carried out in a 4-bit flash
type ADCis
a) 16
b) 15 WBUT 2011(EE)
Answer: (b) c)4 d) none of these
3.The fastest ADC is
a) dual slope type WBUT 2012]
c) counter type b) successive approximation type
Answer: (5) d) none of these

4. DIA conversion will use an input

a)
hexadecimal number as WBUT 2016
c) a binary number b) en octa! number
d) analog wave
Answer: (c)
5. The resolution of 8-bit A/D converter is
a) 0.62 b) 0.38% WBUT 2017]
c) 0.39% d) 1.25%
Answer: (b)

LLong Answer Type Questions

1. a) What are the output voltages caused by logic 1 in each bit
position in an 8-bit
adder if the input level for 0 level is 0 volt and for level 1 is 10 volt?
b) Compare
the maximum conversion period of an 8-bit Digital ramp ADC and 8-bit
Successive approximation ADC, if both utilize 1 MHz clock frequency. [WBUT
2010]
Answer:

1
H DSD-135
ut
 POPULAR PUBLICATIONs

differently. Typically the inputs are

The circuit above performs D to A conversion a little
resistance for both logic 0 and logic 1.
driven by CMOS gates, which have low but equal
really do provide +5 and 0 volts for
AISo, if we use the same logic levels, CMOS gates
their logic levels.
network. It has several
ne input circuit is a remarkable design, known as an R-2R ladder
advantages over the basic summer circuit we saw first:
in the entire circuit. This means
.Only two resistance values are used anywhere needed, in a resistance ratio of
that only two values of precision resistance are
especially expensive.
2:1. This requirement is easy to meet, and not
2. The input resistance seen by each digital
input is the same as for every other
digital source gate is 3R. With a
input. The actual impedance seen by each
very standard values of 10k
CMOS gate resistance of 200 ohms, we can use the
and 20k for our resistors.
numbers. Thus, if we use binary
3. The circuit is indefinitely extensible for binary
the ladder network for
inputs instead of BCD, we can simply double the length of
16-bit number (0 to 65535).
an 8-bit number (0 to 255) or double it again for a
We only need to add two resistors for each additional binary
input.
4. The circuit lends itself to a non-inverting circuit
configuration. Therefore we
along the way. However, an
need not be concerned about intermediate inverters
appropriate.
inverting version can easily be configured if that is
is extended, the output will remain
One detail about this circuit: Even if the input ladder
will simply allow the output
within the same output voltage limits. Additional input bits
resolution. This is equivalent to adding
to be subdivided into smaller increments for finer
value for each bit), but
inputs with ever-larger resistance values (doubling the resistance
extended ladder.
still using the same two resistance values in the
is actually quite simple. Current flowing
The basic theory of the R-2R ladder network
the far end. The effective
through any input resistor (2R) encounters two possible paths at equally
resistances of both paths are the same (also 2R), so the incoming current splits
lower orders of magnitude
along both paths. The half-current that flows back towards
voltage. The halfthat
does.not reach the op amp, and therefore has no effect on the output
output.
takes the path towards the op anmp along the ladder can affect the
its current toward the op
The most significant bit (marked "8" in the figure) sends half of
amp, so that half of the input current flows through that final 2R
resistance and generates
"8" only) will be one-third of the
a voltage drop across it. This voltage drop (from bit
controlled
logic 1 voltage level, or 5/3 = 1.667 volts. This is amplified by the op amp, as
shown,
by the feedback and input resistors connected to the "-" input. For the components
3, tne
this gain will be 3 (see the page on non-inverting amplifiers). With a gain of
amplifier output voltage for the "8" input will be 5/3 x 3 = 5 volts.
going
The current from the "4" input will split in half in the same way. Then, the half
curTent
towards the op amp will encounter the junction from the "8" input. Again, this
a
"sees" two equal-resistance paths of 2R each, so it will split in half again. Thus, only
1/8 or c
quarter of the current from the "4" will reach the op amp. Similarly, only
current from the "2" input will reach the op amp and be counted. This continues
backwards for as many inputs as there are on the R-2R ladder structure.
DSD-136
 DIGITAL SYSTEM DESIGN
aximum
The max Output voltage
Thus, an 8-bitfrom this
circuit
Circuit will be one step
56x
(255/256 10 volts). This ladder
is fine for can
Can produ
produce
step of the least significant bit
output voltages up to 9.961 votts
es a 0-9 volt output many
many applications.
amplifier with a from a BCD input, you you have an application tna
If you
Sing gain of 1.6 (8/5). can casily scale the utput upwards

For 8 bitrramp ADC, maximum number

of countis, =2" = 256
n=2|
desimum conversion time,
T.== =256x10s = 256jus
For8tbit successive approximation ADC,
maximum number of count is
T 8x10 = 84s
t cancanbe noted that the conversion
speed of successivé approximation AlDC 1S mucCn
faster than the staircase ramp type.

2 a) Draw a neat diagram for a weighted DAC

operation. resistor type explain its
nd
WBUT 2011(EE)]
Answer:
Principle
Let assume an N bit binary input to a resistor network which produces a current 1
us
coresponding to logic I at the most significant bit, 1/2 corresponding to logic 1 at next
lower bit, 1/2 for logic I at the next lower bit and so on. Total current thus produced will
be proportional to digital input. This curent can be converted into a corresponding
voltage by using an Op-amp, which will be proportional to the digital input.
The circuit of DAC is shown in Fig. This circuit is referred as a weighted-resistor D/A

converter since resistance values are weighted with binary weights.

R
M
LSB

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thrown to 1
In the circuit, digital inputs (1 or 0) operate the switches. A switch is position
or O for a digital input corresponding to that bit being or 0 respectively. The voltage
I

I
and V(0) if it is
applied to a resistor is V(1) of the switch connected to it is in position
in position 0. The current, L is given by, 1, = Iy- +lN-2 +IN-3t..a tl *lo
where
= Vo
IN- ;Iy-2 N-IR
R
where
V, = V(1) ifb, =1|
=V(0) ifb, = 0
For straight binary input, V(a) = 0; V(1) =-Va and output voltage,

V--Vab,*2t
with

V
with V(1) and V(0) as thé voltages applied to the resistor network for land 0 respectively,
output voltage,

N2w-+2**Vn-at.2'V,
oN-IR +2°V%

b) Describe the operation of successive approximation type ADC.

WBUT 2011(EE), 2012, 2014, 2015, 20181
How many clock pulses are required is worst case for each conversion cycle of an
8-bit SAR type ADC? WBUT 2011(EE), 2012, 2014, 2015]
Define quantizing error for an ADC. WBUT 2012, 2015, 2018]
Answer:
1" Part:
The successive-approximation (SA) converter is one of the most widely used types of
Analog to Digital converter. It has a shorter conversion time than the other ADCs, with
the exception of the flash type. It also has a fixed conversion time which is not dependent
on the value of the analog input.
Figure below shows a block diagram of a 4-bit successive-approximation type ADC. It
consists of a DAC, an output register, a comparator, and control circuitry or logic. The
basic operation is as follows:
The bits of the DAC are enabled one at a time, starting with the MSB. As each bit is
enabled, the comparator produces an output that indicates whether the analog input
voltage is greater or less than the output of the DAC VM. If the D/A output is greater than
the analog input, the comparator output is LOW, causing the bit in the control register to
reset. If the D/A output is greater than the analog input, the comparator output is HIGH,
and the bit is retained in the control register.

DSD-138
 DIGITAL SYSTEM DESIGN
The systemn enables the
MSB
bits of the DAC
have been first, then the nextssignificant bit, and on. After
each bit takes one tried, the so all the
Ca,
clock cycle; the conversion
will
w be N clock cycles. eso, cycle
so, the total conversic
That is, for total
is complete. The processing o
conversion time for an jV-bit SA-type AD
t SAC = (N x 1) clock
Analog
cycles.
Va
input
Conrol CLK
logic
Comparator START
EOC

Output
register

LSB
Binary output
DAC

VAx

Fig: The successive -approximation

type ADC
The conversion
time will be the same
control logic has to regardless of the value of Ka. This is
process each bit to see because the
The method is best explained whether al is needed or not.
by an example. Let us
ranges from OV to 15V assume that the output of the DAC
as its binary input
producing OV, and O001 producing ranges from 0000 to 1111, with 0000
1V, and so on. Suppose that
input voltage. the unknown analog
VA is 10.3V.
On the first clock pulse, the output
converted register is loaded with 1000, which is
by the DAC to 8 V. The voltage
the analog input (10.3 V); so,
comparator determines that 8 V is less than
the control logic retains that bit. On the
the control circuitry causes the next clock pulse,
output register to be loaded with 1100.
DAC is now 12 V, which the comparator The output of the
determines as greater than the analog
Therefore, the comparator output goes LOW. input.
The control logic clears that bit; so,
output goes back to 1000. On the next clock pulse, the
the control circuitry causes the output
register to be loaded with 1010. The output of the DAC
is now 10 V, which the
comparator determines as less than the analog input. Thus, on the next clock
pulse, the
control logic causes the output register to be loaded with 101 1. The
output of the DAC is
now 11 V, which the comparator determines as greater than the
analog input; so, the
control logic clears that bit. Now the output of the ADC is 1010, which is the neares
integer value to the input (10.3 V). At this point, al of the register bits have been
processed, the conversion is complete and the control logic activates its HOC output to
signal that the digital equivalent of Ka is now in the output register.

The advantages of the Successive approximation type ADC are

1)
tis faster compared to other counter type ADC.
4 The conversion time is fixed and short.

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The constant conversion time allows the output to be synchronized so that it can be rread
at known intervals.
For the digital ramp converter maximum conversion time is (2"- 1)x(1 clock cyele)
255 xI 4s 255us
For an 8 bit successive approximation type conversion, the conversion timé is alwWays 8
clock periods i.e. 8 x I us = 8 gus.
2nd
Part:
Quantizing error
The smallest digital step is due to the LSB and it can be made smaller only by increasing
the number of its in detail representation. The error is called quantizing error.

3. a) Describe the R-2R ladder type D/A converter. WBUT 2012, 2014, 2018]
b) What do you mean by resolution? WBUT 2012]
Answer:
a)
Refer to Question No. 6(a) of Long Amswer Type Questions.
b) Resolution is defined as the smallest quantity that an instrument can measure without
ambiguity. The resolution of a D/A can be defined as the smallest change in the analog
output voltage corresponding to a change of one bit in the digital input. It actually
depends on the number of bits in the digital input signals.

4. Explain the sequence of operatiorn of converslon of an analogue signal to its

digital equivalent when the expected digital output is 1010. WBUT 20161
Answer:
In successive approximation type ADC. Suppose the unknown analog voltage is 10.3V.
.On that clock pulse, output register is loaded with low, which is converted by DAC to
8V. The voltage comparator determines that 8V is less than analog input (10.3V). So
constant logic retains that bit. The control logic clears through the output gives back to
1000. On the next clock pulse output register to be loaded with 1010. The output of DAC
is now 10V, which comparator determines as less than analog input. Thus on the next
clock pulse constant logic comes the-output register to be loaded with 1011. The output
of DAC is now 11V, which the comparator determines as greater than analog input. So
control logic clears that bit. The output of ADC is 1010 which is the nearest the nearest
integer value to the input 10.3V.

5. Draw aneat diagram of an R-2R ladder type DAC. WBUT 20171

Answer: Refer to Question No. 6(a) of Long Answer type Questions.

6. Write short notes on the following:

a) R-2R ladder type DIA converter
WBUT 2009, 2016]
b) Successive approximation ADC
WBUT 2009, 2017
c) Flash type ADC WBUT 2009]
d) Dual slope A/D converter
WBUT 2013)

DSD-140
 DIGITAL SYSTEM DESIGN
Answer:
aR-2R ladder type D/A
n R- 2R ladder D/A converter:
An
converter is shown
digitallyoverter
applied through
controlled switches.in Fig. The inputs to the resistor network are

w W
2R
T

2R T R

The output voltage,

-
4b, +2b,
For an N bit D/A converter,
output voltage can be determined and is
given by
Vo
=(2by- +2bN-2*t...+2b, +2'b, +2°bo)
where,
R, =3R and Ve = 2*v
Because of the widespread in the resistance
values for N, the weighted resistor D/A
converter is not suitable.

b) Successive
approximation ADC:
Refer to Question No. 2(6) of Long Answer Type Questions.

c)Flash type ADC:

Flash type ADC is the highest speed ADC but it is much more circuitry than other
type.
Flash type ADC consists of 2" I comparator, 2" register and encoder logic.
-

The voltage corresponding to Full Scale is V form which reference voltages VR., VR..

.are generated using resistor returns. The voltage V, is compared simultaneously with
reference voltage by using comparators. A 7-bit output is obtained from the comparator
which is stored in latches. This 7-bit digital signal is converted to a 3-bit output by using
a decoder circuit.
The principle of parallel comparator A/D conversion is the simplest in concept and
fastest. The main disadvantages of this A/D conversion are rapid increase in the number
of comparators with the, number of bits [(2-1) comparators are required for an N bit
circuit.
converter] and the corresponding complication of decoder

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Ana log
pu

Digital
output

R
C

D
H

R2 F

d) Dual-Slope AD Converter:
The block diagram of a dual-slope A/D
Converter is shown in Fig. It has four major
blocks viz.
1) An Integrator
2) a Comparator
3) a binary Counter
4) a Switch driver

DSD-142
 DIGITALSYSTEM DESIGN

V,
0 Si

N bit

C
Binary Counter
Clock pulses

BN
Ba
<-Nbit bin ary output
Dual slope
AD Converter
The conversion process
begins at t = 0
with switch S in position 0 thereof connecting
analog voltage Va to the input of the integrator. the
The integrator output,

This results in High Vc,

thus enabling AND gate and
terminal of the counter which was clock pulses reach the clock
initially clear, counter counts from
111.Il when 2"-1 clock pulses are applied. At the next 00.....00 to
cleared and becomes 1. This controls the clock pulse 2*", counter is
state Si which moves to position 1 at Ti
connecting-Vr to the input of integrator.-The output of integrator thereby
positive direction. The counter continues now starts to move in
to count until Vo< 0. As soon as Vo goes
positive at T2, Vc goes low disabling AND gate.
The counter will stop counting in
absence of clock pulses. Waveforms are shówn in Fig.

AVo

.a-T)

Waveforms of dualslope converter

of clock pulses.
The time T, =2N Tc, where Te= time period
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POPULAR PUBLICATIONS

When switch S, is in position 1, output voltage,

V, T+0-T)
T
Vo =0 att = T2

:(T-T)=T2Te
R R
Let the count recorded in the counter be n at T2

(T-T)= nle2lc
Which gives,

n N
VR
So output of counter is proportional to analog voltage V.

DSD-144
 DIGITAL SYSTEM DESIGN
VLSIDESIGN
FLOW
Chapter at a Glance
Design Hierarchy:
The use
module into sub-modules of hierarchy,
complexity of the sub-modulesand then or "divide
repeating this and conquer", involves dividing
The hierarchy oper a
is stopped is at an appreciably peration on the sub-modules until the
and physical at the level compt
layouts 1.e., where where modules nprehensible level of detail.
hierarc describing the modules are defir
efined in terms of simulation
moodels
hierarchies the same structure. are standard cells. There may
between the function, Generally
allows consistent structure it is aag good practice to be two
maintain
checks between and physical aspects identical
to the very top
levels. Frequently description domains from of a design becauSe
or functional
hierarchy, it if the physical the lowest level of the
will be found hierarchy is designed hierarcny
other hand structural first without a structura
hierarchies may that the resulting hierarchy
constraints. be defined that do is cumbersome.
VLSI Design not map well to the On
Flow: The design pnysiea
and tested against process starts with a given set of requirements.
is developed
has to be improved. the requirements. Initial design
If such improvement When requirements
of requirements are not met, the design
and its impact analysis is either not possible or too costly, then
D. Gajski) shown must be considered. the revision
in Fig. below illustrates The Y-chart (first
activities on three introduced by
different axes (domains) a design flow for most logic chips,
which resemble the using design
letter Y.
Structural
Domain Behavioral
Processor
Domain
Register
Algorithm
ALU Finite
Leaf Cell
Moduleate
Descriptidachine
ransisto Boolea
Equaticn

Mask

Cell
Placemen
Module
lacement
Chip
Floor plan

Geometrical Layout Domain

Typical VLSI design flow in three domains (Y-chart representation)
he Y-chart consists of three major domains, namely:
Behavioural domain,
Structural domain,
Geometrical layout domain.
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 PoPULAR PUBLICATIONSs

fow starts from the algorithm that describes the behaviour of the target chip The
The design
coresponding architecture of the processor is first defined. It is mapped onto the chip wurface
byfloor-planning The next design evolution in the behavioural domain defines finite wate
machines (FSMs) which are siructurally implemented with functional modules wch a
registers and arithmetic logic units (ALUs). These modules are then geometrically piaced onto
the chip surface using CAD tools for automatic module placement followed by touling, with a
ROal of minimizing interconnect areas and signal delays. The third evolution starts with a
behavioural module description. Individual modules are then implemented with leaf cells. At
this stage the chip is described in terms of logic gates (leaf cells), which can be placed and
interconnected by using a cell placement & routing program. The last evolution invoves
detailed Boolean description of leaf cells followed by a transistor level implementation of leaf
cells and mask generation. In standard-cell based design, leaf cells are already pre-designed
and stored in a library for logic design use.

Multiple Choice Type guestions_

1. VHDL is acronym of MODEL QUESTION
a) verilog hardware description language
b) very high speed insulated chip hardwáre description language
c) very high speed integrated circuit hardware description language
d) none of these
Answer: (c)

2. Synthesis translate from MODEL QUESTION

)physical description behavioral description
b) structural to physical description
c) behavioral description to structural description
d) structural description to behavioral description
Answer: (c)

3. Min-cut algorithm is a MODEL QUESTION

a) placement algorithm b) routing algorithm
c) testing algorithm d) floor planning algorithm
Answer: (a)

4. Which domain is
not inctluded in three domaine of Y chart [MODEL QUESTION
a) system specification b) structural
geomotrical layout
c) d) behavioral
Answer: (a)

5.For a symmetric CMOs Inverter (, +Vm) is equal to MODEL QUESTION

a) b) 2 c) p d) Vom-O

Answer: (e)

DSD-146
 Hierarchical
decomposition DiLAL SYSIEM DESIGN
of a iargo
a) modularity systein in VLSI desin
Answer: (a) b) regularity sign is calted
MODEL QUESTION
c) locality d) al! of thone
7. VLSI stands for
a) Very Large
c) Very Long
Source Integration
Scale Integration (MODEL OUESTION
Answer: (b) b) Very Large Scale
d)
integration
Very Low Scale Integration
8 VLSI design flow is a
a) cycle process
c) sequential [MODEL QUESTION
and cyclic process b) para!lel process
Answer: (a)
d) none of these

Short Answer Type

1. Write
Questions
the VHDLVerilog
Answer: code for a 3input AND gate.
module and WBUT 2019
gate_3in( input_a, input_b,
input_c,
output_y)

I/NPUTS:
input input_a;
input input_b;
input input_c;

IOUTPUT:
Output output_y;

IDeclaration of 3 input AND Gate

assign output_y = (input_a) &
(input_b) & (input_c);
endmodule

2.
Write difference
Answer:
beveen CPLD and FPGA. MODEL QUESTION
omparison between CPLD& FPGA
CPLD FPGA
Architecture Large, wide fan-in blocks of AND Amay of small logie blocks
OR logic. surrounded by VO blocks.
Bus Interfaces. Logic consolidation
Application Complex State Machines. Board integration.
Fast Memory Interface. Replace obsoiete devices
Wide Decoders Simple State Machines.
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CPLI D FPGA
PAL device integration. Compiex controlicrs interfaces
Fast pin to pin pertormance. Very high density.
timing. Pienty of /Os and Flip flops.
Key Attributesredictabie Generally low power devices
Easy to use.
SRAM devices are reprogrammabie.
Gate Capacity 300 to 6000 gates. 800 to above S00000 gates.
PAL-like. Application dependant.
Design Timingixed,
Design tmng Very fast Very high shift frequencies.
pinto pin pertormance

3. Define Moor's Law. Explain VLSI Design flow. IMODEL QUESTION

Answer:
From the initial siage of electronic system design, miniaturization has been a costant
challenge to increase the speed and complexity in the microelectronics industry. Scaling
down of device dimensions to a quasi-nanometre level allows designers to 1ncrease
complexity with a drastic reduction of volune and power consumption per iunction,
whilst tremendously increasing the speed of the systems integrated on a chip.
The iaw is named cfter Intel co-founder Gordon E. Moore, who described the trend in his
1965 paper. The paper noted that the number of components in integrated circuits had
doubled every year from the invention of the integrated circuits in 1958 until 1965 and
predicted the trend would continue for at least ten years'. His prediction has proven to be
uncannily accurate, in part because the law is now used in the semiconductor industry to
guide long term planning and to set targets for research and development.
The capabilities of many digital electronic devices are strongly linked to Moore's law
processing speed, memory capacity, sensors and even the number and size of pixels in
digital cameras. All of these are improving at roughly exponential rates as well. This
exponential improvement has dramatically enhanced the impact of digital electronics in
nearly every segment of the world economy. Moore's law describes a driving force of
technological and social change in the late 20th and early 21st centuries.
On 13 April 2005, Gordon Moore stated in an interview that the law cannot be sustainad
indefinitely: "It can't continue forever. The nature of exponentials is thau you push them
out and eventually disaster happens". He also noted that transistors would eventually
reaeh the limits of miniaturization at atomic levels. In terms of size [of transistors] vou
can see that we're approaching the size of atoms which is a fundaniental barrier, but itt
be two or three generations before we get that far-but that's as far out as we've ever been
able to see. We have another 10 to 20 years before we reach a fundamental limit. By then
they'ii be able to make bigger chips and have transistor budgets in the billions.
In 2003, Intel predicted the end would come between 2013 and 2018 with 16 nanometer
manufacturing processes and 5 nanometer gates, due to quantum tunneling, although
others suggested chips could just get bigger, or become layered. In 2008 it was noted that
for the last 30 years it has been predicted that Moore's law would last at least another
decade.

DSD-148
 DIGITALSYSTEM DESIGN

processor Transistor Counts 1971-2011& Moore's Law

2.000,000,000 Cen

.000,000,000 **

w
100.000.000o

10.000.000
ue show innelsoe
every
U doubing

1,000,00001

100,000

10,000

2,300
CA 1S
e KE

1971
1980 1990 2000 2011

Date of introduction
4. What is an FPGA? How is it different from CPLD? What
are it advantages?
[MODEL QUESTION]
Answer:
"
Part:
A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by a. customer or a designer after. manufacturing- hence "field-
programmable". The FPGA configuration is generally specified using a hardware
description language (HDL), similar to that used for an application-specific integrated
circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as
they were for ASICs, but this is increasingly rare.)

2 d Part: Refer to Question No. 2 of Short Answer Type Questions.

3d Part:
The cost of designing traditional standard cell ASlICs is increasing every year. In addition
to the non-recuring engineering (NRE) and mask costs, development costs are increasing
due to design complexity. Issues such as power, signal integrity, clock tree synthesis, and
manufacturing defects can add significant risk and time-to-market delays. FPGAs offer a
viable and competiti ve option to traditional standard cell ASIC development by reducing
time-to-market delays.
the risk of re-spins, high NRE costs, and
Programmable logic has progressed from being used as glue logic to today's FPGAS.
implemented on a single device. The number
where complete system designs can of
e

increased dramaucally to compete with capabilities that have

gates and features has
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 POPULARPUBLIGATIONS
we have higher
ASIC devices. In today's FPGA,
traditionally only been offered through interconnects
intellectual property (IP) integration, and high-speed l/o
density devices, in digital
these elements have allowed FPGAs to play a central role
Technology. All of
systems implementations.

LLong Answer Type Questions

the concepts of Regularity,
1.a) What do you mean by design hierarchy? Discuss
Modularity and Locality in VLSIl design. [MODEL QUESTION
b) Explain the VLSI design flow with the help of Y-chart.
Answer:
a) Some of the classical techniques for reducing
the complexity of lc design are
described in the following sections.
Hierarchy
involves dividing a module into sub
The use of hierarchy, or "divide and conquer",
until the complexity of the
modules and then repeating this operation on the sub-modules
sub-modules is at an appreciably comprehensible level of detail.
At a system level, the use of hierarchy allows one to specify single
designer projects, at
Significant
which level the schedule is proportional o'the number of available personnel.
benefits accrue where modules be re-used within a system design. In this case we
design in
create a single design for thís nodule but we use several instances of this
different parts of the system.
The hierarchy is stopped at the level where modules are defined in terms of
simulation
models and physical layouts i.e., where the modules are standard cells. There may be two
"disjoint" hierarchies describing the same structure. Generally it is a good practice to
maintain identical hierarchies between the function, structure and physical aspects of a
design because this allows consistent checks between description domains from the
lowest level of the hierarchy to the very top levels. Frequently if the physical hierarchy is
designed first without a structural or functional hierarchy, it will be found that the
resulting hierarchy is cumbersome. On the other hand structural hierarchies may be
defined that do not map well to the physical constraints
Usually after a few iterations the physical and structural hieràrchies may be reconciled.
Many times the issue is moot because an automatic layout system is able to take the
structural hierarchy and create a layout that meets both timing and area requirements.

Regularity
Hierarchy involves dividing a system into a set of sub modules, However hierarchy alone
does not necessarily solve the complexity problem.
With regularity as a guide, the designer attempts to divide the hierarchy into a set of
similar building blocks. The use of iteration to form arrays of identical cells is an
illustration of the use of regularity in the IC design. However extended
use may be made
of regular structures to simplify the design process. Regularity can exist at all levels of
the design hierarchy. At the circuit level, uniformly sized transistors
might be used rather
than manually optimizing of each device. At the logic
module level, identical gale
DSD-150
 DIGITALSYSIEMDESIGZ
structures might
be employed.
a number ot identical
,
At higher levels. one might construct
may be judged processor architectures ua
correct by structures. By using regularity
a design may also construction. Methods
for formally providing the coe ness of
be aided by regularity.
Reguiary controls the manner
replacing a complex in which sub-modules
system are chosen. The strategy is o av
attempts to divide design with a complexity
the hierarchy of sub-modules. The desiger
into a set of similar blocks.
Modularity
Sub modules must
have
formed, the interactions well defined functions and iterfaces. Where modules are well
with other modules
the intertace is defined are easy to characterize. In the case of 1ayout,
by the ports
locations and using of the sub modules which must be at
specified conductors. speciies
with other. modules If
may be well characterized.
modules are "well-formed", the interaction
behavioural, structural In an IC correspond a well detiea
and physical interface that indicatesthis
size, and Signal type the position, name, 1ayr
of
electrical characteristics. externa! interconnections, along with the logic function and
The concept of modularity
enables the parallelization of the design
the use of generic modules in process. It also allows
various designs. The well defined functionality
interface allow plug and and signal
play design. By defining wel1-characterized
module in the system, we effectively interfaces for each
ensure that the internals of the each module
unimportant to the exterior modules. become
Internal details remain at the local level.
level, the correct decision regarding At a system
modularity allows one to break-up a
confidence that when the parts are combined, system with the
the whole system will function as specified.
Locality
By defining well characterized interfaces for
a module, we are effectively stating that
other irternals of the moduie are unimportant to any exterior the
interface. In this way we are
performing a form of "information hiding" that reduces the
apparent complexity of the
module. In software, this is paralleled by the reduction of global variables
to a minimum
A side effect of this complexity hiding is that a
sub-module may be changed at any time
without disturbing the overall design provided that the changed sub-module
continues to
support the same interface.
The concept of locality ensures that connecuons are mostly between
neighbouring
modules, avoiding long distance connecions as much as possible to reduce the delay
and
complexity of routing. Time critical operaions should be performed locally, without the
ieed to access distant modules or signals.
For locality to work, we must impose restrictions on the use of a sub-module. In the case
of layout, we must avoid making unwanted connections to elements in the sub-module
and we must avoid design rule violations caused by proximity of external elemens to
internal elements.

b) Refer to Chapter at a Glance.

DSD-151
POPULAR PUBLIGATIONS
[MODEL QUESTION]
2. What is full custom design?
circuits, or
Answer:
designs some or all of the logic cells,
engineer approach of
In a fullcustom ASIC an means the designer abandons the
This sense to
layout specifically for one ASIC. all or part of that design. It makes
pre-characterized cells for be
using pretested and existing cell libraries available that can
there are no suitable fast
take this approach only if be because existing cell libraries are not
might may
used for the entire design. This enough or consume to0 much pOwer. One
small that there
enough, or the logic cells are not technology is new or so specialized
the ASIC
need to use full-custom design if ASIC is so specialized that some circuits must
the
are no existing cell libraries or because most expensive to manutacture and to
Full-custom 1Cs are the an IC-not
be custom designed. time it takes just to make
time (the
design. The manufacturing lead IC.
design time) is typically eight weeks for a full-custom ASICs, for
including
we are more interested in are semicustom
IC family that
(possibly all) of the mask layers
are
The members of the and some
predesigned
which all of the logic cells are our lives as designers
predesigned cells from a cell library makes
customized. Using
two types of semicustom ASICs: standard-cell-based
much, much easier. There are
ASIC's and gate-array-based ASICs.
QUESTION
up approach in VLSI design? [MODEL
3. What is top down and
bottom
Answer:
Top-down and bottom-up design:
English Specification

Executable System throughput

Behaviour design line
program

Function units,
Sequential Register
clock cycles
machines transfer
Cost
Function
Logic Literals gate
Logic
Gages depth, power

Translators
Circuit Nanoseconds

Rectangles Layout Microns

DSD-152
 QUESTION
2015
Group-A
1.Answer any ten (Multple Choiee
questions Type Questlons)
The number of bit required to
a) 8 represent an
eight digit decimal
b) 16 number in BCD Is
) 24 d) 32
All Boolean expression can
a) NAND gate only be inmplemented
with
c) Combination of b) NOR gate only
all basic gates
d) Any of these
i) The minimum
number of NAND
A+AB+ABC is gates requlred to
Implement the Boolean
function
a) three
b) two
c) one d) zero
) Which of the following flip-flop
is used as a latch?
a) J-K flip-op
b) S-R flip-flop
c)D lip-flop
d) T ip-lcp
v)A full adder can
be made out of
a) two half
adder
c) two half adder and a OR gate b) two half adder
and an inverter
d) two half adder
and a AND gate
vi) An
asynchronous counter is also known
as
a) ripple counter
b) multiple clock counter
c) decade counter
d) modulus counter
vi) A MOD 13 counter
must have
a) 13 flip-flop b) 3 flip-flop c) 4 lip-lop d) 2 flip-flop
VIt) Which of the following is an invalid state of
an 8241 BCD counter?
a) 0010 b) 0101 c
1000
d) 1100

) The fan out of a logic gate

refers to number of
a) input device that can be connected
b) input terminal
c) output terminal

d) circuit that can be connected at the output

POPULAR PUBLICATIONS
is of
RAM ispreferred over dynamic RAM when the requirement
xStatic b) large storage
capacity
a) slow speed of operation consumption
d) lower power
c) lower access timne

xi) A PLA can be used memory

b) as a dynamic
a) cs a microprocessor combinational circuit
d) to realize a
c) to realize a sequential circuit

Group-B
Questions)
(Short Answer Type implement it using only
for a 3-input majority function and hence
2. Obtain the logic expression
NAND gates Question No. 6.
COMBINATIONAL CIRcUITS, Short Answer Type
See Topic:

2:1 multiplexer.
3. Design 4:1 multiplexer using Type Question No. 13.
COMBINATIONAL CIRCUITS, Short Answer
See Topic:

B\A+C)
4.Prove that(A+B)(4 +©)(B+C)=(4+
Question No. 5.
Topie: BOOLEAN ALGEBRA, Short Answer Type
See

subtract (101 101), from (1011101),.

method
6. Using 2's complement
Question No. 2.
NUMBER SYSTEMS, Short Answer Type
See Topie:

6. ConvertJ-K fip-flop to D fip-flop. No. 8.

SEQUENTLAL CIRCUTT, Short Answer Type Question
See Topie:

Group-C
(Long Answer Type Questions)
following function using K-map:
7. a) Simplify the
15)+2d(3.13)
f2m(0.5,8, 10, 11,14, Question No. 3(a).
See lopic:
BOOLEAN ALGEBRA, Long Answer Type

minterms and maxterms?

b}What are the difference between
ALGEBRA, Short Answer Type Question No. 4.
See Topie: BOOLEAN

Absorption law
c) Prove Distributive law and
ALGEBRA, Long Answer Type Question No. 6.
See Topie: BOOLEAN
DSD-154
 8. a)What is
the difference DIGITAL SYSTEM DESIGN
h Show how a full-adder between full-adder
circuit. can be and full-subtractor?
converted to
Design a full a full-subtractor
actor witn
subtractor with the addition of an inverter
using
See Topic: cOMBINATIONAL two half-subtractors
CIRCUITS, and one extra gate, if necess
9.a) Describe Long Answer
Type
pe Question
No. 9(a),
the operation (b)& (c).
See Topic: 4A/D of successive
& D/A CONVERTER, approximation
type ADG
Long Answer
b) Explain
Type e
Question No. 2(b}(1"
ne sequence Part).
when the expected of operation
digital output of conversion
of an analogue signal
See Topic: AD
& DIA cONVERTER, is 1010. to its digital equvai nt
Long Answer Type
Question No. 4.
c Define quantizing error
See Topic:
for an ADC.
AD & D/A CONVERTER,
Long Answer
Type Question No.
10. a) What 2(b) (3* Part).
is the significance
See Topic: LOGIC of the logic family
FAMILIES, Long with reference to
digital Integrated Circuits
Answer Type Question (cs)?
No. 5(a).
b) What is
the totem-pole output
See Topic: stage? What are its advantages?
LOGIC FAMILIES,
Long Answer Type
Question No. 5(b).
c) Implement the following
functions using PROM:
FI(4, B, C)-2m(0,2)
And
F2(4, B,C)=2m(14,7)
See Topic:
PROGRAMMABLE LOGIC DEVICES,
Long Answer Type Question No.
7.
11.Write short notes on any
three of the following:
a) Lock-out phenomena in counters
b) Iregular counter
c) PAL
d) Encoder
e) CMOS and its operation
a) See Topic:
SEQUENTIAL CIRCUITS, Long Answer Type QuestionNo. 17(d).
D See Topic: SEQUENTIAL CIRCUITS, Long
Answer Type Question No. 17(e).
) See Topic: PROGRAMMABLE LOGIC
DEVICES, Long Answer Type Question
4) See
No. 9(c
Topic: COMBINATIONAL CIRCUITS, Long Answer Type Question No.
15(d).
See Topic: LOGIC FAMILIES, Long Answer Type Question No. 7(c).

DSD-155
POPULAR PUBLICATIONS

QUESTION 2016

Group-A
(Multiple Choice Type Questions)
1. Choose the correct alternatives for any ten of the following
)A ring counter is d) none of these
b) synchronous counter
) up-down counter
a) shift register

counter is
i) Number of flip-flop required for a mod 15 ripple d) 6
a) 3 b) 4 c)5

i) In AND-OR relation is equivalent to

c) K-map
d) none of these
a) SOP b) POS

AB216 is
iv) The equivalent octal number of hexadecimal number
c)5268 d) 2562
a) 6272 b) 5262

is HIGH if
v) The output of a two input NAND gate
a) both inputs are LOW
is LOW
b) one of the input is HIGH and the other one
c) both inputs are HIGH
d) none of these

vi) A 4 bit serial adder requires

a) a half adder b) 4 half adder c) 4 full adder d) a full adder

vi) All Boolean expressions can be implemented with

a) AND gates only b) NOR gates only

c) Combination of AND and OR gates d)

none of these

vii) DIA conversion will use an input as

a) hexadecimal number b) an octal number

c) a binary number d) analog wave

I) Which of the foltowing devioces alows only one output to be activated at one time?
a) Multiplxer b) Demultiplker / decoder
c) Encoder d) none of these

DSD-156
x)The maina
advantage
of DIGITAL SYSTEM DESIGN
a) Power dissipation Schottly TTLlogic
family
c) Fan-in isitits least
b) Propagation delay
xi)The fastest logic d) Noise immunity
is
a) TTL
b) ECL
Asynchronous c) IL
Xn) d) RTL
counter
differs from
a) the mod number a synchronous counter
in
c) the type of fiip-flop
used b) the method of clocking
d) the number of states in
a sequence

Group-B
2. Explain race
(Short Answer
around condition Type Questions)
of J-K fip-fiop.
See Topic: SEQUENTIAL Show how this condition can
CIRCUITS, be avoided.
Short Answer Type Question
No. 5.
3.What is a BCD
code? What are its advantages
See Topic: NUMBER SYSTEMS, and disadvantages?
Short Answer Type Question
No. 3.
4. Design a 5:32 decoder using 3 :8 decoder and
See Topic:
2:4 decoder.
COMBINATIONAL CIRCUIT, Long
Answer Type Question No. 1.

5.Write short notes on weighted and non-weighted

codes
See Topie: NUMBER SYSTEMS,
Short Answer Type Question No. 4.

6. Briefly describe Johnson counter with proper diagram.

See Topic: SEQUENTIAL CIRCUITS, Short Answer Type Question No. 9.

Group-C
(Long Answer Type Questions)
7. What
is ripple counter? Design a presentable 4-Bit up asynchronous counter using J-K F-F. A
binary ripple counter is required to count to (16389)1o How many F-Fa are required? f the clock
requency is 8.192 MHz, what is the frequency at the output of the MSB?
Type Question No. 11.
See Topic: SEQUENTIAL CIRCUITS, Long Answer

counter with JK flip-flop.

Design MOD 10 asynchronous Up/Down
.a) combinational circuit and sequential circuit.
9) Write down the difference between
Question No. 12.
SEQUENTIAL CIRCUTTS, Long Answer Type
See Topic:
Short Answer Type
Question No. I.
9 See Topic: SEQUENTIAL CIRCUITS,

DSD-157
 POPULAR PUBLICATIONS

9 a) Using k-map method, simpify the following function:

F(,x, J,)-2(1.3,4.5,6,7,9,12,13).
b) What do you mean by SOP and PO$?
c) What do you mean by Maxterm and Minterm?
d) Stete DeMorgan's theorem.
See Topie: B0OLEAN ALGEBRA, Long Answer Type Question No. 7(a), (b). (o) & (d).

10. a) Design the folcwing function using suitable MtX: h:

F(4,B,C,D)= 2(1,3,4,11,12,13,14,15).
b) Design a 16: 1 MUX using 4: 1 MUX.
Design substractor using two half substractor.
fuli
Sce Topic: COMBINATIONAL CIRCUITs, Long Answer Type Question No. 10(a), (b) & (c).

11. Write short notes on any three of the following

a) Even parity generator and checker
b) R-2R ladder type D/A converter
c) EEPROM
} PLD
e) TTL

)Sce Topic: COMBINATIONAL CIRCUITS, Long Answer Type Question No. 15(a).
b) Sce Topie: AD & D/A CONVERTER, Long Answer Type Question No. 6(b).
c) See Topic: PROGRAM LOGIC DEVICES, Long Answer Type Question No. 9(b).
d) See Topic: PROGRAM LOGIC DEVICES, Long Answer Type Question No. 9(a).
) See Topic: LOGIC FAMILIES, Long Answer Type Question No. 7(d).

QUESTION 2017
Group-A
(Multiple Choice Type Questions)
1. Choose the correct alternatives for any ten of the following:

Gray code of 1011 (binary) =

a) 0101 b) 1101 c) 1110 d) none of these

i) An example of reflected code is

a) BCD b) ASCII c) GRAY d) Hamming code

DSD-158
 minimun
i) The minimum number DICITAL SYSTEM DESIGN
of NAND
a) 3 gates required
b) 4 to design
design one X-OR gate is
c)5
*
M (212), d) 6
=(25)10 where x is
a) 2
base (tve integer) thenthe
value of x
b) 3 is

c)4 d) 5
Ful form of FPGA is
a)Full Programmable
Gated Array
c)Full Peripheral
Gated Array b) Field Programmable Gated Array
d) Field Peripheral Gated
Array
The resolution of 8-bit A/D converter
a) 0.62 is
b) 0.38%
c)0.39% d) 1.25%
viOne bit even parity
detector code
a) any even number fails to detect
of error
c) both (a) and (b) b) any odd number
of error
d) none of these
v What is the word
size of 16x 8 ROM?
a) 16
b) 8
c) 128
d) none of these
(A+B+A'B)C =

a) 1
b) 0
c)C d) C"

FIF that makes output equals to input after clock

is
a) J-K FIF b) D F/F
c)TFIF d) none of these
) 8421 is a
a) weighted code b) non-weighted
code
c) complementary code d) none of these

) The characteristic equation of T fip-flop is given by

a) Q=TO+TO b)O =T0+TQ

Q=TO d) none of these

DSD-159
POPULARPUBLICATIONS

Group-B
Questions)
(Short Answer Type obtain minimal POs
following Boolean function and
2. Using the
K-map method, simplity the
expression: Y=.(0,2,6,7)+2(3,8,10,11,15)
Question No. 6.
Sce Topic: BOOLEAN
ALGEBRA, Short Answer Type

two 2:1 multiplexers.

3. Implement a full adder circuit by using Type Question
No. 14.
COMBINATIONAL CIRCUITS, Short Answer
See Topic:

number of NAND gates.

4.Design a full adder using minimum Type Question No.
15.
COMBINATIONAL CIRCUITS, Short Answer
See Topic:

filip-flop and other required logic

gates.
5. RealizeaD flip-flop by using a T 10.
CIRCUITS, Short Answer Type Question No.
See Topie: SEQUENTIAL
an OR gate.
substructure
full by using two half substructures and
6. Construct a Type Question No. 3.
See Topie:
COMBINATIONAL CIRCUITS, Long Answer

Group-C
(Long Answer Type Questions)
for the given input signals.
Draw the timing diagram of a D flip-flop & D-latch
7. a)

CLK

INPUT
CIRCUITS, Long Answer Type Question No. 13.
See Topie: SEQUENTIAL

of an R-2R ladder type DAC.

b) Draw a neat diagram
See Topic: AD & D/A
CONVERTER, Long Answer Type Question No. 5.

DSD-160
 DIGITALSYSTEM DESIGN
8. Design a
a) De sequential circuit
ftops for the design. that implements
the following state diagram. Using all D-type flip-
1/0

C
O/0
/
O/0

l/1
O/0
1/0

b) Draw and explain

the BCD 0/1
a)See Topic: SEQUENTIAL adder using 7483.
CIRCUITS, Long
b) See Topic: COMBINATIONAL Answer Type Question No.
14.
CIRCUITS, Long
Answer Type Question No. 11.
9. a)Explain the operation
of PROM and EPROM.
b) Design a 5 Mod synchronous
a See Topic: PROGRAMMABLEbinary counter using J-K flip-flop and necessary logic gates.
b) See Topic: SEQUENTIAL
LoGIC DEVICES, Long Answer
Type Question No. 8.
CIRCUITS, Long Answer
Type Question No. 15.
10.
a) What are the differences
between the Decoder and Demultiplexer?
b) Form a multiplexer
tree to give 8:1 MUX from
two 4:1 MUX and 2:1 MUX.
c)Implement a full-adder circuit
using 3 to 8 decoders with
necessary logic gates. ll active high outputs
and other
a) See Topic: COMBINATIONAL
CIRCUITS, Long Answer
b) See Topic: COMBINATIONAL Type Question No. 4(a).
CIRCUITS, Long Answer
e See Topic: COMBINATIONAL CIRCUITS, Type Question No. 12.
Short Answer Type Question
No. 12.
11. Write short notes on any three of the following:
a) Shift registers
b) Johnson counter
c) Successive Approximation Type A/D Converter
d) Noise margin
e) Master-slave JK flip-flop
a) See Topic: COMBINATIONAL CIRCUITS, Long Answer
Type Question No. 15(e).
b) See Topic:
SEQUENTIAL CIRCUITS, Long Answer Type
Question No. 17(a).
)See Topic: A/D & D/A CONVERTER, Long
Answer Type Question No. 6(e).
) See Topic: LOGIC FAMILIES,
Long Answer Type Question No. 7(¢).
) See Topic: SEQUENTIAL
CIRCUITS, Long Answer Type Question
No. 17(0.

DSD-161
POFULAR PUBLICATIONS

gUESTION 2018

Group-A
(Multiple Choice Type
Questions)
any ten of the following
question
1. C 1o0se the correct alternatives for
9 (10)1o is equivalent to
c)AA d) AF
a) FD ) DF

converter?
Which one of the following can be used as parallel to serial
)
b) Digital Counter
a) Decoder
d) Demutiplexer
c) Muitiplexer

i) Which code is used in K-Map?

d) Excess-3
b) Binary c) Gray
a) BCD

in such a way that the

two identical flip-flops connected
iv) Amaster slave configuration consists of
one of the following is corect?
output of the master is input to the slave. Which
triggered
a) Master is level triggered and siave is edge
is level triggered
b) Master is edge triggered and slave
is negative edge triggered
c)Master is positive edge triggered and slave
d) Master is negative edge triggered
and slave is positive edge triggered

counter is 0110. What will it be after 37 clock pulse?

v) The initial state of MOD-16 down
b) 0101 c)O001 d) 0110
a) Indeterminate

to produce X= 1
is
vi) Ir the figure shown the input condition, needed

a) A 1,B=1, C 1
b) A 1, B 1, C=0
= d)A 0, B =
) A= 1,B =0, C 0 1, C 1

DSD-162
 vil) How many
nlification? gates would DIGITALSYSTEM DESIGN
XY +
X (X
be required
a) 1 +Z) +Y (X to implement
+Z) wing Boolean expression beforee
b) 2
vil) BCD coding of 12 c) 4
is d) 5
a) 00001010
c) 00010010
b) 00001100
d)
How many flip-flops None of these
required to
a) 3 design MOD
b) 4 10 counter?
c)5
xf the output of a logic gate d) 6
a) A NAND or is '1' when all
a NOR its inputs are
at logic 0', the gates
c) An OR or a is either
NAND b) An AND or an EX-
NOR
d) An EX- OR or
an EX- NOR
xFor a binary half
output (=A
adder having two
+ B) points A and B
and (= carry) are the correct set of logical
a) S AB + A'B expression of tne
&C = A'B
c)S AB+ AB&C =AB b) S A'B+ AB'&C= AB
d) S AB+
Xi) Which
A'B' &C = AB
of the following is
reflected code?
a) 8421
b) Excess-3
c) Gray
d) ASCII

Group- B
2. (9 Convert
(Short Answer Type Questions)
the following decimal numbers into
binary.
(a) 72.45
(6) 2048.0625
9 Convert the following binary numbers
into decimalt
(a)
10001101
(6) 10111.1011
(c)0.1101
oee
Topic: NUMBER
SYSTEMS, Short Answer Type Question No. 5.

Simpliífy the
Boolean expression Y= AB + ABD+ ABCD + BC using K-map
method.
opic: BO0LEAN ALGEBRA, Short Answer Type Question No. 7.

DSD-163
POPULAR PUBLICATIONS
flip-flop. What is
race around condition
triggered and level triggered
4. What do you mean by edge
in J-K fip-flop? How it can be overcome? 11.
Short Answer Type Question No.
CIRCUITS,
" Part: See Topic: SEQUENTIAL Answer Type Question No. S
SEQUENTIAL CIRCUITS, Short
2 Part: See Topic:
explain how it works.
circuit diagram of a 2 input TTL NAND gate and
5. Draw the 1.
FAMILIES, Long Answer Type Question No.
See Topie: LOGIC
gates.
6. Design a 4 to 16 decoder using 3
to 8 decoder and logic
No. 4.
COMBINATIONAL CIRCUITS, Short Answer Type Question
See Topic:

converter
7. Explain R-2R Ladder type D to A
No. 3(a).
See Topic: A/D & D/A CONVERTER, Long
Answer Type Question
Group-C
(Long Answer Type Questions)
it possible to replace the
correction circuit of this
BCD adder. Is
8. Draw and explain the circuit of
adder by comparator (digital)? Explain. No. 13.
See Topic: COMBINATIONAL CIRCUITS,
Long Answer Type Question

and Flip Flops?

9. (a)What are the differencés between Latches
(b) Design MOD-3 synchronous
counter using JK FLIP FLOP
FLOP.
counter using negative edge triggered JK FLIP
() Design MOD-6 Ripple
Long Answer Type Question No. 10(a), (b) & (c).
See Topie: SEQUENTIAL CIRCUITS,

10. (a) What is Cary Look Ahead Adder?

Decoder.
(b) Design a Full adder circuit using 3:8
() Simplify the Boolean
function F=A'C + A'B+ AB'C BC
CIRCUITS, Short Answer Type Question No. 9.
a) See Topic: COMBINATIONAL
b) See Topie: COMBINATIONAL CIRCUITS, Short
Answer Type Question No. 12.
e) See Topie: BOOLEAN ALGEBRA, Short
Answer Type Question No. 8.

11. (a) Design a counter with the following binary sequence (0, 1, 3, 7, 6, 4) and repeat using
T-Flip Flop
(b) Describe the operation of successive approximation type ADC.
(c) Define Quantizing error of ADC.
a) See Topie SEQUENTIAL CIRCUITS, Long Answer Type Question No. 16.
b) See Topie: A/D & D/A CONVERTER, Long Answer Type Question No. 2(b) (1" Part).
c See Topie: A/D & D/A CONVERTER, Long Answer Type Question No. 2(b) (3*d Part).

DSD-164
 12. Write
short
notes on any DIGITAL SYSTEM DESIGN
(a) 4 bit
Parallel Binary three of the followings.
(b) Master adder
Slave Flip
(c)CMOS Flop
and its operation
(d) PISO
Shift register
(e)Ringcounter
a) See Topic:
COMBINATIONALCIRCUITS,
b) See Topic:
SEQUENTIAL Long Answer Type Question
c) See Topic: CIRCUnS, No. 15).
LOGIC FAMILIES, Long Answer Type
Question
d) See Topic: Long Answer No. 170).
SEQUENTIAL Type Question No. 7(©).
e) See Topic: CIRCUITS,
SEQUENTIAL Long Answer Type Question
CIRCUTTS, No. 17(b).
Long Answer Type Question
No. 8D).

QUESTION
2019
Group A
(Multiple Choice
Type Questions)
1. Choose the
correct altenative
) In CMOS circuits, for any ten of
which type of power the following:
charging and dissipation occurs
discharging of load due to switching of transient
capacitance? Curent and
a) Static dissipation
c) Both (a) and (b) b) Dynamic dissipation
d) None of these
i) Which among the following
functions are performed
a) Gates, Op-amps by MSI category
of IC technology?
c) b) Microprocessor,
Filters A/D
d) Memory,
DSP
i) In pull-down network,
NMOS transistors are
conducting path between output connected in parallel
node and Ground yielding with the provision of
a) 1 Output.
b) 0
c) both (a) and (b)
d) none of
these
iv) CMOS logic dissipates .. powerthan TTL logic
circuits.
a) more b) less c) equal
d) very high
v) Inenhancement MOSFET, the magnitude of output current
magnitude of gate potentials due to an increase
in the
a) increases b) remains constant
c) decreases d) none of these

DSD-165
POPULARPUBLICATIONS
minimum propagation
families, the logic family having
DTL, TTL, ECE and CMOS logic
vAmong
delay iis d) CMOS
c) ECL
a) DTL b) TTL

upto
vii) An n-stage ripple counter can count d) 2
c)
a) 2" b) 2-
fip-flop is
the propagation delay of each
If
counters uses J-K flip-flops.
viH) A 4-bit modulo 16 ripple equal to
maximum clock frequency that can be used is d) 4 MHz
50ns, the MHz
b) 10 MHz c)5
a) 20 MHz

ix) Flip flops are b) sequential

circuit
circuit
a) combinational d) none of these
true
c) both (a) and (b) are
2-input AND gate is
1 MUX required to realize a
x) The minimum number pf 2: c)3
d) 4
b) 2
a) 1
a 4: 1 MUX is
MUX required to realize
The minimum number 2:
of 1 d)4
xi) c) 2
1 b) 3
a)

an 8: 1 MUX can be
used to obtain
additional circuitry,
Without any
xii)
Boolean functions of 3 variables
not all
a) Some but none of 4 variables
functions of 3 variables but
b) All
some but not all of 4
variables
of 3 variables and
c) All functions
variables
d) All functions of 4
BB
Group
Questions)
(Short Answer Type
expression
are they called so? Realize the
Why
universal logic gates?
2. What are
or NOR gates only.
AC+BC" using NAND No. 16.
S= COMBINATIONAL CIRCUITS, Short Answer Type Question
See Topie:

flip flop and explain

its operation.
diagram of a J-K
3 Draw the circuit Answer Type Question
No. 12.
SEQUENTIAL CIRCUITs, Short
See Topie:

DSD-166
 4. Reduce
the following
DIGITALSYSTEM DESIGN
F(4,B,C,D)Boolean function using Karnaugh
See Topic:
BOOLEAN
nction
=m(0,2.3,4,6,7,8Kanaugh Map to
the minimum possible
number of
ALGEBRA, 12,14,15)+d(1,5,13)
Short Answer literals.
5. What are
the differences Type Question
SRAM.
between
See Topic: static and
and dynamic
LOGIC RAM? Draw
FAMILIES, and explain the CMOS
Short Answer
6.Write Type Question
the VHDLVerilog No. 4.
See Topic: VLSI code for a
DESIGN 3-input AND
FLOWw, gate.
Short Answer
Type Question
No. T

Group-C
(Long Answer
7. Draw and Type Questions)
explain 4-bit
adder circuit? parallel adder
Also draw circuit.
What are the
See Topic:
COMBINATIONAL
and explain differences between
the serial adder serial and
CIRCUITS, circuit. paraiie
Long Answer
8. With the Type Question
help of block No. 14.
can we diagram explain
expand the word the
2048x 32 memory size and memory basiç operations of a semiconductor
using 256 x memory size of a memory chip? memory. How
See Topic:
LOGIC FAMILIES, 4 chips. Expand the word
Long Answer size of a
Type Question
No. 5.
9. Answer
the following:
a) What are
the differences between
b) Draw static and dynamic
and explain the CMOS RAM?
c) Draw SRAM.
and explain the CMOS
See Topie: DRAM.
LOGIC FAMILIES,
Long Answer Type Question
No.6.
10.
a) Why 2's complement
representation? representation has
better acceptability
6) Perform than 1's
complement
the addition of two negative
) Perform numbers (8) and (-9)
the addition of the 91 and 81 using 2's complement
using BCD arithmetic.
See Topic: arithmetic.
NUMBER SYSTEMS, Long
Answer Type Question
No. 2.
1. a) Express
NANO
De-Morgan's theorem and prove
gate. that negatve logic of an
OR gate is
equivalent
with
What are the limitations
of K-map? How can we overcome such
limitations?

DSD-167
 PUBLICATIONS
POPULAR what typs of logi gate?
an oxample of
case is
ways switch used in stair
application of two NAND gate only.
)The + BC+CA using (a)
Express the expression f= AB Answer Type Questfon No. B(a), (b), (e)
&

BOOLEAN ALGEBRA, Long

See Topic:

DSD-168