Binary Code and Classification Book
Binary Code and Classification Book
2
8. (b)
.(a
17,@ 18 (b) 19. (a
16(b 27. 1b)
28. (a)
29. tb
ANSWERS
26. d
25 a
E
1L 12
o sUPPLEMENTARY P R O
ARY PROBLEM
is
equvalent
octal
)
a n d binary
(73.89)10
BINARY CODES
namberto
Convert
the
foliowing
decimal
magnitude form using 1l's and 2's complement methods 45 +(-17). sult in s 22DISADVANTAGES OF BINARY CODES
16. Using 2's complement method unwanted signals called noise signals
are get added to it.
(a) (156)10-(9);0 perfom: 1. During transmission and reception,
17. Give
difference tby(16)10-5)10 '1' changeto0' dueto noise.
between Is 2'may change to '1' and may
18. Specify the maximum and complement, 2's complement and Larger data or information in binary
codes is difficult for the user to understand directly.
minimum 4-bit sign with suitable amples 3.
(a) sign
magninude form bl's
muaniber that can be magnitude Tor 91
complement form represented in
c) 2's
complement form
DIGIIAl RCUITS & LOGIC DESIGN
92 BINA
2.3 Various
CLASSIFICATION OF VARIOUS BINARY (DIGITAL)coDES
binary codes are classified as 2.3.1.1 BCD Code (Binary Coded DecimalCODES AND CLAssIFICATION
Code) 3
BCD represent each of
( a ) Binary digital clocks, calculators,decimal
as its
digit as a 4 bit
binary code. It is also known as 8421
output is always
from to 9. code(weighted code). it 1s
Weighted Codes
(i.e., 8421,
Tt takes decimal digit
separately and convert each into0 1Ou
5211, 5311, 2421, 3321,
5421, 6311, 4221
EXAMPLE Obtain BCD of binary coded form.
( 6 ) BCD 2.1
7421 sOLUTION: Convert 3 to binary(399)10
Non-weighted Codes
( a ) Excess-3
7421,8421) code using 8421
(3)10 (0011)pCD
code, we have
6)Gray Code Similarly,
910= (1001)BCD
(¢) Five bit BCD codes
9)10 (1001)BCD
a ) Excess-3 (399)10 (0011 1001 1001)gCD
=
Gray Code 0 1 1 1
Decimal Number Binary Equivalent -- -----.
10 0 0
0 0 0 0 0 0 0
0 9 0
0 0 0 1
oo l0
2 0 0 1 0
o 0 1 1 11 1 1 1
12
o100 110 0
O101 13
o 14
0 1 1 11
15 1 111
I 0 0 0
I 0 0 1
10
10 1 0 1 11
DIGITAL CIRCUITS & LOGIC DESIGN
BINARY CODES AND CLASSIFICATION|
23.222 Advantages of Gray Code bits and gray code bits are as s
and(b). Represent 1 C d
Binary Number
+Gray Code
DESIGN
DIGITAL CIRCUITS & LOGIC
for gray code. Discard the carry
bit ry iif comes.
|BINARY CoDES AND CLASSIFICATION 99
bt and write the next
bit to M S B
98 Case I . Add
the adjacent
Case I . Gray Code
+ Binary Number
Binary Number
Gray Code
(1)
Cary T Carry 1s Discard the carry
discardedd
discarded
Conversion
Code to Binary
2.3.2.2.5 Gray umber by considering following steps
can be converted
into its equivalent binary 0 (0+0)
The Gray Code
remains s a m e in binary number.
of the Gray Code
(Most Significant Bit)
(1) The MSB bit of the gray code, if cary comes discard thecan
generated to the next significant ary and
(2) Add each binary digit bit. Gray Code
write the sum a s next binary
Conversion
to Binary
Generalized form for Gray Code Similary, we have
Binary Number
Let the Gray Code be [Where, (ABCD) is any 4-bit Gray Code number]
(ABCDGray Code
Its binary number is Hence, (11011010)Gray Code (10010011)2
MSB LSB
B C D Gray Code 2.3.3 Reflective Codes
it is
Case I. Drop MSB as
reflective if the code for 9 is the complement for the code for 0,
the code for 8 is the complement
The code is said to be code for 3
Binary Number code for 6 is the complement for the
the code for 7 is the complement for the code for 2, the
A for the code for 1,
for the code for 4.
and the code for 5 is the complement
of reflective codes are
when the 9's complement must be found. The examples
Gray Code The reflectivity is desirable in a code
C D
excess-3 code.
Case 2421, 5211 and
A (AtB)
Binary Number 2.3.4 Sequential Codes
discard it. of data. In these codes each succeeding
code is one binaryy
I f carry comes
Sequential codes make use of mathematical manipulation
codes are 8421 and excess-3.
number greater than its preceding code. The examples of sequential
Similarly,
Gray.Code
2.3.5 Alphanumeric Codes
(i.e.,
data ietters, symbols and numbers). Thetelegraph which
Case IlL B It isspecial code which represents all alphanumeric
a
Other
which Hollerith code are the examples of alphanumeric codes.
use Morse Code in 1's and 0's and punched cards use
Binary Number
A (A+B)=Y (Y+C)=Z (Z+D) alphanumeric codes as ASCI, EBCDIC and ISCl.
discard it. 2.3.5.1 ASCII Code (American Standard Code For Information Interchange)
Ifcarry comes
0000 (0) NUL DLE SP Table 2.5 EBCDIC code EBCDIC code of
P from table 2.5 as shown belo Code have positions (01234567).
have bit (01234567). The
1De
r
ns is 00, 10,0000, elow.
0001 (1) SOH
DC A TABLE 2.5
0010 (2) STX DC2 B Bit
00
position 01 10 1
0011 (3) ETX DC C 0, 1
Abbreviations 1010 CC SM
ACK Acknowledge FS Form Seperator
1011 $
BEL Bell GS Group Seperator
HT Horizontal ab 1100
BS Backspace
LF Line feed
CAN Cancel 1101
CR Carriage Return NAK Negative acknowledge
1110 +
English language, make feasible to use Indian Seripts with English from table 2.6, 11000110 is F For example:
TABLE 2.6 Sine wavve:
10V-
Sin 0 30 5 60 0
Hex Dec 016|32 48 64 80 96 112 123 144| 160|176|192 |208 |224 2 Time
0 NUL DLE SP
P EXT
-10V-
Table 2.7
sOH DC A Fig. 2.2 Sine Wave
STX DC2 2B R From the table 2.7 we conclude that this shape is of sine wave as shown in fig. 2.2, hence we come to know about the
values at diferent points ie. at 0', 30, 45, 60, 90° etc. Similar examples for cosine wave can be considered.
s3ETXDca 3 cS s Now if this analog data is encoded into binary form, than a change in single bit can change the enture meaning or
information. Thus, the errors are categorised as
4EOT DC4S4 D T d
Erors
ENQ NAK s EU
66 ACK SYN | & 6 F Vf Single bit error Burst erTOr
BEL ETB 7 GW Here only 1 bit of given data unit (e.g. byte packet, word etc.) is changed from 1' to "0' or 0' to 'l'.
88 BS CAN H X For example : Let data at sender side be 10010001 as shown with data received
9 9 HT EM Y INV
A10 LF SUB Error
Data
B11 VTESC K ceived 1 1 1 0 o o
C 12 F FS a
These errors
occurs mostly in parallel transmission. For example If
at the same time and
using 8 wires to send all of the 8-bits
: we are o
byteWhereas in serial data transmission, the occurrence of these types of errors is very
that one of the wires is
imagine noisy,
therefore that bit will be corrupted in each byte.
D13 R GS M
For
rare.
example : Suppose a data is sent at 1 Mbps.
E 14 SO RS
This means that every bit lasts tor seconds or we can say 1 us. Therefore, for single bit error to occr
F15 S1US ? o DEL ATR 10.00,000
m u s t have a duration
of only 1 4s, which is very rare as noise normally lasts much longer.
104
2.3.6.1.2 Burst Error
Here two or more bits in the data unit changes from 0 to 1 or from 1 to 0.
For example: Data at sender 8Ide 18 as shown with received data in two exumplcs, one with : BINARY AND CLASsIFICATION
another with 6-bits burst error. one with S-bUH The most cominon.y Used mcthod for error d
Error are three l's in the codc, wnich will number of l's in the
coxde 'cven'. For
Therecode group includingtuthe parity bit willgive
aroup including odd number of l's.
So an cxtra '1' bit example,
1 to
is addedtne even.
1nub, the
make it even. Thus,
Received o
data
new
odd parlty methoa ueto nake
is
be 1011 100X).
number
This is called even
parity method.
u
hen the parity
bit is choKen as 0. So thatthe of l's in the code
'odd'. For example, if the code group is
bits 6 bits
the number of
1'a remains odd in
the new code.
J0
Length of burst orror is 5 bits Table 2.8 shows the BCD code (8421) with
Here length of burst parity bits
error is 6
In this fig. 2.3, thegenerating function generates some redundant bits which
is transmitted from the sender side over the link to receiver.
are
appended along with the bits
TABLE 2.8
data Even (E) Parity
Sender Recelver Odd (O) Parity
BCD (8421)
BCD (8421)
1010 1001 1001 1101 (Even Parity bit) P
Odd Parity blt)
0000
0000
Generating
ACcept 0001
0001 (O
0010
Function Checking
Function 0010
0011
0011
0100
Reject 0101
0100
1001 001 0110
0101
Redundant bits 0110
0111
0111
1000 1
1000
1001
100100110101001 1001101 0 1001
The parity bit can be attached either at the end or at the
Fig.2.3 Transmitting data from sender to recelver beginning of the code
design used. It is clear from the table that the number of l's are always even for group.
It depends on the type of system
Now the entire stream is passed through a checking function at the receiver side which decides whether the d always odd for odd parity. even and the number of l's
parity are
should be accepted or rejected. An error using parity bit can be detected for
single bit only but it cannot check for two errors at a time. Thus, only
2.362 Error Detecting Codes single error can be detected. To illustrate lets take an example
Data or entire bit stream is checked or detected by the following methods of error detection Let the code transmitted including the even
bit is parity given by
. VRC 2. LRC CRC 4. Checksum
0101
Error Detection
Even parity bit BCD code
Lets assume that the error is occured in LSB ie., (the last bit "1' becomes
'0') as shown
LRO VRC CRC Check Sum B i t error
Drawbacks of VRC
Even pariy b BCD code 23621.2
nunber
VRC method fals the beip of an erare
when
A e r end he a chek cituit fits o eTr becase te mumber of !'s are
fl's are appear
even
of bits are
changed This can be understood =ih
t be e e a i h i s s the
daauck of parity bit nethods. zppearer Een ir
as sbown in fig
puriy Thus e eror
Sender's deta Pamy r
uaer thingrve hee s i s ess that eos o r in aonsecuzive biss. The k D-DDD DDDDe
mesued f n he i s a p e i bt D e 2st carped mbee m g t be possbe t a some bits are
These aror os R y aT e a i Tasssaoa, as the d s i o n of noise is normaliy l n
lcege han te 3100
1000
236211 Camcept of Redndanc Recee -oe
Fan
One mettcd f r emr dnetice is a Evey daa sbruid bese c . o that the receiver can compae
t e d a nd y dhange i t wouid resuk m error eeeton. a t i s mehod is very time consu re
tie coS g
Rg. 2.5 VRC method fails in this example
S s onciacei t r e a d at endng zL e bts. scme sthorer TDY f bits should be applied at d
a Ts s caled s Redndang a e e m bes e d n i t to omation and these arr disceriedas The inportat poini 0 TOEE ere 5 tar eror occers2Ipositiozs ie. bt D 2ai iD- Tbe esar g s c g e d
so. t e wll da2 s corec bough i 3 2O
bet parity remains ac s
even. reever
e folowng data:
z2smisE s denerminei
Las p p o e =e wat o
an eac
11991009 VRC method can detect singie ba error. I can also dsea burs errors if the toazd xnba of errors n
data unt a odd.
uminer's and gpiies e psriy bir ( r I anis czse) io e a d Noa he otal mumber of 1's becomes evea
23622 LRC Longitndinal Redundancy Check)
Here instead ofsending a block of 32 bits. e make a tabie of for oms and eigt coiumns. So, the par
Receeer calculased for each colamm and bence a new row is created of eighs bits tich re the perity bits for i s whole block
Party r added to the wboie
Bock parity is the arrangemet of bits imo rOms and a redundent row of bits ie. pariry bits are
1011019 0-1010 G
0 1
Receiver
cecng me numb
f one s e q a io e e n
Cereraor acceps 2 s cored dza
99
1993193
Receved d a
kantangs.
9991191
14111149 99119
dea 1o be corect, sttwwh the ds vnaisaerr
1991 199
19191919 2362.3 CRC Cydhe Redundaney Chek)
CRCis basd n biary divissn, wdiks VR ard 1 E whh ase besed n itarn Here a seqnz d sehatda
99191919 bits called CKCIEnAder is appied 1o the ed d daa unit o that tie tesuitng detz isnes de vissti vy a preeterm
Paray sock seaed tr eah reportive sow binary nunber. On the receiver side, the data is divided by e sane nuzet aus it te remaiuór t m e s r , t a dda
isaseumed to be coret ad is aeped
w, tas sedundatt biok d ists it akied o the whle tick and is sent to the eoeiverin the forsal ss sónws Sremainder ther than e o Cmes, then it is asned thal data has t u snruprd n tbetwe
Deta00
Drso Dta Cac For example:
lf a polynomial is seiected such as
ntets
sOLUTION
divisor- 101)t0GI 0 bitsof zero'sadded to the 111110001
10101)1 100100101011
data Note that divisor is a+1.
1101 10101
110000
101 10101
11010
10101
11111
10101
10101
10101
When Left most bit -0 0 0 00 00000-Remainder
data is accepted,
otherwise it is
the unit result is zero,
The receiver receives is also complemented.
If the
arithmetic and the sum
one's complement
using
010 rejected.
101 Suppose data is
1010 1010 0011 0011
00 0 0 +001 10011
110
11011101
Sim
00100010
000 Checksum
00100010 2211+k+1
ie., 2 2 12 ++k
The minimum value of k is given by
Compkement 00000000
24212+4
Hence, there is no eToT i.e. 16 16
k = 4
23.6.3 Eror Correcting Codes Thus, the parity bits are 4 ' in number.
There are two ways to handie eror correction Their positions are given by
1. The receiver should retransnit the entire data. For P2"=1 ie. 1st Position.
ForP 2 2 ' = 2 ie. 2nd position.
2 For single bit enror, the receiver simply reverses the value of the corrupted bit.
An error comccting code is a binary code which will detect andcorrectsingle bit error occured during tanon: For P424 =4 ie, 4th position.
Thas, these are the codes which not only detect the error but also corect it. Example is Hamming code. ISmiSsKn For Pg2" 8 ie. 8h position.
=
C)The code word consisting of parity bits is used for the calculation of the sequency of bits that alternate check
M,M,M,P.M, B bits and skip bits.
For 1st position i.e. for
are
Here, P, P2 and P4 are the parity bits placed at 2m bit position, where m = 0, 1, 2, 3 -1. ( P
sucha way tht
For example, if the bit word to be transmitted is 4-bits wide. Then the value of k must be chosen in Skip Skip Skip Skip
1 bit bit l bit I bit
must satisfy as
2 2n+k+1
s
7 6 4 32
Check Check Check Check
Thus, for n =4 (* bit word is 4-bits wide in example) bit 1 bit Tbit 1 bit
we get, 2h2 4+k+1 Thus, for P considerbits 1, 3,5,7,9, 11, 13, 15,.. *******
Also, the parity bits P1, P2 and P4 are placed at 20, 2! and 22 i.e., at 1st, 2nd and 4th positions respectveiy
get the code format:
Check Check Check
2 bits 2 bits 2 bits
Bit numbers 6 Thus, for P consider bits 2, 3, 6, 7, 10, 11, 14, 15,..**
Allocated for- M| Ms Ms Pa MsPzP
DIGITAL CIRCUITS & LOGIC DESIGN BINARY cODES AND CLASSIFICATIONI 115
114 For 4th position ie, for P4 that the Dit at n posiaon is in we get unc
(ii) It is clear error. So, change the 4th bit i.e., complement it,
Skip 4 bits
Skip 4 bits Bit Positions
Received Code-
Check 4 bits Check 4 bits
Correct Code
consider bits 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23,...
Thus, for P
check bits and skip bits 1or positions 8, 16, 32.and so on
Similarly, there are altermate EXAMPLE 2.3 Assume data 1001101 as number of message bits or data bits without parity bits. Check
in the positions after checking comes odd, then set
(d) For even parity, the total number of l's
if et the parity bit error if any
the correct code.
and tind
0101 1010
Code: It is a representation
ofa
number or character in a unique way.
Excess 3 code
DIGITAL CIRCUTS & LOGIC DESIGN
BINARY CODES AND CLASsIFICATION j
LSE code > (4096) 10
ASCII
) 1001 0110- BCD
0100 0000
0110100 0110000 01i101 0110110 ASCI code
( ) Gray Code
(1 10 0 0 0 00 0 0
DGay Code
3 Code
Excess
(
(4096)10
3
MSB 2
(396)0= (1100011002
ASCHCode
(396) 1i000i100) 0111 0011 1100 1001 Excess 3 code
3 those errors for which it is designed, other types of errors may remain
undetected.
code can only detect
12 Structure of encoder and decoder in e r r o r detection
2 32 0 Codeword
Codeword Unreliable of
0 Transmission Bits
2 n-Bits
RECEVER
SENDER
MSB-
(4096)10 (1000000000000)2
DIGITAL CIRCUITS & LOGIC DESIGN
Círcuits.
and Hold
short note
on Sample BINARY cODES AND
CLASSIFICATION
120 I Ex.
Write a
and Hold circuits
are used to sample an analog signal at a particular
nstant ot
lirne verture t i m e Type of switeh
121
Solution : Sample andh
required Relay
sample as long
as
value of the control sígnal and the ho
Sampling instants
in
and Hold duration are
the circuit is being
which
Used.
determined by a logic d
interval depervda tm, In ma
50-100ns
FET
P'ast diode switche
application hold sample voltage. ns
CAPACITOR w
utilize a
These circuits the capacitor Acauisition time : t is
he shorlest tine after SAMPI. narnel has theen given tiat }1
a
a means 1or rapidly charging
a
controlled switch which provides (2) esult in cutput vollage vwhich approximaten
an
Itis an electronically can retain the desired voltage
the input voltage with cenary
Auta7
so that the capacitor
input sele
and then removing
the
circuit is shown with VA the analog
source and
R. the internal impedancr De3)
3) Settling time a »pecifiea epercentage
aal value, within onthe opening of the switch (0O.D) t the peoint when the tnutput has
scale.
A sample and Hold
Rate : This represent ire an"
Sample and Hold Circuit (4) Output Decay en the voltagc change acrs the capacitn during the HOLI
Switch controlled by Ve w
eruely proportional
capacitance s i n e dv,/dt m 1/¬:
the capacitor lcakage current.
where I is
It may arise
Bias current in an op-anp ) EAkage current through switch (e) Internal leakage in the capaciur.
VA
C. Vo (a)
Practical Circuit
der to achieve a low driving Circuit impedance and a high load impedance acros the holding circut, a pracuea
In o
Hold eircuits
are used.
sample and Circult with switch
Inverting Sample-Hold
also as shown. is as shown. It operatcs as follows
dealized waveforms are
Tts circuit
Voltage held is closed (SAMPIE), the circuit acts as a conventional op-amp RC filter. When switch (S) is openea,
When switch S
WIill h e l d on the capacitor.
Error the voltage Va
Circuit with switch is as shown
Inverting sample hold
R
Aperture
time
Sarmple
A
Sample
Hold
Acquisition
time Inverting Sample-Hold Circuit with FET's
Sample FET as a switch is shown in figure
Hold VA D
E the assumption RCS
Explanation: The switch is closed while the control logic waveform Vc is high and on
the output voltage will vary closely follow the input voltage and will be equal to it at the
instant that the controlng* Hold
sal,
goes low, opening the switch.
During the Hold interval, while the control signal is low, the switch is open and capacitor 'C' will hold the las HE b
vaiue.
Sample
Various Specifications
nd the i op-amp
(1) Aperture time : It is the maximum delay between the time that control logic tells the switch to open an
that it actually does. It determines the type of switch to be used.
LOGIC DESIGN
DIGTAL CIRCUTS & În this type of transistor.Creatiflows whn
wich sapchennel depiedon
FET.
m o r e negative. In this cin ut
BINARY cODES AND CLASSIFICATION
FETswach T. souroe o gaae voitage becomes the FET numbers in Excess-3 Code. (PTU. E C E ,
Dec. 2005)
es es a s the
eaarged
ot the nPut is changed
a s i n e poiangy opezu Add the following
soue
n d drain
T
(PTU,
and disadvantages ? (PTU, CSE, Dec.
De
2009, Mar
108 + 789
s
interz s
? Hhat a r e its advantages
FEL
W a t is a
BCD a d e
coaed dacinal
co e tor the rpresentation tal of igi (275+ 496
code
s e Dnay excess-a
1010 1010
a d semai. Numbers 0 to 9, punctuuation marks and many other symbols.
aASCH ade (1010 1010 0100)Exces-3 or (771)10
saa
basically produces
wrd wich grdesnainly
sth
sed in shaft position encoders. A position encoder
ngsia posiioe of the shaft
BINARY CODES AND CLASSIFICATION
DIGITAL CIRCUITS & LOGIC DESIGN do you
you mean by G
mean Gray code ? Convert the following numbers
125
Gray coae
following
numbers in BCD
PTU, ECE, May E13
What
6) (286)10
to
(363.3eCD
2 0 5 . 7 + 193.65
2 40
0010 0000 0101 0111 0000 2 2 0
0011. 0110 0101
+ 0001 1001
MSB-
1000 1101
Invalid Valid (286)10=(1000111102
(i 1 110 1
0 0Gray Code
LOGIC DESIGN 127
DIGITAL CIRCUITS & BINARY CoDES AND CLASSIFICATION
requiredequve
Decimal
Coded
digit c a n be as long a s aa four bits are Write
decimal
resultis
Soluion:
a
Binary
coded called
binary-coded
decimal.
Since a decimal
lo FEx 19
Solution: (87)10 = (?)BCD
such as 678 (decimal).
decimal numbers
digit. take a
the BCD code,
To illustrate
(1000 0111)BCD PTU, CSE,
Dec. 2010)
OBJECTIVE TYPE
0101 0001 (BCD)
1001 D O O O
Q U E S T I O N S
are
For illustration more examples
1001 (BCD) to its decimal equivalent.
Convert 0111 1000 0011 is
( in a self-complementing
code
- 9
s u m of weights
8 9 10 (a) 111011011010
( 10-bt code
code is a
c ) 7-bit code
BCD addition. 4. ASCII
Ex. 17Solve the following using ()9-bitcode
(6) 6-bit code
Gray Code
DIGITAL GRC OGIC DESIGN
the word kength of Hanming code is
14. To represent deeianat digiks
c) 7
i d
3
is not a setf cemplenenting code ?
.Which of the koklowing
fa) Ciray cod b) Eycic cede ic) Hahning code
d All the abse Output
ANSWERS
.t
12 13 tc
4.(e)
14. fe
.
15 d
9. NOT
ANELOGIC GATES
sUPPLEMENTARY PROBLEMS AND BOOLEAN ALGEBRA
.What is & seif-compiementary code
7
Explais briefly?
cod*. 3 . 0 INTRODUCTION
2. Wrs the steps nvoived is ceatsng a Harmening electronic circuit makes the logical decisions. Most common logic gates
which
used are AND, OR,
15 an
3. Write the procedure fox the comversion of the folaowing A logic gate
universal gates.
ti#y Gray code o binary coxde NOT. NAND, NOR, XOR. XNOR
gates. NAND and NOR gates are called certain input combinatuons
in Binary code to (iray code is High only for
have one or more inputs and only one output. The output
Logic gates are or
boolean variables. Boolean
functions
between even parity and oxdi parity expressions having
4. Esplaun the difference Boolean algebra
contains boolean function which are