1

FC & ICC2

############## IO placement commands #########

# To open lib
open_lib lib_name

# To close current lib

close_lib lib_name

# To check what is current lib

current_lib lib_name

# To save current lib

save_lib lib_name

# To show all libs in your design

get_libs
report_libs

# create lib
create_lib lib_name -ref_name { all ndm file}
current_lib

# lib set
ctrl + k == To show preference
ctrl + r == To show properties
ctrl +s == To open option windowtrl + k == To show preference
ctrl + r == To show properties
ctrl +s == To open option windowtrl + k == To show preference
ctrl + r == To show properties
ctrl +s == To open option windowreate a collection of the libraries you want to
analyze, which is known as a libset, by
using the create_libset command, as shown in the following example:
fc_shell> create_libset -name myLibset -libs {abcd1 abcd2}

You can specify the naming convention for this library by using the
set_lib_cell_naming_convention command, as shown in the following example:
fc_shell> set_lib_cell_naming_convention -library $lib \
-column 1 -pattern {[a-zA-Z0-9]*} -attribute
"lexical_cell_prefix_name"
fc_shell> set_lib_cell_naming_convention -library $lib \
-column 2 -pattern {D[0-9]*} -attribute "lexical_drive1_name"
fc_shell> set_lib_cell_naming_convention -library $lib \
 2
-column 3 -pattern {WS} -attribute
"lexical_well_substrate_bias_architecure"
fc_shell> set_lib_cell_naming_convention -library $lib \
-column 4 -pattern {ULVT|SVT|LVT|MVT} -attribute
"lexical_device_threshold_voltage"

# CORE pG pads creation

create_cell {core_power_pad1_ew core_power_pad2_ew core_power_pad3_ew
core_power_pad4_ew core_power_pad5_ew core_power_pad6_ew
core_power_pad7_ew core_power_pad8_ew} vDD_EW
create_cell {core_power_pad1_ns core_power_pad2_ns core_power_pad3_ns
core_power_pad4_ns core_power_pad5_ns core_power_pad6_ns core_power_pad7_ns
core_power_pad8_ns} vDD_NS
create_cell {core_ground_pad1_ew core_ground_pad2_ew core_ground_pad3_ew
core_ground_pad4_ew core_ground_pad5_ew core_ground_pad6_ew
core_ground_pad7_ew core_ground_pad8_ew} vSS_EW
create_cell {core_ground_pad1_ns core_ground_pad2_ns core_ground_pad3_ns
core_ground_pad4_ns core_ground_pad5_ns core_ground_pad6_ns
core_ground_pad7_ns core_ground_pad8_ns} vSS_NS

# iO pG pads creation
create_cell {io_power_pad1_ew io_power_pad2_ew io_power_pad3_ew
io_power_pad4_ew io_power_pad5_ew io_power_pad6_ew io_power_pad7_ew
io_power_pad8_ew} iOVDD_EW
create_cell {io_power_pad1_ns io_power_pad2_ns io_power_pad3_ns
io_power_pad4_ns io_power_pad5_ns io_power_pad6_ns io_power_pad7_ns
io_power_pad8_ns} iOVDD_NS
create_cell {io_ground_pad1_ew io_ground_pad2_ew io_ground_pad3_ew
io_ground_pad4_ew io_ground_pad5_ew io_ground_pad6_ew io_ground_pad7_ew
io_ground_pad8_ew} iOVSS_EW
create_cell {io_ground_pad1_ns io_ground_pad2_ns io_ground_pad3_ns
io_ground_pad4_ns io_ground_pad5_ns io_ground_pad6_ns io_ground_pad7_ns
io_ground_pad8_ns} iOVSS_NS

set_attribute [get_lib_cells vDD_EW] -name reference_orientation -value r90 "enter"

# IO guides creation
create_io_guide -name top_guide -side top -line {{0 1800} 1800} -offset {360 360}
-pad_cells $top
create_io_guide -name right_guide -side right -line {{1800 1800} 1800} -offset
{360 360} -pad_cells $right
create_io_guide -name left_guide -side left -line {{0.000 0.000} 1800} -offset {360
360} -pad_cells $left
create_io_guide -name bottom_guide -side bottom -line {{1800 0} 1800} -offset
{360 360} -pad_cells $bottom

report_io_guides "enter"
 3

create_io_ring -name pad_ring -guides {*_guide} "enter"

# power_io_constraints
set_power_io_constraints -io_guide_object [get_io_guides {top_guide
bottom_guide}] {{reference_cell:vSS_NS} {ratio:4}}
set_power_io_constraints -io_guide_object [get_io_guides {top_guide
bottom_guide}] {{reference_cell:vDD_NS} {ratio:4}}
set_power_io_constraints -io_guide_object [get_io_guides {top_guide
bottom_guide}] {{reference_cell:iOVSS_NS} {ratio:4}}
set_power_io_constraints -io_guide_object [get_io_guides {top_guide
bottom_guide}] {{reference_cell:iOVDD_NS} {ratio:4}}
set_power_io_constraints -io_guide_object [get_io_guides {left_guide right_guide}]
{{reference_cell:vSS_EW} {ratio:4}}
set_power_io_constraints -io_guide_object [get_io_guides {left_guide right_guide}]
{{reference_cell:vDD_EW} {ratio:4}}
set_power_io_constraints -io_guide_object [get_io_guides {left_guide right_guide}]
{{reference_cell:iOVDD_EW} {ratio:4}}
set_power_io_constraints -io_guide_object [get_io_guides {left_guide right_guide}]
{{reference_cell:iOVSS_EW} {ratio:4}}

# signal io constraints
set_signal_io_constraints -io_guide_object right_guide -constraint "{40} $right"
set_signal_io_constraints -io_guide_object left_guide -constraint "{40} $left"
set_signal_io_constraints -io_guide_object top_guide -constraint "{40} $top"
set_signal_io_constraints -io_guide_object bottom_guide -constraint "{40} $bottom"

# placing pads
place_io "enter"

# creating io fillers
set_attribute [get_lib_cells fILLER*] -name reference_orientation -value r90 "enter"
create_io_filler_cells -reference_cells {fILLER50 fILLER40 fILLER35 fILLER20
fILLER15 fILLER10 fILLER5 fILLER1 fILLER01} -io_guides [get_io_guides ] "enter"

set_locked_objects [get_cells -filter "physical_status==placed"] "enter"

# It shows io placement check

check_io_placement "enter"
check_io_placement -power_constraints "enter"
check_io_placement -signal_constraints "enter"

######### floorplan #########

 4
initialize_floorplan -control_type die -honor_pad_limit -side_length {1800 1800} -
core_offset {350 350} -core_utilization .7 -site_def unit -use_site_row -boundary {{0
0} {1800 1800}} -coincident_boundary false "enter"

# To get core area

get_attribute [get_core_area] area "enter"

# It will show all ref_name of cells and buffers.

get_cells -filter "ref_name=~*BUF*"

# To check attribute of all cells

list_attribute -application -class cell

# To check attribute of selected item

list_attribute -application -class press_tab

# To check total numbers of buffer in my design

sizeof_collection [get_cells -filter "ref_name=~*BUF*"]

# To get the total numbers of port

sizeof_collection [get_ports *]

# To get the total numbers of macro

sizeof_collection [get_flat_cells -filter "is_hard_macro"] "enter"

# To get the total numbers of std cells

sizeof_Collection [get_flat_Cells -filter "!is_hard_macro"] "enter"

# Remove boundary cells

remove_cells [get_flat_cells *boundaryfiller* -all]

# Remove tap cells

remove_cells [get_flat_cells *tapfiller* -all]

# It shows all the macro in the deisgn

get_flat_cell -filter "is_hard_macro==true" "enter"

# It shows all the cell which have "cell" class

list_attributes -class cell -application "enter"

# It shows number of power pad in the design

sizeof_collection [get_flat_cells *iopad] "enter"
 5
# It shows total number of std cell in the desig
sizeof_collection [get_flat_cells] "enter"

# Remove all rulers inside the design

gui_remove_all_rulers -window [gui_get_current_window -types layout -mru];
"enter"

# Get_lib_cells -of_objects [get_cells vDD]

# It shows end cap cells

check_boundary_cells "enter"

# Io lock physical objects

set_locked_objects [get_cells -filter "physical_status==placed"] "enter"

# Io check how many fillers cells are added in my design

get_cells -q -physical_context *fill* "enter"

# Io know whether selected is available in my design or not

get_lib_cells *fILL* "enter"
get_lib_cells *tap* "enter"
get_lib_cells *boundary* "enter"

# Io place std cell or macro by using coordinates

set_cell_location [get_flat_cells i_CLOCK_GEN/i_PLL_SD] -coordinates {380.0560
459.2280} "enter"

# Tracks creation
remove_tracks -all "enter"
create_track -layer m1 -dir y -offset 0 -bbox [get_attribute [get_core_area ] bbox] -
relative_to core_area "enter"
create_track -layer m2 -dir x -offset 0 -bbox [get_attribute [get_core_area ] bbox] -
relative_to core_area "enter"
like that for aLL mETAL lAYERS "enter"

## Sites creation
remove_site_rows -all "enter"
create_site_array -site unit -boundary {{350 350} {1450 1450} } "enter"

# Both are use to get the macro name

get_attribute [get_cells -hierarchical -filter "is_hard_macro"] name "enter"
get_flat_cells -filter "is_hard_macro" "enter"

# To get the info about selected area

 6
get_attribute [get_selection ] name "enter"

# Set keepout margin

create_keepout_margin -type hard -outer {5 5 5 5} [get_cells
i_CLOCK_GEN/i_PLL_SD] "enter”

# To save library
save_lib lib name "enter"

# To save block
save_block and save_block -as block_imported "enter"

# Placement of ports :--

# Setting the constraints for the ports
set_block_pin_constraints -self -allowed_layers {m3 m4} -side {2} -hard_constraints
location "enter"

# To set the direction of routing layer

set_attribute [get_layers {m1 m3 m5 m7 m9}] routing_direction horizontal "enter"

# To check routing direction

get_attribute [get_layers m*] routing_direction "enter"

# Placing the ports

place_pins -self

# Creating voltage area

create_voltage_area -power_domains pD_RISC_CORE -guard_band {{$a $b}} -
region {{$llx $lly} {$urx $ury}} "enter"

# Macro placement - enabling different colors for different families

set_color -cycle_color "enter"

# To fix macro
set_attribute [get_flat_cells -filter "is_hard_macro" ] physical_status fixed "enter"

# To unfix macros
set_attribute [get_flat_cells -filter "is_hard_macro" ]physical_status fixed -value
placed "enter"

# To fix all hard macros , iO , corner cells

set_locked_objects [get_cells -physical_context -filter "is_hard_macro && !
is_physical_only"] physical_status fixed "enter"

# To fix ports
 7
set_attribute [get_ports *] physical_status fixed "enter"

# Create boundary cell

create_boundary_cell -right_boundary_cell *fILL3_HVT -left_boundary_cell
*fILL3_HVT "enter"

# Compile boundary cell

compile_boundary_Cells "enter"

# Create tap cell

create_tap_cell -lib_cell *fILL3_HVT -distance 60 -offset 30 -pattern stagger "enter"

check_boundary_cells
compile_boundary_cells
compile_targeted_boundary_cells
remove_boundary_cell_rules
report_boundary_cell_rules
set_boundary_cell_rules

# To create filler
create_stdcell_fillers -lib_cells {fill_lib/fill1x fill_lib/fill2x}
report_cell_groups

# To get the block coordinate

get_attribute [current_block ] boundary

# To get shapes
get_shapes

# To get vias
get_vias

#################### Checks after floorplan

###############
# To check the netlist
check_netlist "enter"

# To check the timing

check_timing "enter"

# To check multi voltage design

check_design -checks mv_design "enter"

# To check mismatch
 8
report_design_mismatch "enter"

# To check the state of design

check_Design_states "enter"

# To check summary of floorplan

report_design -floorplan

# Check utilization
report_utilization

## Check boundary cells

check_boundary_cells

############ power plan commands ########

# To create net
create_net -power vDD "enter"
create_net -power vSS "enter"
_________________________________________________________
create_net -power vDD "enter"
create_net -ground vSS "enter"
connect_pg_net -net vDD [get_pins -physical_context vDD] "enter"
connect_pg_net -net vSS [get_pins -physical_context vSS] "enter"

# To remove pg strategy
remove_pg_strategies -all "enter"

# To remove pg pattern
remove_pg_patterns -all "enter"

# To remove strips
remove_routes -stripe "enter"

# To remove rings
remove_routes ring "enter"

# To remove follow pins

remove_routes -lib_cell_pin_connect "enter"

# To remove vias
remove_vias vIA_SA_29 "enter" to remove via

# To remove all via

 9
remove_vias vIA_SA_* "enter"

# To see details of reunning commands

any_commands -v -e "enter" {v = verbose , e = echo} "enter"

# To remove all nets or vDD , vSS and all

remove_nets -all "enter"

# Create pg ring
create_pg_ring_pattern ring_pattern_1 -horizontal_layer m9 -horizontal_width {10}
-horizontal_spacing {2} -vertical_layer m8 -vertical_width {5} -vertical_spacing {1}
"enter"

# Treate pg ring strategy

set_pg_strategy core_ring_1 -pattern {{name:ring_pattern_1} {nets: {vDD vDD vSS
vSS}} {offset:{2 2}} } -core "enter"

# Compile ring
compile_pg -strategies {core_ring_1 core_ring_2} "enter"

# Create keepout margin

create_keepout_margin -type hard -outer {5 5 5 5} {i_CLOCK_GEN/i_PLL_PCI
i_CLOCK_GEN/i_PLL_SD i_CLOCK_GEN/i_CLKMUL} "enter"
create_keepout_margin -outer {5 5 5 5} [get_flat_cells -filter "is_hard_macro"]

############ checks after power plan ##################

check_pg_connectivity "enter"
check_pg_connectivity -check_std_cell_pins none "enter"
check_pg_drc "enter"
check_pg_drc -ignore_std_cells "enter"
check_pg_missing_vias "enter"
check_mv_design "enter"
check_report_power "enter"

############### placement ################

set_app_option -name place.coarse.continue_on_missing_scandef -value true

# Global placement
coarse placement
create_placement -incremental "enter"

# Legalize placement
legalize placement
legalize-placement "enter"
 10
# Details placement
detail placement
place_opt -to final_opto "enter"

# Report design
report_design

# Report early data checks for coarse placement

report_early_data_checks -checks place.coarse.missing_scan_def

############ CELL swapping ################

size_cell i_ORCA_TOP/i_RISC_CORE/i_CONTROL/u28 aND2X1_LVT

# Save design
save_design - block and dEF

# To remove all placement blockages

remove_placement_blockages -all

# To create bound
create_bound -name bound_name

# To define a soft move bound, use the following syntax:

create_bound -name name [-type soft] [-effort effort_level] -boundary {coordinates}
[bound_objects]

# The default effort is ultra; you can also specify low, medium, or high

# To cfreate rectangular bound

create_bound -name b1 -boundary {100 100 200 200} iNST_1

# To define a hard move bound, use the following syntax:

create_bound -name name -type hard -boundary {coordinates} [bound_objects]

# Sanity checks:---
1 - congestion -
a - global route congestion
go to view -> map -> global route congestion -> reload or report_congestion -
rerun_global_router
b - cell density
go to view -> map -> cell density
c - pin density
go to view -> map -.> pin density
2 - logical dRC
 11
a - max trans
b - max cap
c -max fanout
3 - timing check (setup)

## Global routing congestion

report_congestion -rerun_global_router "enter"

## Max transition
report_constraints -max_transition "enter"

## Max capacitance
report_constraints -max_capacitance "enter"

## Legality
check_legality "enter"

## Timing checks
report_timing -delay_type max "enter"

## Save block
save_block -as place_done "enter"

## Save dEF
write_def "enter"

## To create blockages
create_placement_blockage

to create keep out margin - create_keepout_margin

## Fix----
1 - swapping of cells (hVT to lVT , lVT to hVT)
2 - up-sizing and down-sizing of cells
3 - inserting buffer
4 - cloning
5 - path group

# To get power(VDD) nets of selected cell

fc_shell> get_pins -of_objects [get_Selection ] -filter "port_type==power"

# To get power(VSS) nets of selected cell

fc_shell> get_pins -of_objects [get_Selection ] -filter "port_type==ground"
 12
# To get signal (in & out) nets of selected cell
fc_shell> get_pins -of_objects [get_Selection ] -filter "port_type==signal"

## To get input pins name & nets name , output pins name & net name.
report_cells -connections [get_selection ]

############### swapping and sizing of cells ###############

# Swapping
report_timing -from
i_ORCA_TOP/i_SDRAM_TOP/i_SDRAM_WRITE_FIFO/reg_array_reg_3__4_
oR2X2_LVT

# Strength
report_timing -from
i_ORCA_TOP/i_SDRAM_TOP/i_SDRAM_WRITE_FIFO/reg_array_reg_3__4_ -to
i_ORCA_TOP/i_SDRAM_TOP/i_SDRAM_WRITE_FIFO/data_out_sync_reg_4_

# To know whether we have differenet flavour cells and drive strength

get_alternative_lib_cells i_ORCA_TOP/i_BLENDER_1/mult_219/u2

# To know which cell is added in any perticular net

get_lib_cells -of_objects i_ORCA_TOP/i_BLENDER_1/mult_219/u2 = without pin

## To get the alternative lib cells available

get_lib_cells */ref_name* "enter"

## To get alternative drive strength with same flavour

get_lib_cells */AND*_LVT "enter"

## To get alternative vT cells with same drive strength

get_lib_cells *AND2_*VT "enter"

## To swap the cell

size_cell "enter"

################ add buffer & remove buffer ################

# The following example shows the command adds buffers on net1 using the
lib/BUF library cell. The repeater distance is 100 and the first distance is 80.
prompt> add_buffer_on_route -repeater_distance 100 \ -first_distance 80 net1 -
lib_cell lib/BUF
add_buffer_on_route -first_distance 30 -repeater_distance 100
I_ORCA_TOP/I_SDRAM_TOP/I_SDRAM_IF/eco_net_2_cts0 -lib_cell NBUFFX2_RVT
{adding multiple buffers on net}
 13
fc_shell> add_buffer_on_route -repeater_distance 100
I_ORCA_TOP/I_PCI_W_MUX/pci_wfifo_data[3] -lib_cell saed32hvt_c/NBUFFX2_HVT
fc_shell> get_cells -of_objects [get_nets
I_ORCA_TOP/I_PCI_W_MUX/pci_wfifo_data[3]] == To see whether my cell is added
or not.

# It will show you cell cell name which is connected through below net.
fc_shell> get_cells -of_objects [get_nets
I_ORCA_TOP/I_PCI_W_MUX/pci_wfifo_data[3]]
{I_ORCA_TOP/I_PCI_W_MUX/U7 I_ORCA_TOP/I_PCI_W_MUX}

# To get_net report
report_net -connections net_pserr_n_in -nosplit

# The following example adds buffers on net1 using the lib/BUF library cell. One
location is specified and let command to detect layer.
prompt> add_buffer_on_route -location {100 200} -detect_layer net1 \

## To insert buffer
insert_buffer instance_name_with_pin space cell_name_from_library

# To remove buffer
remove_buffer instance_name

################### creating buffer

#######################
get_lib_cells *BUFF*
create_cell {adil_buff1 adil_buff2 adil_buff3 } saed32hvt_c/NBUFFX4_HVT
get_attribute [get_cells adil_buff3] ref_name

##################### creating nets

#######################
fc_shell> create_net adil_net1

# to show all corners

report_scenarios

# To show all corners

report_corners

# To get timing reports

report_timing

# To get all timing reports

report_global_timing
 14

# To get hold reports

report_timing -scenarios func_ff1p16v125c_cbest

# To get setup reports

report_timing -scenarios func_ss0p95v125c_cworst

# To get all max path reports

report_timing -delay_type max

# To get max fall path reports

report_timing -delay_type max_fall

# To get max rise path reports

report_timing -delay_type max_rise

# To get all min path reports

report_timing -delay_type min

# To get min fall path reports

report_timing -delay_type min_fall

# To get min rise path reports

report_timing -delay_type min_rise

# To get parasitics reports

report_parasitics

# To get all parameters reports

report_parasitic_parameters

# To get setup fixing terminology

get_app_options *setup*

# To get get max trans reports

report_constraints -all_violators -max_transition transition.txt

# To check short violation

check_lvs -max_errors 100 -checks short

# For to check open nets for a specific net

check_lvs -checks open -nets {biss_bg_vref_out} -open_reporting detailed------>for
to check opens of a specific net

# To get min width and spaicng of perticular metal layers

 15
get_attributes [get_layer m9] min_width
get_attributes [get_layer m9] min_spacing

### checks after placement without generatig reports

# redirect logs/$node/create_placement.log {create_placement} -tee -file
# redirect logs/$node/legalize_placement.log {legalize_placement} -tee -file
# redirect logs/$node/place_opt.log {place_opt} -tee -file

## sanity checks#####

# redirect rpts/$node/congestion.rpt {report_congestion} -tee -file

# redirect rpts/$node/check_legality.rpt {check_legality} -tee -file
# redirect rpts/$node/report_placement.rpt {report_placement} -tee -file

##generating reports path group wise###

#sh mkdir rpts/$node/setup

# redirect rpts/$node/timing_summary.rpt {report_global_timing -

separate_all_groups} -tee -file
# redirect rpts/$node/report_constraints.rpt {report_constraints -all_violators} -tee
-file

## checks after placement without reports

report_congestion
check_legality
report_placement
report_global_timing
report_timing
report_constraints -all_violators
report_constraints -max_transition -verbose -all_violators
report_constraints -max_capacitance -verbose -all_violators
report_global_timing -separate_all_groups

###################################################
#################### clock tree synthesis #############

# Before cts checks

check_design -checks pre_clock_tree_stage "enter"

report_clocks -physical -nosplit

report_clock_qor -type enter tap

create_io_guide -name right_guide -side right -line {{1800 1800} 1800} -offset
{360 360} -pad_cells $right
 16

report_clock_timing -type skew

report_analysis_coverage = it will show all violation with % , how much solve and
what is remains = pt_shell command

write_sdc -output sdc_name

write_sdf sdf_name

report_timing -input_pins

set_max_transition

remove_max_transition

set main_clk {pclk sys_clk sdr_clk}

pclk sys_clk sdr_clk

set clk_name {sDRAM_CLK pCI_CLK sYS_2x_CLK sYS_CLK }

create_routing_rule
remove_routing_rules(2)
report_routing_rules(2)

create_routing_rule clock_ndr_2w2s -default_reference_rule -widths {m4 0.06 m5

0.06 m6 0.06 m7 0.06} -spacings {m4 0.06 m5 0.06 m6 0.06 m7 0.06}
set_routing_rule(2)
set_clock_routing_rules -net_type root -rules clock_ndr_2w2s -min_routing_layer m4
-max_routing_layer m7
remove_clock_routing_rules -
clocks default_rule net_type nets rule
set cts_cell " saed32lvt_c/nBUFFX2_LVT saed32lvt_c/nBUFFX4_LVT
saed32lvt_c/nBUFFX8_LVT saed32lvt_c/nBUFFX16_LVT saed32lvt_c/iNVX2_LVT
saed32lvt_c/iNVX4_LVT saed32lvt_c/iNVX8_LVT saed32lvt_c/iNVX16_LVT "
saed32lvt_c/nBUFFX2_LVT saed32lvt_c/nBUFFX4_LVT
saed32lvt_c/nBUFFX8_LVT saed32lvt_c/nBUFFX16_LVT saed32lvt_c/iNVX2_LVT
saed32lvt_c/iNVX4_LVT saed32lvt_c/iNVX8_LVT saed32lvt_c/iNVX16_LVT
fc_shell> set_lib_cell_purpose -include cts $cts_cell
information: the design specific attribute override for lib_cell
'saed32lvt_c:nBUFFX2_LVT.timing' is set in the current block 'oRCA', because the
actual library setting may not be overwritten. (aTTR-12)
set_scenario_status -active true [get_scenarios ]

# To get clock qOR

report_clock_qor -
 17
all histogram_bins modes scenarios smallest
clocks histogram_max nosplit show_paths through
corners histogram_min output show_verbose_paths to
csv histogram_type per_clock_root significant_digits
trace_beyond_exception
from largest robustness_corner skew_group type

# To get clock qor related to corners

report_clock_qor -corners
ff1p16v125c ss0p95v125c

# TO get report related to clocks

report_clock_
report_clock_balance_groups report_clock_gating_checks
report_clock_power report_clock_timing
report_clock_balance_points report_clock_gating_enable_condition
report_clock_qor report_clock_tree_options
report_clock_cell_spacings report_clock_gating_objects
report_clock_routing_rules report_clock_tree_reference_subset
report_clock_gate_latency report_clock_gating_tree_options
report_clock_settings report_clock_trunk_endpoints
report_clock_gating report_clock_jitter
report_clock_skew_groups report_clock_trunk_qor

# Clock_opt

# redirect logs/$node/clock_opt.log {clock_opt} -tee -file

####sanity checks###

# redirect rpts/$node/check_timing.rpt { check_timing } -tee -file

###reports####
# redirect rpts/$node/report_clock_tree.rpt { report_clock_tree_options } -tee -file
# redirect rpts/$node/timing_summary.rpt {report_global_timing -
separate_all_groups} -tee -file
# redirect rpts/$node/congestion.rpt {report_congestion} -tee -file
# redirect rpts/$node/clock_drv_violations.rpt {report_clock_qor -type drc_violators
-all} -tee -file
# redirect rpts/$node/report_utilization.rpt {report_utilization} -tee -file

# Checks after cts without generate reports

report_clock_tree
report_global_timing
report_timing
report_congestion
 18
report_clock_qor
report_clock_qor -type drc_violators -all
report_utilization
check_timing
report_constraints -max_transition -verbose -all_violators

################ routing ################

# To get how many nets in your design
sizeof_collection [get_nets ]

# redirect logs/$node/route_auto.log {route_auto} -tee -file

# redirect logs/$node/route_opt.log {route_opt} -tee -file
# redirect logs/$node/optimize_routes.log {optimize_routes -
max_detail_route_iterations 8} -tee -file

## sanity checks#####

# redirect rpts/$node/check_routability.rpt {check_routability} -tee -file

# redirect rpts/$node/check_routes.rpt {check_routes} -tee -file
# redirect rpts/$node/check_lvs.rpt {check_lvs} -tee -file

### reports ####

# redirect rpts/$node/report_utilization.rpt {report_utilization} -tee -file

# redirect rpts/$node/timing_summary.rpt {report_global_timing -
separate_all_groups} -tee -file

## checks after route without generating reports

route_opt
optimize_routes -max_details_route_iterations 10
check_routability
check_routes
check_lvs

########### LVS commands ############

# To check attribute of selected things

get_attribute [get_selection] owner
get_attribute [get_selection] net
get_attribute [get_selection] origin
get_attribute [get_selection] physical_status

# To check pins and ports of slelcted cells

get_ports -of_objects [get_selection ]
 19
get_pins -of_objects [get_selection ]

# To select net and do modification

change_selection [get_nets net_name]

# To checks detailed open for individual nets

check_lvs -nets [get_net adil_net1] -open_reporting detailed
# To check only shorts
check_lvs -checks short
# To check individual nets info
check_lvs -nets net_pserr_n_in
# To check short violation in adil_net3
check_lvs -checks short -nets adil_net3
# To check route length & metal layer of slected full net
get_attribute [get_selection ] route_length

# To get net length

change_Selection [get_nets -of_objects [get_selection ]]
get_attribute [get_Selection ] dr_length

# If net is already connected use this command to disconnect net

disconnect_net -net net_pserr_n_in [get_selection ]

# To check info or open / shorts on this nets

check_lvs -nets net_pserr_n_in

############### How to fix OPEN #############

check_lvs -max_errors 100
open error browser ( CTRL + SHIFT + E)
select the open net & see the info
come to GUI
check In & OUT pin
click on IN pin
shift + r & slect metal layer
check whether net is slected or not on check slection BOX
NOW ROUTE

############## How to fix shorts ##############

check_lvs -max_errors 100
open error brower
select the short net & see info
come to GUI
check where you are getting shorts
 20
1 - same layer with different nets
2-
route with required layers

########## To place buffer manually on 1000 micron wire ###########

change_selection [get_nets net_pserr_n_in]

get_lib_cells
get_lib_cells */*BUFF*_HVT
create_cell {cell_name(adil_buff1)} lib_name/cell_ref_name
create_net net_name (adil_net1)
set_cell_location -coordinates {743.279 1120.792} adil_buff1 == get coordinates
from gui (where you want to place buffer)
get_selection == select in or out pins of cell to make logical connection between
cell and net
connect_net -net net_pserr_n_in [get_selection] == make logical connection
now route net or make physical connection
select VDD pin of buffer to make PG_connnection
connect_pg_net -net VDD [get_Selection]
connect_pg_net -net VDD [get_Selection]

############## Others commands #############

### #### Enable win command on icc2 & fusion compiler #######
source ~ssb00853/.synopsys_icc2_gui/preferences.tcl ( write this command on fc or
icc2 shell )
open linux shell
cat ~ssb00853/.synopsys_icc2_gui/preferences.tcl ( write this command on linux
shell )
###################################################
#####
# To see units of inputs and outputs
report_units

# To open selected pin or port

change_selection [get_pins pad_iopad_4/PADIO]

# To get cell name and ref_name of selected pin

change_selection [get_pins pin_name]
get_selection
get_attribute [get_cells -of_objects [get_selection]] name
get_attribute [get_cells -of_objects [get_selection]] ref_name

# To get net name and dr_length

change_selection [get_pins pin_name]
 21
get_selection
get_nets -of_objects [get_selection]

change_selection [get_pins pin_name]

# To copy and paste something

double click on that "what you want to copy" & just press shift + fn + insert "where
you want to paste"

# To show or get something on gui whether it is pins , ports, nets, and all....
change_selection [get_nets net_pserr_n_in]

# To get fanout and fanin of that individual net.

report_nets net_pserr_n_in -nosplit

# Write verilog
write_verilog -exclude physical_only_cells my_route_exclude.v

# Write parasitics
write_parasitics -format spef -output my_route.spef

# For timing
parasetic model

corner "set parasetic"

"set operating condition"
mode
scenario
display timing setting
output
analysis

## Table 6 Commands for Reporting Multivoltage Information

To do this Use this command

# Report a summary of multivoltage information

report_mv_design

# Report information about the multivoltage cells

report_mv_cells

# Report information about the multivoltage library cells

report_mv_lib_cells
 22
# Report paths with multivoltage constraints and the associated multivoltage cells
report_mv_path

# Report the power domains

report_power_domains

# Check whether the specified power domains are equivalent

check_equivalent_power_domains

# Display a list of equivalent power domains

get_equivalent_power_domains

# Report the voltage areas

report_voltage_areas

### Table 7 Design Rule Commands

To do this Use this command

# Specify the minimum allowed capacitance for input ports, library cell pins, leaf
cell pins, clocks, or blocks
set_min_capacitance

# Specify the maximum allowed capacitance for input ports, library cell pins, leaf
cell pins, clocks, or blocks
set_max_capacitance

# Specify the maximum allowed signal transition time for input ports, library cell
pins, leaf cell pins, clocks, or blocks
set_max_transition

# Remove a user-specified minimum capacitance constraint

remove_min_capacitance

###################################################
#####
######### To read or set parasetic ############
EXAMPLES

the following example reads in the file.tlup tLUPlus file.

prompt> read_parasitic_tech -tlup file.tlup -layermap file.layermap \

-name critical_worst_param_1

the following example reads in the file.nxtgrd nxtgrd file.

 23
prompt> read_parasitic_tech -tlup file.nxtgrd -layermap file.layermap \
-name critical_worst_param_1

############### To set_parasetic_parameters ############

EXAMPLES
the following example sets parasitic parameters to the current con-
straint corner.

prompt> set_parasitic_parameters -early_spec file.tlup -early_temperature 25

#################### Report_parameters
#################
EXAMPLES
the following example reports the parasitic parameters for the current
corner.

prompt> report_parasitic_parameters -corners [current_corner]

#### set_operating_conditions ####

NAME
set_operating_conditions
specifies the operating conditions that are used to establish
the process number, voltage, and temperature for the current
corner of the current design.

SYNTAX
status set_operating_conditions
[-analysis_type single | bc_wc | on_chip_variation]
[-library lib]
[condition]
[-min min_condition]
[-max max_condition]
[-min_library min_lib]
[-max_library max_lib]
[-object_list objects]

#################### Set process ################

################ set_process_lebel ##############

EXAMPLES
this example shows how to set the early and late process labels to the
 24
same values for an entire design.

prompt> set_process_label wORST

this example shows how to set the early and late process labels to dif-
ferent values for an entire design.
prompt> set_process_label -late wORST -early bEST

this example shows how to give default process labels for the design,
as well as different process labels for cells from a particular refer-
ence library.

prompt> set_process_label -late wORST -early bEST

prompt> set_process_label -library mem_lib -late sLOW -early fAST

this example shows how to give default process labels for the design,
but have process labels be ignored for cells from a particular refer-
ence library.

prompt> set_process_label -late wORST -early bEST

prompt> set_process_label -library pll_lib *

################# set_process_nember ###############

EXAMPLES
this example sets the same early and late process number for an entire
design.

prompt> set_process_number 1.0

this example sets separate early and late process numbers for an entire
design.

prompt> set_process_number -late 1.5 -early 0.8

this example sets default process numbers for the design, as well as
different process numbers for cells from a particular reference
library.

prompt> set_process_number -late 1.5 -early 0.8

prompt> set_process_number -library mem_lib 1.0
###################################################
#
 25
############# Set voltage ########

########### set_voltage ##############

NAME
set_voltage
applies an operating voltage to a list of supply nets, supply
ports, cells or ports, or to the current design.
EXAMPLES
the following example sets max (worst-case) and min (best-case) voltage
values of 1.05 and 1.2 on the supply net vDD1, for the corner corner3:

prompt> set_voltage 1.05 -min 1.2 -corner corner3 -object_list [get_supply_net

vDD1]

the following example sets the max and min top-level default primary
voltage to 1.05 volts for the current corner. this value will be used
for any cells that are not powered by supply nets.

prompt> set_voltage 1.05

############### set tempreture ###########

prompt> set_temperature 125.0 -min -40.0 -corner [all_corners]

###################################################
####

############### create scenario #################

prompt> create_scenario -name m1@c1 -mode m1 -corner c1

###################################################
#####
# There are four thing when you are goin to create timing setting////
display tiing setting :----- parasetic corner mode scenario

#report_supply_nets
#report_pvt
#to get the attributes of anythings
get_attribute [get_cells i_CLK_SOURCE_PCLK] area "enter"
[to get cell from design, select object] select attributes whatever you want

# To move one for more than one file from one directory to another directory
mv powerplan.tcl floorplan.tcl scripts
 26
# To get error browser by using gui command
gui_error_browser -show

# Create a new lib

create_lib ORCA.lib -technology
/proj/testcase/28nm/sAED/sAED32nm_EDK_01252022/sAED32nm_EDK_01252022/
tech/milkyway/saed32nm_1p9m_mw.tf

# fc_shell> check_
check_3d_design check_io_placement
check_pre_place_io
check_advanced_boundary_cells check_isolation_coverage
check_pt_qor
check_boundary_cells check_legality
check_rdl_routes
check_bufferability check_legalizer_sanity
check_routability
check_bump_spacing check_libcell_pin_access
check_routes
check_busplan_constraints check_license
check_routing_corridors
check_clock_gate_library_cell_availability check_lvs
check_rp_constraints
check_clock_trees check_macro_pin_access
check_sadp_tracks
check_consistency_settings check_mib_alignment
check_safety_intent
check_design check_mib_for_pin_placement
check_scan_chain
check_design_for_clock_trunk_planning check_multibit_library
check_secondary_pg_placement_constraints
check_design_states check_mv_design check_shapes
check_duplicates check_netlist
check_stage_settings
check_equivalent_power_domains check_objects_for_push_down
check_starrc_in_design
check_error check_pg_connectivity
check_supply_equivalence
check_feedthroughs check_pg_drc
check_targeted_boundary_cells
check_finfet_grid check_pg_missing_vias
check_tcd_cells
check_floorplan_rules check_physical_constraints
check_timing
check_freeze_silicon check_pin_placement
check_topology_plans
check_hier_design check_placement_constraints
check_variants
 27
check_host_options check_pre_pin_placement
check_vclp_design

# fc_shell> get_attribute [get_blocks] -class

anchor curved_poly_rect manufacturing_shape
routing_corridor supply_net
annotation_point density_rule matching_type
routing_corridor_shape supply_port
annotation_shape design mismatch_object routing_guide
supply_set
block design_rule mismatch_type routing_rule
synchronization_element
bound drc_error mode rp_blockage
tap
bound_shape drc_error_data module rp_group
tech
bounding_box drc_error_type multisource_sink_group rtl_cell
tech_purpose
budget_clock early_data_check_record net
rtl_cell_construct terminal
budget_path_type eco_bus_buffer_pattern net_bus rtl_module
timing_arc
budget_pin edit_group net_estimation_rule
rtl_module_construct timing_path
budget_pin_constraint ems_check output_delay
rtl_statement timing_point
budget_pin_data ems_database overlap_blockage
safety_core_group topological_constraint
budget_segment ems_message parasitic_tech
safety_core_rule topology_edge
bump_region ems_rule path_group
safety_error_code_group topology_group
bump_region_pattern exception pg_region
safety_error_code_rule topology_node
bundle exception_group pin
safety_register_group topology_plan
bus_buffer_array failsafe_fsm_group pin_blockage
safety_register_rule topology_repeater
busplan_bus failsafe_fsm_rule pin_bus scan_chain
track
busplan_element fill_cell pin_constraint
scan_flop_element track_pattern
category_node geo_mask pin_guide scan_partition
utilization_config
category_tree grid placement_attraction scan_signal
variation
cell group placement_blockage scan_test_mode
via
 28
cell_array_pattern gui_annotation poly_rect scenario
via_def
cell_bus gui_object port shape
via_ladder
clock hier_tech_layer port_bus shape_pattern
via_matrix
clock_balance_group input_delay power_domain
shaping_blockage via_region
clock_group io_guide power_state_group
shaping_channel via_rule
clock_group_group io_ring power_strategy
shaping_constraint virtual_connection
clock_path keepout_margin power_switch_pattern site_array
voltage_area
comment layer pr_rule site_def
voltage_area_rule
constraint_group lib pseudo_bump site_row
voltage_area_shape
core_area lib_cell reconfiguration_multiplexer skew_group
core_block_element lib_pin retention_element_list stub_chain
corner lib_timing_arc routing_blockage supernet
fc_shell> get_attribute [get_blocks] -class

# fc_shell> list_blocks
lib orca_lib_33 /proj/pD_Training/training_2022/ssb00600/orca_lib_33 tech current
-> 0 oRCA.design may-10-15:01
+> 0 adiltrail.design may-12-16:03 current
2

############ checks after floorplan

set_attribute [get_selection ] -name physical_status -value unplaced "enter"
report_design_mismatch "enter"
reort_Design -floorplan "enter"
report_Design -enter tap"enter"
check_mv_design "enter"
check_netlist "enter"
check_timing "enter"

#################### my power_plan
########################

catch {create_net -power vDD}

catch {create_net -ground vSS}
catch {connect_pg_net -net vDD [get_pins -physical_context *vDD]}
catch {connect_pg_net -net vSS [get_pins -physical_context *vSS]}
 29
create_pg_ring_pattern ring_pattern -vertical_layer m8 -vertical_width 5 -
vertical_spacing 1 -corner_bridge true -horizontal_width 5 -horizontal_spacing 1 -
horizontal_layer m9
set_pg_strategy core_ring -pattern {{name :ring_pattern}{nets : {vDD vSS vDD
vSS vDD vSS vDD vSS}} {offset : {1 1}}} -core
compile_pg -strategies core_ring

create_pg_std_cell_conn_pattern rail_pat -layers {m1}

set_pg_strategy rail_strategy -core -pattern {{name: rail_pat} {nets: {vDD vSS}}}
set_pg_strategy_via_rule rail_via_rule -via_rule {{intersection: all}
{via_master: nIL}}
compile_pg -strategies rail_strategy

create_pg_mesh_pattern mesh_pattern -layers {{vertical_layer: m8} {width: 2.4}

{spacing: interleaving} {pitch: 6.24}} {{horizontal_layer: m9} {width: 2.4}
{spacing: interleaving} {pitch: 6.24}} }
set_pg_strategy_via_rule mesh_via_rule -via_rule { {{{strategies:
mesh_strategy} {layers: m8}} {{existing: std_conn} {layers: m1}}
{via_master: default}} {{intersection: undefined} {via_master: nIL}} }
set_pg_strategy mesh_strategy -core -pattern {{name: mesh_pattern} {nets:
{vDD vSS}}} -extension {{stop: outer_ring}}
compile_pg -strategies {mesh_strategy} -via_rule mesh_via_rule

####################################################
#
fc_shell> set_edrc_setting -check_drc {true}
fc_shell> set_edrc_setting -filter_same_net_spacing {true}
fc_shell> set_edrc_setting -check_fill {true}
fc_shell> set_edrc_setting -check_drc {false}
fc_shell> set_edrc_setting -check_drc {true}

#################### Set the technology node

################
set_technology -node 7

# To check the report of given technology node

source -v -e cts.tcl
given
set_app_options -name route.track.timing_driven -value true
set_app_options -name route.track.crosstalk_driven -value true
set_app_options -name route.global.timing_driven_-value true
set_app_options -name route.global.timing_driven-value true
set_app_options -name route.global.timing_driven -value true
set_ignored_layers -max_routing_layer m7 -min_routing_layer m2
 30
set_app_options -name route.common.global_min_layer_mode -value
allow_pin_connenction
set_app_options -name route.common.global_min_layer_mode
set_app_options -name route.common.global_max_layer_mode -value soft
set_app_options -name route.common.global_min_layer_mode -value hard
set_app_options -name time.si_enable_analysis -value true
set_app_options -name time.enable_si_timing_windows -value true
route_global
route_track
route_detail
route_auto
route_opt

report_net -connection net_name -nosplit

set enable_recovery_removal_arcs true

set timing_enable_multiple_clocks_per_reg true
set timing_remove_clock_reconvergence_pessimism true

set physopt_enable_via_res_support true

set physopt_hard_keepout_distance 5

# Set_ahfs_options -remove_effort high

set_buffer_opt_strategy -effort medium
set_case_analysis 0 scan_en

place_opt -num_cpus 2 -effort low -optimize_dft

legalize_placement -effort medium

# Verify_pg_nets

clock_opt

#foreach net {vDD} { derive_pg_connection -power_net $net -power_pin $net -

create_ports top}
#foreach net {vSS} { derive_pg_connection -ground_net $net -ground_pin $net -
create_ports top}

#route_zrt_auto
#verify_zrt_route

#route_zrt_eco -max_detail_route_iterations 5
#verify_lvs -check_open_locator -check_short_locator
 31

#insert_stdcell_filler \
-cell_without_metal "sHFILL128 sHFILL64 sHFILL3 sHFILL2 sHFILL1" \
-connect_to_power {vDD} \
-connect_to_ground {vSS}

# Save_mw_cel -overwrite
remove_scenario -all

create_scenario scan_min
source $scripts/min_operating_conditions.tcl
set_tlu_plus_files \
-max_tluplus $tluplus_max \
-min_tluplus $tluplus_min \
-tech2itf_map $tluplus_map
check_tlu_plus_files
read_sdc $sdc_file_scan
remove_ideal_network -all
set_timing_derate -min -early 0.9
set_timing_derate -min -late 1
set_timing_derate -max -early 1
set_timing_derate -max -late 1.1

create_scenario scan_max
source $scripts/max_operating_conditions.tcl
set_tlu_plus_files \
-max_tluplus $tluplus_max \
-min_tluplus $tluplus_min \
-tech2itf_map $tluplus_map
check_tlu_plus_files
read_sdc $sdc_file_scan
remove_ideal_network -all
set_timing_derate -min -early 0.9
set_timing_derate -min -late 1
set_timing_derate -max -early 1
set_timing_derate -max -late 1.1

create_scenario func_min
source $scripts/min_operating_conditions.tcl
set_tlu_plus_files \
-max_tluplus $tluplus_max \
-min_tluplus $tluplus_min \
-tech2itf_map $tluplus_map
check_tlu_plus_files
 32
read_sdc $sdc_file_func_min
remove_ideal_network -all
set_timing_derate -min -early 0.9
set_timing_derate -min -late 1
set_timing_derate -max -early 1
set_timing_derate -max -late 1.1

create_scenario func_max
source $scripts/max_operating_conditions.tcl
set_tlu_plus_files \
-max_tluplus $tluplus_max \
-min_tluplus $tluplus_min \
-tech2itf_map $tluplus_map
check_tlu_plus_files
read_sdc $sdc_file_func_max
remove_ideal_network -all
set_timing_derate -min -early 0.9
set_timing_derate -min -late 1
set_timing_derate -max -early 1
set_timing_derate -max -late 1.1

###################################################
##################### for generating report #############

## Sanity checks#####

redirect rpts/$node/congestion.rpt {report_congestion} -tee -file

redirect rpts/$node/check_legality.rpt {check_legality} -tee -file
redirect rpts/$node/report_placement.rpt {report_placement} -tee -file

## Generating reports path group wise ###

#sh mkdir rpts/$node/setup

redirect rpts/$node/timing_summary.rpt {report_global_timing -

separate_all_groups} -tee -file
redirect rpts/$node/report_constraints.rpt {report_constraints -all_violators} -tee -
file

################### Short cut keys

##################################
ctrl + shift + i == To show input nets of selected cell
ctrl + shift + o == To show output nets of selected cell
ctrl + shift + n == To show nets(in & out) of selected cell
ctrl + shift + p == To show all power nets of selected cell
 33
ctrl + k == To show preference
ctrl + r == To show properties
ctrl + s == To open option window
ctrl + shift + plus = zoom in console
ctrl + hyfun = zoom out console
ctrl + u = ruler

m == To move selected items

s == To strech slected item
c == To copy slected item
x == To pase selected item
d == To delete selected item

################### To fix max cap ###########

# Fisrt way to fix ( increse drive strength )
report_constraints -max_capacitance -all_violators -verbose
get_lib_cells -of_objects instance_name_without_pin
get_lib_cell cell_name { NBUFFX*_*VT}
size_cell inst_name buff_name

# Second way to fix ( added buffer )

change_selection [get_pins I_ORCA_TOP/I_PCI_W_MUX/U7/Y]
get_selection
get_nets -of_objects [get_Selection]
change_selection [get_pins I_ORCA_TOP/I_PCI_W_MUX/U7/Y]
insert_buffer [get_nets I_ORCA_TOP/I_PCI_W_MUX/pci_wfifo_data[3]]
NBUFFX2_HVT
########### Add buffer & remove buffer #########
# Add buffer on route
add_buffer_on_route -repeater_diatance 100 net_name -lib_cell
lib_name/buffer_name
change_selection [get_pins pi_name]
get_selection
get_nets -of_objects [get_selection] == to get pin name
report_net -connection net_name -nosplit

## To insert buffer
insert_buffer instance name with pin space cell name from library

# TO remove buffer
remove_buffer instance name

remove_eco_repeater I_ORCA_TOP/I_PCI_W_MUX/eco_cell
 34
# To get the location of eco cell
get_attribute [get_cell I_ORCA_TOP/eco_cell] bbox