ELECTRONIC DEVICE & CIRCUITS

CHAPTER - 1
ENERGY BAND STRUCTURE OF AN INSULATOR,
A SEMI CONDUCTOR AND A METAL

Conduction band Free electrons

Conduction
band
Forbidden band Eg 1eV
EG 6eV
Valence
band
Valence band holes

(b) (c)
Insulator Semiconductor Metal
(example; diamond) Example: Ge and Si Example: Al
 large forbidden band EG = 0.785 for Ge  here there
separates the filled & 1.21 eV for Si at 00K are overlapping
valence region from the  hole: absence of an valance and conduction
vacant electron in the valance band bands
condition band, e cannot is represented by a small
acquire circle, called a hole.
sufficient applied energy  Conductivity increases
hence conduction is with the increases of temp.
impossible

TRANSPORT PHENOMENA IN SEMICONDUCTORS

If a constant electric field is applied to a metal say E (Volts/m) As a result of this electrostatic force,
the electrons would be accelerated and velocity would increases indefinitely with time, were it not for
the collisions with the ions. However at each inelastic collision with an ion, an electron loses energy
and a steady state condition is reached. Where a finite value of drift speed V is attained. This drift
velocity is in the direction opposite to that of the electric filed.
The direction opposite to that of the electric filed.
The speed at a time ‘t’ between collision is at, where a = qE /m is the acceleration. Hence the average
speed V is proportional to E, Thus.
V = F
  m2/V – S (mobility of electron)
Current Density:
J = nev
= v
J  current density (current /area)
n  electron concentration (no. of electrons/m3)
v  velocity in meters per second.
  ne (charge density in coulombs /m3)

Conductivity:
 ELECTRONIC DEVICE & CIRCUITS
Also
J = nev = neE = E  equation is recognized as Ohm’s law
- where
 = en
unit: (ohm – meter)-1
with the effect of applied E – field, as a result of collision of electrons power is dissipated within the
metal and is given by
JE = E2

watts / m3
  n
For good conductor, n  1028 electrons /m3
for insulator , n  107
For semiconductor, n lies between these two values.(n 1012-14electron/m3)

Energy EG:
EG required to break a covalent bond is about 0.72 eV for Ge and 1.1 eV for silicon at room
temperature

In intrinsic semiconductor:
The no. of holes is equal to the no. of free electrons. Thermal agitation continues to produce new hole
– electron pair, whereas other hole – electrons pair disappear as a result of recombination. The hole
concentration P must be equal to the electron. The hole concentration n, so that
n = p = ni
ni  intrinsic concentration.
Donor and acceptor in purities
Donor:
 If suitable pentavalent impurities as
Conduction
antimony, phosphorus and arsenic added to band
0.01 eV
EC
intrinsic silicon or Ge, such impurities
donate excess (negative) electron carries,
Energy

ED
and therefore referred to donor or n – type
impurities. E G donor energy level
 energy band diagram of n – type EV
semiconductor.
Valence band

 if intrinsic metal is doped with n type impurities, not only does the no. of electrons increases, but
the no. of holes decreases below that which would be available in the intrinsic semiconductor. The
reason for the decreases in the no. of holes is that the larger no. of electrons present increases the
rte of recombination of electrons with holes.
Acceptor:
If trivalent impurity (boron, gallium or indium) is added to an intrinsic semiconductor, only three
of the covalent bonds can be filled and such impurities make available positive carries because they
create holes which can accept electrons. These impurities are referred to as acceptor or p – type
impurities.

 energy band diagram f p – type semiconductor

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 ELECTRONIC DEVICE & CIRCUITS

Conduction
band EC

Energy
Acceptor energy level

EG EA

EV

Valence band 0.01 eV

 a very small amount of energy is required for an electron to leave the valence band and occupy
the acceptor energy level, it follows that holes generated in the valance band by these electrons
constitute the largest no of carries in the semiconductor material.

Mass – action law:

Under thermal equilibrium(at constant temperature ,the product of positive and negative
concentrations is a constant independent of the amount of donor and acceptor impurity doping i.e.
np = ni2
the intrinsic concentration is a function of temperature
ND  equal to concentration of donor atoms.
NA  equal to concentration of acceptor atoms.
Semi conductor is electrically natural
Total positive charge = Total negative charge
i.e. ND + p = NA + n

 For an n type material

NA = 0, n > > p
n  ND or nn  ND subscript represent ‘n’ type material
concentration p of holes in n – type will be given by
2 ni2
nn pn = ni p n  …………………………(1)
ND

 For an n type material.

pp  NA
n2
np pp  ni2  n p  i
NA

 For a p type material

Pp ≈ NA
2
2 ni
 n p p p  ni  np 
NA
Here subscript represent `p` type material.

Note: If concentration of donar atoms added to a p-type semiconductor exceeds the acceptor
concentration i.e. (ND > NA), the specimen changes from p – type to n-type semiconductor. ND is
replaced by (ND – NA) in above relation (1)

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 ELECTRONIC DEVICE & CIRCUITS

Electrical properties of Ge and Si

Conductivity: Current density
J  ( n n  p p )eE  E
Here n = magnitude of free-electron (negative) concentration.
p = magnitude of hole (positive) concentration.
 = conductivity  e( n n  p p )
For pure semiconductor n = p = ni Thus
  eni (  n   p )
ni  Intrinsic concentration

Intrinsic concentration:
 EG 
 0 

2  KT
ni  AoT e 3 

EG0  energy gap at 0 o k in eVs , K  Boltzman`s constant in eV /oK.

Ao  constant independent of temp

Energy Gap: EG depends on temperature.

For Si, EG(T) = 1.21 – 3.60 × 10-4 T
For Ge, EG (T) = 0.785 – 2.23 × 10-4 T

Property Ge Si
Atomic number……….. 32 14
EG0, eV, at 00K………….. 0.785 1.21
EG, eV, at 3000K ……….. 0.72 1.1
Ni at 3000K, cm-3………. 2.5×1013 1.5×1010
0
Intrinsic resistivity at 300 K,Ω- 45 230, 000
cm
μn, cm2/V-s at 3000K………. 3,800 1,300
2 0
μp, cm /V-s at 300 K…….. 1,800 500
Dn, cm2/s = μnVT……….. 99 34
Dp, cm2/s = μpVT…………… 47 13
Properties of germanium and silicon

Mobility:
μn > μp
Because movement of free electron considered is movement of conduction band electron, while
movement of hole is considered as movement of valance band electron. Thus mobility of
electrons is greater than the mobility of holes.

up to 100-400oK
µ varies as T-m where m = 2.5 (2.7) m = 1.66 (2.33)
   

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 ELECTRONIC DEVICE & CIRCUITS
electrons holes electrons holes
 
silicon Germarium

Variation with electric field:

Value of electric fields(Volt / meter) Relationship

E < 103 Constant
103 < E < 104 μn α E-1/2
4
E>10 μn α E-1
And for the higher field ie E > 104V/cm, carrier speed approaches the constant value of 107 Cm/s.

HALL EFFECT
if a specimen(carrying a current I, metal or Y 2
semiconductor) is placed in a transverse magnetic field
B, and electric field E is induced in the direction
d
perpendicular to both I and B, this is Hall effect.
I
w
* Hall effect is used to determine to type of x
1
semiconductor, to find the carrier concentration, B
Semiconductor
Z
conductivity (σ) and mobility (µ) can also be bar
calculated.
In equilibrium eE = BeV
E  Bv
V BJd BI
 H  BvVH  BvD  
d  w
1
Hall coeff . RH 

VH w
R H 
BI
   if  , RH are measured , then mobility
  RH
3  8 
Pr actically R H  then    RH
8  3 

Application
VH  B so hall effect is used into a magnetic field meter and hall effect is also used as Hall – effect
multiplier.

PHOTOCONDUCTORS

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 ELECTRONIC DEVICE & CIRCUITS
This is the energy diagram of a semiconductor having
Conduction band
both acceptor and donar impurities. If photons of (2)
Sufficient energy illuminate this specimen, Donar level E
D

photogeneration takes place and the following transition

are possible. Transition (1): e-h pair can be created by a (1) EG
high-energy photon, in what is called intrinsic
excitation. Transition (2), (3): a photon may excite a (3)
Acceptor level E
A
donar electron into the conduction band (2) & this may
also excite a valence electron to acceptor state (3), these Valence band
transitions are called extrinsic excitation.

 density of states in C.B. & V.B >> that of impurity states so that photoconductivity is due
principally to intrinsic excitation.

hc
* Spectral response:  c corresponding to energy gap EG is expressed as EG =

1.24
c 
EG
c  expressed in microns EG  electron volts
 If the wavelength   c , then energy of the photon is less than EG and such a photon cannot cause
a valence electron to enter the conduction band hence  c is
100
called the critical, or cutoff wavelength or long wavelength
threshold of the material. 75
For Si, EG  1.1ev andc  1.13m 
at room temp. Ge
For Ge, E G  0.72eV and c  1.73m  relative
50
Si
response %
Relative spectral response 25

* Photoconductor is frequency selective device. That means 0

0.5 1.3 1.7
0.9
photoelectric yield depends upon the frequency of the
(range of wavelengths
incident radiation. of visible light)

Commercial Photoconductive cells

* Photoconductive device with the widest application is the cadmium sulfide cell. (CdS)
* The sensitive area of this device consists of a layer of chemically deposited (CdS) which may
contain impurities like silver, antimony or indium.
* In absolute darkness, resistance  2 M  and in strong light illumination resistance  10  .
* These photoconductors are designed to dissipate safely 300 mW and can be made to handle safely
several watts. Hence CdS photoconductor can operate a relay directly with out intermediate amp.
Circuits.
* PbS cell has a peak on the sensitivity curve at 2.9 µm, hence is used for infrared detection or
infrared absorption measurements
Selenium cell is sensitive through the visible end, and particularly toward the blue end of the
spectrum.

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 ELECTRONIC DEVICE & CIRCUITS
Generation and recombination of charges
On an average the time required by the hole (electron) to exist before P
recombination is called mean life time  p ( n )
P-Po=P`(o)e-t/
p

illumination effect on minority carriers concentration (p) in an P

n-type semiconductor is as shown:-
radiation affects the majority concentration hardly at all and P-Po=P`(o)
therefore we see the behavior of minority carriers. Po Po

t` o
Recombination centres (Light (Light t

* Recombination is a process where an electron moves from the CB into turned on) turned off)

the valence band so that a mobile hole-electron pair disappear.

* Gold is extensively used as a recombination agent by semiconductor device manufactures.
* Recombination centre is working on principle of momentum conservation law.

Diffusion
In addition to conduction current, there exists non uniform concentration of particles in a
semiconductor i.e. concentration gradient exists and due to this concentration gradient the
diffusion hole current density or diffusion electron-current density exists and given by
dp
J p (amp / m 2 )  qD p
dx
dp
 vewe incorporate a  ve sign.
dx
dn
and J n (amp / m 2 )   qDn
dx

Note: When both potential gradient and a concentration gradient exist simultaneously within a
semiconductor. Then
dp dn
J P  ep p E  eD p & J n  en n E  eDn
dx dx

Einstein Relationship
D p Dn KT T
  VT  
 p n q 11600
at room temp T  300 o K
VT  0.026V ,   39 D
p holes/m3

7 Ip
Ipd+Ip

x x+dx
 ELECTRONIC DEVICE & CIRCUITS

Continuity equation
Based on the assumption that charge can neither be created nor destroyed (charge conservation
law)
p
 increase in holes per unit volume per sec ond .
t
 Po  p  1 dJ p 1 dJ p
     decrease in hole concen / per sec ond due to current I P
   q dx q dx
 p 

Minority carrier injection

p(x)

-x/Lp
p(x)=Po+P`(o)e
n=ND

p`(o)
A
radiation po
p`(x)
x=0 x
Light falls upon the end of a long x
semiconductor bar.

Figure :- Hole (minority) concentration p(x) in the bar

as a function of distance x from the end of the specimen

The statement that the minority concentration is much smaller than the majority concentration is
called
the low-level injection condition.
d 2 p p  po
 LP  ( D p p )1 / 2
dx 2 D p p
LP  diffusion length for holes LP
x / L x / L
 p`( x)  p`(0)e p  p ( x)  p o  p( x)  p 0  p`(0)e p
 we see that diffusion length Lp represents the distance into the semiconductor at which the injected
concentration falls to 1/e of its value at x = 0.
 hole diffusion current
dp
I P   AqD p
dx
Dn
 ratio of magnitude of majority to min ority diffusion current  2 for Ge
DP
Dn
and  3 for si
DP

Note:- hole drift current is negligible compared with hole diffusion current. Thus the injected
minority-carrier current, under low level injection is essentially a diffusion current.
1. Due to majority carriers only drift current is taken into account, diffusion current is negligible.
2. Due to minority carriers only diffusion current taken into account, drift current is negligible

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 ELECTRONIC DEVICE & CIRCUITS
Type of carrier Drift Diffusion
Majority √ ×
Minority × √

Built-in potential for an open-ckted step-graded junction Jn

The buit-in potential p type n type
p po
Vo  V21  VT ln
p no
Ppo  N A
2 NA ND
n
Pno  i
ND x1 x2
NAND KT N A N D V0
Vo  VT / n 2
 ln 2
ni q ni
 Vo depend upon the concentration of acceptor and donar impurities.

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 ELECTRONIC DEVICE & CIRCUITS
CHAPTER - 2

* Junction-diode characteristics

Acceptor ion Junction Donar ion

+ + + +
Hole electron
+ + + +

+ + + +

+ + + +

+ + + +

P type n type
0.5 cm

2
dV +
2 =
dx

Electric field
intensity

electrostatic pot. V.

p side Vo
v=- dx
V=0
Distance from junction

E=0
Potential energy
barrier for electron
Eo n side

p-n junction as a rectifier

reverse bias:
When no voltage is applied to the p-n junction, the potential barrier across metal ohmic contacts
the junction is as shown earlier. When a voltage V is applied to the diode,
the height of the potential barrier is increased by the amount qv. This p n
increase in barrier height serves to reduce the flow of majority carriers.
However the minority carriers, since they fall down the potential energy
hill, are uninfluenced by the increased height of the barrier. The small
+
current caused by these carriers is called reverse saturation current V
denoted by
Io. It is not possible to measure contact difference of potential directly with a voltmeter.
Expression for diode current
I = Io ( e v / VT  1) for both applied forward or reverse bias.
If V is –Ve and is large compared to VT  26 mV then
I   I o (reverse saturation current )
Io = f(T)
 = 1 for Ge and  = 2 for Si
T
VT = at T  300 o K , VT  26mV
11600
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 ELECTRONIC DEVICE & CIRCUITS
I,mA
Forward volt-amp. Charge Ge Si
100

V cut  in potential for Ge  0.2V and for Si,V  0.6V .

80
Re ason : ( I o ) Ge  1000( I o ) Si also  2 for Si
60
Logarithmic Characteristic
log I = log Io + 0.434 V/  vT at low currents log I vs V is 40
almost linear correspond to  =2. At high current diode
behaves more like a resistor than a diode and current 0 0.2 0.4 0.6 0.8
V

increases linearly rather than exponentially with applied

voltage.
Temp. dependence of VI characteristic
Reverse saturation current approximately doubles for every 10o rise in temp. if Io = I01 at T =T1
then at temp T, Io is
I O (T )  I 01  2 (T T1 ) / 10 , for 10C change is Temp, I0 changes by approximately 6 to 7%
* For either silicon or Ge at room temperature,
dV
 2.5mV / o C in order to maintain a constant value of I.
dT
Diode resistance
For VF = 0.8 V at IF = 10 mA, RF = 80  and VR = 50 V maintaining IR = 0.1 µA, RR = 500 M.
dV
For small-signal operation, the dynamic or incremental resistance r, r 
dt

dI I e v / VT I  Io
 o 
dV VT VT
VT
r 
I
I  I o for forward current I  26mA at room temperature r  1 ,VT  26mV
Piecewise linear diode characteristic:-
For a current swing from cutoff to 10 mA with a
germanium diode, reasonable value are Slope 1
Rf
V  0.2 V , R f  20 
and for a Si diode V  0.6V , R f  15
Thus for small signal, function resistance predominant.

Space-charge or transition capacitance : CT V v

Comes when there is reverse bias condition
dQ
CT 
dv

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 ELECTRONIC DEVICE & CIRCUITS
Diffusion Capacitance
This comes into play in Forward Bias condition.
dQ dI  I
CD    g  
dV dV r VT
 C DI diffusion capacitance is proportional to the current I.
  rC D
Note: The dynamic diffusion capacitance C`D depends upon how the input voltage varies
with time.
For sinusoidal input at low frequencies   1.
1
C `D   g +
2 I z

For high frequencies C`D decreases with increasing +

v
frequency and is given by RL VZ

1/ 2
  
C `D    g if   1
 2 
Junction diode switching time:- I

Breakdown diodes ZV
Diodes which are designed with adequate power V
I
dissipation capabilities to operate in the break-down
ZK

region may be employed as voltage-reference or

constant-voltage devices. I
Z

Such diodes are known as avalanche, breakdown or

zener diodes.
Two phenomenon of breakdown
Avalanche breakdown: each new carrier, may in turn, produce additional carriers through
collision and the action of disrupting bonds. This cumulative process is referred to as avalanche
multiplication.
Zener breakdown: direct rupture of covalent bond takes place because of the existence of electric
field at the junction, a sufficiently strong force may be exerted on a bound electron by the field to
tear it out of its covalent bond. New hole-electron pair is generated and it increases the reverse
current.
* Zener breakdown occurs at a field of 2×107 V/m. For heavily doped diodes this value is reached
below 6V.
* For lightly doped diodes, the breakdown voltage is higher and avalanche multiplication is
predominant effect.
Temp. sensitivity:
 if the reference voltage is above 6V, where the dominant breakdown is avalanche breakdown.
Them temperature coefficient (% change in reference voltage per degree centigrade change in
diode temperature) is positive.
However below 6V, where true zener breakdown is involved, the temp. coefficient is negative
Additional reference diodes:
Zener diodes are available as low as 2V, below this voltage, it is customary, for reference and
regulating purposes, to use diode in forward direction.
As at low voltages zener diodes have large value of dynamic resistance.

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 ELECTRONIC DEVICE & CIRCUITS
 When a high – voltage reference is required, it is usually advantageous to use two or more diodes
in series rather than a single diode. The combination will allow higher voltage, higher dissipation,
lower temperature coefficient and lower dynamic resistance.
I
Tunnel diode I
(V I ) p p
o
Highly doped diode  barrier width  100 A
p

Forward
current
I
VI characteristic
* Heavily doped diode
I
* very thin depletion layer V

V
* (Vp, Ip) which is in tunneling region is not a very Reverse voltage V V p v
V F

Reverse
current
Forward voltage
sensitive function of temp.
* (Vv, Iv) which is affected by the injection current
is quite temp. sensitive.
* tunnel diode is an excellent conductor in the reverse direction.
* In the forward direction it exhibits a negative resistance characteristics between the peak current IP
and minimum value Iv called valley current. R S
L s

* For currents whose values are between Iv and

Ip, the curve is triple-valued, because each
current can be obtained at three different C
-R n

applied voltages. This feature makes it useful

in pulse and digital circitry.
Ip = 10mA, - Rn = -30  , Rs = 1  , Ls = 5nH, c = 20pF
Application
* high speed switch
* high frequency oscillator
* The most commonly available tunnel diodes are made from Ge or GaAs.
It is difficult to have a high ratio of peak to valley current Ip/Iv. with Si
Advantages:
Low cost, low noise simplicity, high speed environmental immunity and low power
Disadvantage:
* Low output-voltage swing
* Two-terminal device because the tunnel diode is a two terminal device, there is no isolation
between input and output and this leads to serious circuits design difficulties.

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ANALOG ELECTRONICS
DIODE CLIPPERS AND CLAMPERS
A variety of series and parallel clippers with the resulting output for the sinusoidal input are
provided in figure below.

Simple Series Clippers (Ideal diodes)

POSITIVE NEGATIVE

Biased Series Clippers (Ideal diodes)

Simple Parallel Clippers (Ideal Diodes)

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 ELECTRONIC DEVICE & CIRCUITS
Biased Parallel Clippers (Ideal Diodes)

Clampers: A number of clamping circuits and their effect on the input signal are shown below.

Clamping circuit with ideal diodes ( (5  5 RC  T / 2)

Clamping network with a sinusoidal input.

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Salient features of zener, avalanche diode

Doping in avalanche diode  doping in PN junction. Doping in avalanche < doping-in zener
If doping is increased, |Vz| is decreased
I
Temp. effect on zener characteristics
I

-V2 -V1 Vz1

V

-Vz2 -Vz1
V

ordinary avalanche Zener

PN junction diode diode
diode maximum
T2 T=T1 (doping is low)
T1>T2
|Vz1| < |Vz2|

Voltage regulator using zener diode

(V  V ) | Vz | .... condition for regulation
Design of voltage regulator ckt.
I Rs
+ +

V V RL
Vo=Vz
Iz
IL
- -
(V+ V ) |Vz|.... condition for regulation
Case 1:
I R1 RL(max)
+ +

RL
Vi(max) Vo=Vz

IL
- -
Iz(max) IL(min)

Vi (max)  V z
Rmin  R1 
I z (max)  I L (min)
Case 2: I R2 RL(min)
+ +

Vi(min) RL
Vo=Vz

IL
- -
Iz(min) IL(max)

Vi (min)  V z
Rmax  R2 
I z (min)  I L (max)
Practically Iz(min) = 0.2 of Iz (rated), Iz(max) = 0.8 Iz (rated)

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 ELECTRONIC DEVICE & CIRCUITS

Regulated Power Supplies

HW FW. Bridge HW
Rectifier (3  )
No. of 1 2 4 3 6
Diodes.
Secondary Vm 2Vm Vm Vm Vm
Voltage
PIV Vm 2Vm Vm Vm Vm
Vdc Vm 2Vm 2Vm 0.827 0.955
   Vm Vm
r 1.21 0.482 0.482 0.17 0.055
 max 40.6 81.2 81.2 96.5 99.5%
fo Fi 2fi 2fi 3fi 6fi

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CHAPTER 3
BIPOLAR JUNCTION TRANSISTOR O/p C
Current relationship: Junction J 2

IE = IB + IC
IB  0
 IC  IE but IC < IE B

Doping, width, depletion layer and biasing:

(a) doping: I/p
E……….max doping (emits majority charge carriers) Junction J 1

E
B………most lightly (to minimize recombination) E B C
C………relatively less in comparison to emitter regrion
(b) width: N P N
B………width is minimum (to minimize heat dissipation per
unit surface area)
E  medium width.
(c) depletion layer: if RB increased d increases also if doping increased `d` decreases if FB is
increased, `d` almost becomes zero. N J 1P J N 2

d1<d2 << d3 <d4

here J1 (FB) and J2 (RB)
Mode of J1(B – E) J2(C – B) Applications
operations d 1 d d 2 d4 3
Activate region FB RB as an amplifier
Saturation FB FB as an electronic
region switch
Cut-off Region RB RB in digital ckt.
Reverse active RB FB as an amplifier
mode with
Or inverted voltage and
Mode current
gain to be low
Various configuration and their characteristics: I E E C IC

CB Configuration: + N N +
IE  ve Ic  +ve VEB  ve VCB  ve P +
V V
Input characteristics:
EB
CB

+
IE vs VEB (with temp as the parameter)
V B
rin = Zin = |T cons tan t
I
V T >T 2 1

I I E T 2
T1
V
IE = I Eo (e EB / VT  1)
I

VEB
Transfer Characteristics:
IC vs IE with VCB as parameter VEB
Note:- Collector junction is reverse biased hence no effect on
characteristic takes place on varying VCB.

18
 ELECTRONIC DEVICE & CIRCUITS
I
 ac    |V cons tan t IC
I E CB VCB
=5v, 10v, 15v
I C  I E (approximate result )
I C  I E  I CO (exact result ) IC
IE
I CO  I CBO (leakage current )
Output Characteristics:
IC  IEIC remains almost constant with VCB (RB)
IE
VCB
Rout = Zout = | I cons tan t
I C E
IC

15 mA active
region
Saturation IC
region VCB 10 mA

IE=5 mA
CE configuration
IE=0

(FB)
Input Characteristics: ICO=ICBO

VBE (RB)VCB
Zin = rin = T cons tan t
Cutoff
I B
(medium value of zin) IC
C
IB = IBO (eVBE / VT  1) +

B IB
+ VCE

VBE

IB
T2>T1
T2
T1
Transfer Characteristics:
I
 dc  C
I B VCE  cons tan t IB
VBE
I C
 dc  IC
I B VCE  cons tan t VBE
15V
  50  300
10V

 VCE=5V
1
IC

 IB
1 
IB

19
 ELECTRONIC DEVICE & CIRCUITS

Output Characteristics:
T  I B 
VCE  I C  IC
II IB
I B  I C  I 40 A

Re gion 30 A

I  saturation region 20 A

II  active region. 10 A
active region I C   I B  (1   ) I CO 0 A

V CEsat VCE
ICO = ICEO

I CO  I CEO current between collector and emitter when third ter min al base is open. For different modes
of operation of BJT (NPN), polarities of VBE and VCB
J 1  RB  VBE  Ve
1. Cut off region: J 2  RB  VCB  Ve
VCE almost equal to VCC

J 1  FB  VBE  Ve
J 2  FB  VCB  Ve
2. Saturation region: VCE  0.2V  VCE ( sat )
VBE ( sat )  0.7V
I C is max imum
3. Active region (Forward Mode):
J 1  FB  VBE  Ve
J 2  RB  VCB  Ve

4. Reverse active region:

J 1  RB  VBE  Ve
J 2  FB  VCB  Ve
For numerical point of view:
VCE (sat) = 0.2 V
VBE (active) = 0.7 V
VBE (sat) = 0.8 V
Dc equivalent circuits of BJT in various modes
Forward Active Mode: For Saturation Region:
IB IC C IB C
B IC
B
VBE
(active) + +
IB
VBE(sat) VCE(sat)

E
20 E
 ELECTRONIC DEVICE & CIRCUITS
Reverse Active Mode: IB
IC
V =0.7V
Early Effect:- Because base is lightly doped with compare to B
+ BC

C
collector, when in active region, collector junction is in
reverse bias, space charge region (depletion layer) increases,
which is increase
rease more towards to base. That results in
I
reducing of base width. Thus base width modulation due to
R B

reverse voltage at Jc is called early effect. E

Result of early effect:-
(1)  increases with |VCB|  increases
(2) IE increases, IC increases & IB decreases
(3) Completely disappearance of base cause breakdown, called punch through or reach through.
Due to this effect input characteristic shifts down words as |VCB| increase.

Darlington emitter follower

(CC-CC)
6
IE2 = mA
1 R1=?
I E2 VB 1 =50
IB2 = IE1 =50
(  2  1) 2

I E1 I E2
IB1 = = R2=
8

(  2  1) ( 1  1)( 2  1)
= 2.31 µA RE=1K
VB = .7 + .7 + 6V
= 7.4 V
12  7.4
R1 =  2m
I B1

(1) Input Ri → very high, AI is much greater than Single stage

(2) Voltage gain is less than single CC.
(3) Ro may be greater or smaller
(4) Draw back : leakage current of 1st stage is amplified by second stage.

1  h 
fe
2

A1 
1  hoe h fe Re
1  h  R
fe
2
e
Z in  Z in 1
1  h h R 
oe fe e

 Input impedance is very high

 Current gain is very high
 Darlington connection of three or more stages
is generally practically not used because of the
possibility of leakage current being amplified.
ximum reverse biasing voltage which can be applied Before breakdown between B & C
Maximum
with emitter open is represented by BVCBD.
Collector to emitter break down with base open circuited is represented by BVCEO

21
 ELECTRONIC DEVICE & CIRCUITS
1
BVCEO = BVCBO n
h ff
Generally
BVCEO =0 .52 BVCBO 10V
Exp. 1
VBESat = 0.8V,  = 100 RC
VCESat = 0.2
Find Rmin for saturation:-
I 4.2 200K
(IB)min = C IC =  100 = 2.1 mA 5
h fE 200  10 3
9.8 14
RC =  10 3  K  4.67 K
2. 1 3
+12V
Exp. 2
α = .98, VBE = 0.7V 3.3K
IE = - 2mA
VC
Ic = - α IE = .98×2 = 1.96mA I IC
 .98 VB
β=   49
1   .02 IR 2mA
I1
I 1.96  100 20K
IB = C   40 A Re=100
 49
VB = .7 + 2 × 10-3 × 100 = .9 V
VC = 12 – 3.3 × 1.96
= 5.5
.9 9 1.7
I1 = mA I = I1 + IB = + 0.4 mA = mA
20 20 20
5.5  .9
R1 =  20 K
1.7
4.6
=  20 K = 50 K 
17

Exp. 3 VCC
α1 = 0.98, α2 = .96, VCC = 24V RC = 120Ω
Ie2 = - 100 mA find various currents RC
IC2 = αIe2 = 192 mA
IC1
IB2 = 8mA = IE1
IC1 = α1IE1 = .98 × 8
IB1 IC2
IB1 = IE1 – IC1 Q1

IE1 IB2
IE2

22
 ELECTRONIC DEVICE & CIRCUITS

Transistor Biasing
Fixed bias circuit
VCC VCC
IC RC
VCC  VBE VCC
IB = 
Rb Rb Rb RC
Stability problem:-
(1) w.r.t. to β
(2) w.r.t. to ICO VO
VBE Vi

VCC VCE
VCC VCC
Self bias or empire bias:-
R1 RC RC
Rb = R1 | | R2
R2 Rb
V= .VCC
R1  R2
Vi R2 V
RE Re

Thermistor & Senistor compensation:-

-VCC
-
ST +

- RT
-
+ +
Bias Compensation for VBE (Si)

Bias Compensation for ICO (Ge)

23
 ELECTRONIC DEVICE & CIRCUITS
VCC
VCC
RC
R1

IO D
V

Thermistor compensation for

VO VDD increase in IC with T

Thermal Runaway:-
VCC
Across when VCE >
2
I C R
Satiability constant S 1  b
I CO Re
I 1
S ' C 
I CO Re
I I C! S 2
S " C 
 1 (1   2 )
For more stable circuit
Rb
 small
Re
  Greater

Biasing and Stabilization:

Biasing: Means fixing of Q point in such a way that it is almost in the middle portion of the o/p
characteristics of the transistor. Therefore when ac voltage is superimposed on it, its positive half and
negative half remain in the linear portion of output characteristics of the device hence the amplification
will be linear and o/p will be distortionless.

24
 ELECTRONIC DEVICE & CIRCUITS
Stablisation: IC= f(ICO, , IB) ICO is temp sensitive IB is VBE dependent
Once the operating point has been fixed, it has to be stablised against the variation in leakage current
ICO or the temp. T
(2)  of the transistor (3) The input base current IB or the output voltage VBE
Dc and Ac load line
zero signal analysis VCC= ICRL + VCE
(dc analysis) ICRL= -VCE+ VCC
 1  V
IC=  VCE  CC
 RL  RL
 y  mx  c

Small signal analysis:

 1  V
I C   VCE  CC
 Rac  Rac
Rac  R L ||RL(<RL)
Rac – ac or dynamic load line slope > slope of dc load
line
Slope of dc load line |m1| = 1/Rdc
Slope of ac load line |m2| = 1/Rac
Rac <Rdc | m2 | | m1 |
Slope of dynamic or ac load line > slope of dc load line
Stablisation:
Once the Q point has been fixed, it has to be stablised against the variation in 3 parameters, ICO,  and
VBE,
Stability factors:
 Ic I I C
|   cons tan t S   c | I CO  cons tan t SV  | ICO  cons tan t
S= I CO  VBE
V BE  cons tan t V BE  cons tan t   cons tan t
 Minimum value of any stability factor is always 1.
 Higher the stability factor, poor is the stability of ckt. With respect to that particular parameter.
 The most sensitive stability factor is S with respect to Ico, since it is temp. dependent.
General expression of S
 
 
I c 1  
S 
I CO  I 
1  
 I C 

25
 ELECTRONIC DEVICE & CIRCUITS

Fixed Biasing

 I B
 S  1   as 0
I C

Collector to Base Biasing

1    Rc 
S  x  
1 x  Rb  Rc 
S<1+

Potential divider biasing or self biasing or four resistor biasing

I  x 
 S  c  1    
I co x 
 R   R R 
Where  x  1  b   Rb  1. 2 
 Re   R1  R2 
This circuit has best thermal stability among the three biasing circuits.

I C I c. S
 S 
  1   
I c  S
 SV 
VBE 1   Rb  Re 
I c I c1 S 2
Modified value of S   
  1 (1   2 )

Current mirror circuits

A current circuit provides a constant current and is used primarily in integrated circuits. This circuit
is particularly suited to IC manufacture since the circuits requires that the transistors used have
identical base- emitter voltage drops and identical results best achieved when transistors
identi values of beta-results
are formed at the same time in IC manufacture.

26
 ELECTRONIC DEVICE & CIRCUITS
Current mirror circuit
The currents Ix and I can be obtained using the circuit currents. We assume that the emitter current (IE)
for both transistors is the same (Q1 and Q2 being
fabricated near each other on the same chip). The two
transistors base currents are then approximately.
I I
IB  E  E
 1 
the collector current of each transistor is then I c  I E
Finally, the current through resistor Rx, Ix is
2I I 2I  2
Ix  IE  E  E  E  I  IE
    E
In summary, the constant current provided at the collector
of Q2 mirrors that of Q1.
V  VBE
 I x  cc
Rx

27
 ELECTRONIC DEVICE & CIRCUITS
CHAPTER - 4
IB
I
Field Effect Transistors (FETs) +
V =0.7V BC
C

FET Vs BJT B C
* BJT is a current-controlled device while FET is a
voltage controlled device
* BJT transistor is a bipolar device while FET is I R B

unipolar device.
E
* Input impedance of FET is at a level of 1 to several
hundred megaohms. If far exceeds the typical input resistance levels of the BJT transistor
configurations- a very important characteristic in the design of linear ac amplifier systems.
* BJTs have much higher sensitivity to changes in the applied signal. In general, FETs are more
temperature stable than BJTs and they are also usually smaller in construction than BJTs, making
them particularly suitable for IC chips.
* Voltage gain of FET is low so that FET has lower value of gain-BW product. Hence its operation

Junction field Transistors (JFET) Insulated Gate FET(IGFET)

(works in depletion mode) Metal Oxide Semiconductor FET (MOSFET)
Generally used in digital electronics
Generally used in
analog electronics
Work in the Depletion type may
enhancement mode work cither in depletion
mode or in enhancement mode

N-ch P-ch
(N-MOS) (P-MOS) N-ch P-ch
(N-MOS) (P-MOS)
is limited to relatively lower frequencies compared to that of the BJT amplifier.
IG
D
JFET: Two types: n channel and p
+
P

channel. It consists of a semiconductor

block which is n type for n channel and S
n channel
Drain

p type for p channel. On both sides of D I G

I I
n block acceptor impurities p are S
G P
+
D

heavily doped by alloying or by V GG

diffusion. The doped region is called

the gate. Ohmic contacts are attached
S
to the either ends of the n-block. One V DD Symbol for n-channel FET
end is called Source and other is called Drain. The np+ region between source and gate is reverse
biased. In the vicinity of np junction there is diffusion of majority carriers, electrons and holes
from p+ leaving uncovered immobile positive and negative ions. When RB is applied, the space
charge width increases uncovering more ions, until the space charge region from the two ends
28
 ELECTRONIC DEVICE & CIRCUITS
meet. The n type region between the two p+ gates is called n channel and when a positive voltage
is applied between drain and source, there is a current flow in the channel of majority carriers,
(electrons). When a reverse bias is applied between the gate and source, construction of the
channel takes place by widening of the space charge depletion region controlling the flow of
electrons to the drain.

Note: For a P channel FET, the bar is a P type pinchoff or saturation

semiconductor and doping by n donor ID
ohmic Drain to gate
region reverse breakdown
impurity. region
region
4
Characteristics of n-channel FET VPO
VGS=0V

FET transfer characteristics 3 -0.4V

-0.8V
IDSS ID 2

1 -1.0V
6

5 10 15 20 VDS

2mA

VGS -3 -2 -1
FET Parameters:
FET Small Signal model:-
i D  f (vGS , v DS )
i D i D G ID D
i D  vGS  v DS +
vGS v DS
VDS VGS
Vgs gmvGS rd
1
id  g m v gs  v ds -
rd S
S
gm  Trans conductance, rd
μ = gm × rd  Amplification factor
1. Drain resistance rd
V
rd  DS
I D VGS cons tan t
Output resistance of FET and evaluated in constant drain current region of VDS –ID curve. It is of
the order of 10 to 30 k s.
2. Transconductance gm:
I
gm  D
VGS V PS cons tan t
It will be of the order of 2k to 6k micromhos.
3. Amplification Factor µ.
V I V
µ = gmrd = rd  DS  D  DS
I D VGS VGS
µ ranges from 40 to 100.

29
 ELECTRONIC DEVICE & CIRCUITS
VGS
4. Input resistance = rgs =
I GSS
It is of the order of hundreds of megaohms. FET is high input impedance device.
-VDD
D id V01
RD
id-gmv gs
ID gmvgs rd
V01
D
Vi G s rd
S Vo2
V02
vi RS
RS
N

CS Amplifier with Vn bypass source resistance

Rd
AV  
rd  R g  (   1) Rs
Ro  rd  (   1) Rs

CD Amplifier
RS
AV 
rd  Rd  (   1) Rs
rd  Rd
RO 
 1

Prob. 1

id
G +
rds RD VO
RG Vi -
Vi
RS CS RG - vgs
+
S
RD = 3kΩ, RG = 500kΩ,
µ = 60 rdS = 30kΩ
AV = ?
Rd
VO    v gs v gs  v i
rds  R d
Rd
AV   
rds  R d

30
 ELECTRONIC DEVICE & CIRCUITS
id μR g
Ai   very large.
i i rds  R d
VDD
RL i1 R F
RF D iL
VO i2
rds Rd
Vi
Vi - vgs
+
V DD

Rd
vO
Vi
Rg
RS

Biasing of FETs
Self bias circuit
KVL for the gate source loop is
 VGS
VGS  i D Rs or i D 
Rs
This is the equation of a straight line called bias line.
If slope of bias line OA is reduced to O’A’, we note the
variation in quiescent current value is very much
reduced. For this we have to add a positive voltage to
VGS by means of a battery or by the resistor combination as for a BJT.
VGG  i D Rs
VGG  VGs
iD 
Rs
FET biasing circuit and its equivalent

31
 ELECTRONIC DEVICE & CIRCUITS

R2
VGG = VDD
R1  R2

R1 R2
RG  R1 || R2 
R1  R2
KVL for gate loop is -VGG+ VGs +iDRs =0
KVL for drain source loop
 VDD  RD i D  VDs  i D RS  0
Note:- The circuit can not be used with enhancement MOSFET as the
gate is reverse biased. The circuit used is as follows A positive bias is
given to the gate by Rf from VDD. As no current is drawn by gate VGS=
VDS

MOSFET
The real name of MOSFET is IGFET i.e. insulated gate field effect transistor. The gate is
insulated from the
substrate by an oxide D

layer. p
substrate
n
+
+
In this transistor the D
Diffused V
G Al - DD B
metal and channel with n channel G
+
+
+
depletion
region B
dielectric in between -
S n +

S
forms a parallel plate V +
GS
(a) n channel MOSFET
depletion type symbol
capacitor giving rise to Sio dielectric
a high input impedance
2

(a) n channel MOSFET

of 1010 to 1015 ohms
and is the major difference from JFET. There are two types of MOSFET, enhancement and
depletion type.
When a negative voltage VGS is applied to the conducting terminal of the capacitor
capaci positive
charges are induced in the channel, the other side of the capacitor. These positive charges
neutralize the electrons in the n channel and reduce the charge carriers. This reduces the drain
current. The depletion region is wider as in JFET near the drain than that near the source, due to
voltage drop by the drain current. Unlike JFET when gate is reverse biased, in MOSFET there is

32
 ELECTRONIC DEVICE & CIRCUITS
no pn+ junction. As the carriers, electrons, in n channel are depleted this is called depletion type
MOSFET.
The same MOSFET can be made enhancement type when a positive voltage is applied to the gate.
Negative charges are induced in the channel adding to the electron, charge carriers in the channel,
this enhances the drain current.
ID
ID
Enhancement
+ 2V
10 Depletion
+ 1V

VGS=0 V DSS=20V
-1V 5 IDSS
5
mA -2V

0 VDS
10 20 30 -3 -2 -1 1 2
Depletion MOSFET characteristic Depletion MOSFET Transfer characteristics

Enhancement MOSFET
No channel is diffused in the P substrate. So when a positive voltage is applied to the gate, the
minority carriers in the P substrate, electrons are drawn towards the dielectric and this forms an
effective channel. As the positive voltage on the gate is increased, conductivity increases leading
to higher drain current as the negative charge carriers Circuit Symbol
are increased. D D
Low vt is useful because of.
(1) use of small power supply voltage
(2) Compatible with BJT. G G
(3) higher packing density
(4) Smaller switching time
Methods to Allow low vT. S S
(1) Crystal utilized with orientation <100> Depletion type Enhancement
(2) A layer of Si3 N4 + SiO2 is used instead of SiO2 P channel
(3) Polycrystalline Si doped with B, is used as gate electrode instead of Al.
Al G(+) D D

Sio2
Substrate
n n channel n G

p substrate S
(Symbol)

(Positive Gate Voltage greater ID

than VT is applied)
ID mA
ohmic Saturation
pinch off 6
+4
4
+3
VDSS 2
+2
VGS
mA +1 -2 -1 1 2 3 4
33 0 VDS
Threshold
voltage VT
5 10 15
(Enhancement NMOS characteristics) (Transfer characteristics)
 ELECTRONIC DEVICE & CIRCUITS

* We note from the transfer characteristics that a threshold voltage VGST is required for drain current
to flow. Without gate voltage, a small current of nanoampere ID flows in the drain.
* The electric field produced by the gate voltage is largest near the source and least near the drain.
* For pinch off VDS = VGS - VT
VT  2 to 4V.
* Typical values for JFET and MOSFET.

JEET MOSFET
Input Resistance rgs > 10 9  > 10 13 
Transconductance 1K to 25K 1K to 20K
gm(µ mho)
Drain resistance 0.1 M to 1M 1K to 50K
rd (ohm)
Reverse current 0.1 to 10nA 0.1 to 10pA
IGSS
Capacitance 1 to 4 pF 0.005 to 1 pF
C(G to D)

Various relationship in FETs

Pinch off voltage: -ve
p+ type of gate
eN D a 2
Vp  o r
2 N-region
2a
2a  width of channel without any gate bias. S 2b D

W
2b  Width of channel after bias.
G
  V 1 / 2 
b  a 1   GS   When VGS  0, b  a L

  VP  
If w  channel dimension perpendicular to b direction
Then drain current

34
 ELECTRONIC DEVICE & CIRCUITS
V
I D  AqN D  n E  2bwq N D  n DS
L
Substituting `b`
2awqN D  n   VGS  
1/ 2

ID  1    VDS
L   V P  
The ON resis tan ce rd , ON
(rd  Vds / I d )
L
rd , ON  for VGS  0
2awqN D  n
Transfer Characteristics
In amplifier applications, the FET is almost used in the region beyond pinch-off (also called the
constant-saturation region)
2
 V 
I DS  I DSS 1  GS 
 VP 

Transconductance:
I
g m  DS
VGS
I DS  V   1 
 I DSS 21  GS  
VGS  VP  V P 
 V   2 I DSS
g m  g mo 1  GS  g mo 
 VP  VP
From the transfer characteristic we have
VGS I DS
1 
VP I DSS
I DS
g m  g mo
I DSS
 2 I DSS I DS
gm 
VP I DSS
2
gm  I DS .I DSS
VP

35
 ELECTRONIC DEVICE & CIRCUITS
For Enhancement Type MOSFET:
For PMOS
Condition for triode. For N MOS
(1) VGS  Vt (1) VGS  Vt
(2) VDG  |Vt| VDS  VGS – Vt (2) VDG  |Vt| VDS  VGS – Vt
Saturation region Saturation region
(1) VGS  Vt (1) VGS  Vt
(2) VDG  |Vt|  VDS  VGS – Vt (2) VDG  |Vt|  VDS  VGS – Vt

MOSFET
Capacitance per unit gate area
ε
C ox  ox
t ox
ε ox = Permittivity
tox = oxide thickness

1 W
ID  k' (VGS  Vt ) 2 Saturation region
2 L

W 1 2 
ID  K '  (VGS  Vt )VDS  V DS  Triode region
L  2
W
Where kn1 = μn cox Aspect ratio
L

2
Linea region VDS  Negligible

Triode
Saturation
-Vt
IDS VDS<VGS
i near
nl Pinch off channel
No
VGS>Vt
Linear

VDS=VGS -Vt VDS

For n channel MOSFET
VDS sat = VGS - VT
For VGS < VT, the drain current of an enhancement type MOSFET is 0 mA.
For levels of VGS > VT, the drain current is related to the applied gate-to-source voltage by the
following
nonlinear relationship
ID = K(VGS – VT)2
K  constant that is a function of the construction of the device, the value of K can be determined from
36
 ELECTRONIC DEVICES & CIRCUITS
I D ( on)
K
(VGS ( on )  VT ) 2
ID(on) and VGS(on) are the values for each at a particular point on the characteristics of the device.

CHAPTER - 5
OPERATIONAL AMPLIFIERS
Basic operational amplifier:
Ideal op-amp characteristics:
(i) Ri = 
(ii) Ro = 0
(iii) Av = - 
(iv) BW= 
(v) Vo=0 when V1 = V2 independent of the
magnitude of V1
(vi) Characteristics do not drift with
temperature.
Differential I/p
op amp , the resulting difference signal is the difference between
When separate i/p are applied to the op-amp
the two i/ps
Vd  Vi1  Vi2
Common inputs
When both i/p signals are the same, a common signal element due to the two i/ps can be defined as the
average of the sum of the two signals.

37
 ELECTRONIC DEVICES & CIRCUITS
1
Ve  Vi1  Vi 2 
2
Output voltage
V0  Ad Vd  AcVc
Vd – difference voltage
Vc – common voltage
Ad – differential gain of the amplifier
Ac = common-node node gain of the amplifier
CMRR: Having obtained Ad and Ac , we can now calculate a value for the CMRR.
A A
CMRR= d In logarithmic terms CMRR (log) =20 log10 d (dB)
Ac Ac
 The signal components of opposite polarity will appear greatly amplified at the o/p, where as the
common-mode gain Ac is very
signal components that are in phase will mostly cancel out so that common
small. Ideally CMRR is  , but the larger the value of CMRR, the better the circuit operation.
 AV 
V0  Ad Vd  AcVc  Ad Vd 1  c c 
 Ad Vd 
 1 Vc 
V0  Ad Vd 1  
 CMRR Vd 

Practical op-amp. Circuits

Unity follower Summing amplifier

 Rf Rf Rf 
V0   V1  V2  V3 
 R1 R2 R3 
Integrator
Integrator:-
1
V0 t   V1 t dt
RC 

38
 ELECTRONIC DEVICES & CIRCUITS
More than one input may be applied to an integrator like

 1 1 1 
V0 t           
R2 C  R3 C 
v1 t dt  v 2 t dt  v 3 t dt 
 R1C 
Differentiator
dv t 
V0 t    RC i
dt

Op-amp specifications-Dc offset parameters

Input offset voltage V10:
Manufacturer’s specification sheet provides a value of V10
for the op-amp. The o/p offset voltage is then determined by
the i/p offset voltage and the gain of the amplifier.
Consider the circuit
  Rf  
  1  v10 
  R1  

Output offset voltage due to i/p offset current I10:

Op-amp. Connection showing

Input bias currents

V0 offset due to I10   I 10 R f

Slew Rate: Op-amp’s
amp’s ability to handle varying signal: is Slew Rate
Slew Rate= maximum rate at which amplifier o/p can change in volts per microsecond (V/μs)
V0
SR  V / s
t

Maximum signal frequency

amp may operate at depends on both the band width (Bw) and slew rate (SR)
That an op-amp
Parameters of the op-amp.
amp. For a sinusoidal signal.
39
 ELECTRONIC DEVICES & CIRCUITS
V0  k sin 2ft 
Signal maximum rate of change=2fk-v/s
change=2
To prevent distortion at the o/p , the rate of change must also be less than the slew rate that is
2fk  SR
SR
k  SR f  Hz
2k
SR
 rad / s f is also limited by unity gain BW.
k

WAVEFORM GENERATORS
Square –wave generator

Output and capacitor voltage waveform

 R 
   3
 of the o/p is fed back to the noninverting i/p terminal.
R
 2  R 3 

1  
T  2 R ' C ln 
1  
The circuit is also called a stable multivibrator because it has two quasistable states. The o/p remains in
one of these states for a time T1 and then abruptly changes to the second state for a time T2 and the
cycle of period T=T1+T2 repeats.

Pulse Generator : A monostable multivibrator

m
It is having one stable state and one quasistable state. The
circuit remains in its stable state until a triggering signal
causes a transition to the quasistable state. Then after a time
T; the circuit returns to its stable state. Hence a sing
single pulse
has been generated; and the circuit is referred to as a one-one
shot.
(Monostable multivibrator)
o/p and capacitor voltage waveforms)
 1  v1 / v z  
T  R ' C l n 
 1  
1
if vz >> v1 and R2 = R3 so that   then T=0.69 R’C
2
Triangle –wave generator
Practical triangle-wave wave generator:

40
 ELECTRONIC DEVICES & CIRCUITS

R5 R5
 VZ  VZ
R1  R2 R1  R2

R1  R2
f 
4R3  R4 R5 c
Regenerative Comparator (Schmitt trigger)
Assume that vi<v1 so that v0 =+ v0 (+5v).Then using
superposition.
RV RV
v1  1 R  2 0  V1
R1  R2 R1  R2
if vi is now increased then v0 remains constant at V0 and
v1=V1= constant until vi = V1. At this threshold, critical or
triggering voltage, the o/p regeneratively switches to V0 = -
V0 and remains at this value as long as vi > v1.
This transfer characteristic is indicated in figure above.
The voltage at the non-inverting
inverting terminal for vi >V1 is
RV RV
v1  1 R  2 0  V2
R1  R2 R1  R2
2 R2V0
Hysteresis VH  V1  V2 
R1  R2
The most important use made of the Schmitt
trigger is to convert a very slowly varying i/p
voltagee into an o/p having an abrupt wave form,
occurring at a precise value of input voltage.

CHAPTER – 6(I)
EQUIVALENT CKT OF BJT AT LOW FREQUENCIES:
h parameter is preferred to define a particular transistor at low frequencies

V1=hiI1 + hr V2 -----------KVL
-----------
I2= hr I1+ho V2 ---------------- KCL

41
 ELECTRONIC DEVICES & CIRCUITS
Input current and output voltage are taken as independent parameters.
Approximately equivalent ckt.
CE configuration:
Now for CE configuration
Hie – input impedance (1.1 k) rent gain (50)
Hfe – forward current
Hre - reverse voltage gain (small -10-4) Hoe – output conductance 10-6 s
1/hoe ~ 1MΩ  high
 Approximately model of BJT in CE configuration

Condition so that approximate equivalent ckt is applicable

Is hoe R L  0.1
For exact analysis the current gain A1, input impedance Zin, voltage gain Av and output
impedance Zout is given by:
 hf
A1  Z in  hie  hr A1 RL
1  ho RL
1
R    h f hr 
Av  A1  L  z out  h0   
 Z in    hi  Rs 
 Z in 
A p  Av A1 Avs  Av  
 Z in  Rs 
 Rs 
A1s  A1   Ap s  Avs . A1s
 Z in  Rs 

Approximate analysis of BJT in various configuration at low frequency:-

frequency:
CE amplifier

1. A1 = -hfe
Input current and output current are 1800 out of phase.
V h I
2. Z in  be  ie b  hie (medium
medium)
Ib Ib
 R   h fe R L
3. Av  AI  L  
 Z in  hie
input, o/p voltage are 1800 out of phase

42
 ELECTRONIC DEVICES & CIRCUITS
Z out  
4.
Z out  Z out || RL   || RL  RL

Features:
(i) high current gain (ii) high voltage gain
(iii) input and o/p currents are phase shifted by 1800
(iv) input and o/p voltages are out of phase by 1800
(v) medium input impedance (vi) medium overall o/p impedance
(vii) Since the amplifier has both current gain and voltage gain simultaneously high, it can be
used
as an amplifier.

CB amplifier
V  hie I b  hie I b
Z in  eb  
Ie  I b  I c  I b 1  h fe 
hie
  30
1  h fe
IL  h fe I b  h fe

A1    
I e  I b 1  h fe   1  h fe


   0.9 to 0.99
R h fe RL h fe RL
Av  A1 L  
Z in 1  h fe hie hie
1  h fe
Z out   Z `out  Z out || R L
  || RL
 RL

Features:
1. high voltage gain
2. Current gain approximately but always less than 1.
3. i/p and o/p voltages are in phase
4. i/p and o/p currents are in phase
5. Lowest input impedance among the entire three configurations.
6. Highest input impedance among all the three configuration.
7. Since there is large variation in input and output impedance it can be used for matching.
8. Current gain is almost unity; it can be used as constant current source.
CC configuration
I b 1  h fe 
 1  h fe 
I
(1) A1  L 
Ib Ib

(2) Av  A1 L  1  h fe 
R RL
Z in hie  1  h fe RL   1
 hie  1  h fe RL
Vbe
(3) Z in 
Ib

43
 ELECTRONIC DEVICES & CIRCUITS
 h  Rs 
(4) Z out   ie 
 1 h 
 fe 
 h  Rs 
Z out ` Z out || R L   ie  || R L  Z out
 1 h 
 fe 
Features:
1. High current gain.
2. Voltage gain approximately one but less than one.
3. Highest input impedance among all the three configuration.
4. Lowest o/p impedance among all the three configuration.
5. input and o/p currents are in phase
6. input and o/p voltages are in phase
7. since input impedance is very high it can be used as a buffer amplifier (draws negligible
negl
current)
8. Since o/p impedance is very low, it can be used as a last stage of any audio amplifier to
match the low impedance speaker for maximum power transfer through it.
CE amplifier with emitter resistance Re: Re:-
Effect of Re
Parameter ce ce with re
A1 -hfe -hfe
R  h fe R L
Av -hfe L
hie hie  1  h fe R L
Zin hie hie+(1+hfe)Re
 h fe RL  h fe R L
Av
hie hie  1  h fe Re
By inducing Re
 Input impedance increase  Voltage gain decreases
 Also voltage gain is independent of h parameters and since h parameters are a function of
temperature as thus the voltage gain is stablised against the variation in temperature hence thermal
stability of the circuit increases.
Effect of Cascading (CE-CC)
 The input impedance of the overall amplifier is controlled by the input impedance of the Ist
stage.
 The voltage gain of the overall cascaded amplifier is the product of the voltage gains of the
individual stages.
 If the two stages are not direct coupled then the current gain of the overall amplifier is always
less than
han the product of current gains of individual stages.
 The output impedance of the overall amplifier is controlled by the output impedance of the last
stage.
 The output impedance of the overall amplifier is controlled by the output impedance of the last
stage.
Approximate conversion formulas for hybrid parameters:
hic= hie hrc= 1
hfc= -(1+hfe) hoc= hoe
hie h h
hib  hrb  ie oe  hre
1  h fe 1  h fe

44
 ELECTRONIC DEVICES & CIRCUITS
 h fe hoe
h fb   hob 
1  h fe 1  h fe
Note:- The CE parameters in terms of the CB paramete rs are obtained by interchanging the subscripts
parameters
b and c
Bootstrap Darlington emitter follower
Emitter follower with biasing resistors:
resistors:-
Z in  hie  1  h fe R L
Z in ` Z in || R1 || R2 .........relatively low value
The emitter follower has highest input impedance among
all three configurations. In the presence of biasing resistors
the overall input impedance falls to a relatively low value.
To increase the overall input impedance over in the
presence of biasing resistors we use the Bootstrap
principle.
Rb , Cb – Bootstrap resistor and capacitor.
Now Z`in = Rb (effective) + (R1 || R2 ||RL)
 
l arg e value

Rb
Rb (effective) =
1  Av
Due to Bootstrap principle, the input impedance of the
amplifier has very large value even in the presence of
biasing resistors.
Bootstrap Darlington emitter follower:
Rb
Rb eff  
1  Av
Av  Av1 Av 2
Z`in extremely large
CHAPTER – 6 (II)

HIGH FREQUENCIES EQUIVALENT MODEL OF

BJT IN CE CONFIGURATION
……….. hybrid  model.
cb`e  c rb`e  r
cb`c  c  rb `c  r
rbb`  base spreading resistance , represents the
effective resistance of the base region when the reverse
bias has been applied. Low value of the order of 8080Ωs.
rb`c  represents the resistance of the forward biased
junction J1 and has a relatively
elatively low value of the order
of 1kΩ.
rb`c  represents the resistance of the reverse bias
junction J2 and have a very high value of the order of 4
mega Ωs.
rce  represents the total resistance of the combined
forward biased junction J1 and reverse biased
bia junction

45
 ELECTRONIC DEVICES & CIRCUITS
J2. it has the relatively high value of the order of 100 K.
gm  transconductance -200 200 ms.
gm Vb`e  represents a current source which accounts for voltage gain of the CE amplifier at high
frequencies.
Cb`e  represents the junction capacitance of the FB junction J1, since the width of depletion layer
is very small at J1. This capacitance has relatively a higher value of the order of 100 picofarad.
Cb`c  represents the junction capacitance of the R.B ju junction J2. Since the width of depletion
layer is large this capacitance has a low value of the order of 3 Pico farad.
Relation between high frequency and low frequency parameters
Ic T
gm  VT 
VT 11600
h fe
rb `e  rbb `  hie  rb `e
gm
1
r  1  h fe 
rb `c  b `c rce   hoe  
hre  rb `e 
gm
Cb `e 
2f T
f T  Frequency at which short circuit current gain of CE amp.
At high frequency becomes unity.
C b `c  kV  n CE k  constant
n=1/2 …….. For abrupt or step junction =1/3 …… for linearly graded junction

MILLER’S THEOREM
 z   Z 
Z 1    Z 1   
 1  Av   1  1 / Av 

Dual miller’s theorem:

Z1 =Z (1-A1)
Z2 =Z (1-1/A1) =Z

46
 ELECTRONIC DEVICES & CIRCUITS
S.C. current gains of a CE amp. At high frequencies, bandwidth of operation and current gain –
B.W product
I  h fe
A1  o  S .C. current gain
I i 1  jf / f 
h fe
A1 
1  f / f 
2

  1800  tan 1  f / f  
1 1
Where f=  ... B.W of the amplifier
2 rb`e cb`e 2 r c
 The current gain at high frequencies for the
common emitter amplifier is complex and is
frequency dependent as the frequency of operation
increase the current gain decreases.
 Also the phase between the input and output
currents is other than 1800 and is frequency dependent
as the frequency of operation increases , its phase shift
with reference to 1800 increases.
Parameter fT :
Frequency at which short circuit current gain of CE amplifier at high frequency becomes unity.
h fe
Ai 
1  f / f 
2

At f=fr, Ai  1
f T  h fe  f    B.W

Current gain
1 h fe
f T  h fe  gm
2rb 'e cb 'e rb 'e
gm gm
fT   cons tan t c b 'e 
2 cb 'e 2f T

RC coupled amplifier
AV AT LOW , MID AND HIGH REQUENCY
Mid frequency region: - all capacitors are short circuit

47
 ELECTRONIC DEVICES & CIRCUITS
Vbe1
h fe I b1  h fe ~ gm Vbe1
hie
The above circuit is redrawn as
 g m RL
 m  180 0 Avm 
R
1 L
hie
g R
Avm  m L  m  180 0
R
1 L
hie
 High voltage gain
 Voltage gain is constant and is independent of frequency of operation
 i/p and output voltages are out of phase by 1800
Effect of Loading
 If the i/p impedance of the 2nd stage is infinite, it does not draw any current , then the voltage
gain of the 1st stage is max and is given by gmRL
 When Zin of 2nd stage is finite , it draws a finite current and then the voltage gain of the 1st stage
 R 
is reduced by a factor of 1  L 
 hie 
Low Frequency Region
…… effect of cc is to be taken
…….. cc  short circuit

jf / f1 1
Av1  AVm f1 
1  jf / f1 2 R L  hie c c
---- Lower cutoff frequency
Av1 f / f1

Avm 1   f / f1 
2

1  180 0  90 0  tan 1  f / f1 
 270 0  tan 1  f / f 1 

48
 ELECTRONIC DEVICES & CIRCUITS
g m RL hie
Where Avm 
rL  hie
High Frequency Region
Cc, Ce-S.C

1 1
R1 || R2 || ~
SC s SC s
1
Avh  AV 'm
1  jf / f 2
AVs 1
  h  180 0  tan 1  f / f 2 
A'Vm 1  f / f2 
2

1
AVm '   g m RL f2 
2R L C S
Where C s  C b 'e  1  g m R L C b 'c
.
Compound Transistor stages
1. CC-CCCC (Darlington) configuration:
(Already discussed earlier)
A1   0  hie
2 2

also. Input resistance of a Darlington connection is increased by 2(hfe+1)

2. CC-CE Connection:
In this case also the overall gain is  o .
2

In CC-CE
CE the collectors are not tied. As the two collectors
are in parallel the output resistance is reduced. Also
the frequency response of CC-CE CE is superior to that
of CC-CC.
3. CE-CB
CB (Cascade) Connection:

49
 ELECTRONIC DEVICES & CIRCUITS
The chief advantage is that gain can be provided to a large value resistance RL over a wide range of
frequencies.
I
Overall gain 0   01
I B1
Voltage gain Av
V   0 RL
Av  0 
Vs r 1  Rs
The output resistance of a CB stage is high so that we are able to connect a large load resistance RL.
Similarly the input resistance of a CB stage is low and this is the load resistance for the CE stage.
Hence the overall input resistance is low and this is reason for wide frequency response of CE-CB
cascade connection.
Complementary – Symmetry connection
Two transistors one npn and the other pnp have their emitters connected together so that this
connection is called complementary-symmetry emitter follower. The base are tied and signal is fed to
the base. Both the transistor are biased near cutoff. When the signal Vs is positive, the pnp transistor is
cutoff. The npn transistor is in active region and provides the o/p signal in the load resistor RL. For
negative swing pnp is active and provides the o/p.
This type of functioning is called push-pull and it doubles the dynamic range of the circuit by
accommodating a larger i/p signal
Various amplifier types and their Ri, R0 and Gain or transfer ratio

CHAPTER – 6 (III)

FEEDBACK
Negative feedback used in amplifiers
In negative feedback, part of the o/p voltage is feedback to the input which is out of phase with the
input voltage therefore the overall i/p voltage decreases and hence the overall voltage gain with
negative feed back decreases.
AV
AVf  k    feedback factor
1  kAV
(0  k  1)

Amplifier Gain- Ax RI RO

Ideal Practical Ideal Practical

V – V Amplifier V0  Very 0 Low
(Voltage Series) AV  high
Vi
I – I Amplifier I0 0 Low  Very High
(Current Shunt) AI 
Ii
V – I Amplifier I0  Very  Very High
(Current Series) GM  High
Vi
I – V Amplifier V0 0 Low 0 Low
(Voltage Shunt) RM 
Ii

50
 ELECTRONIC DEVICES & CIRCUITS

Results
RI Series Shunt
RIF > RI RIF < RI
Ro Voltage Current
Rof < Ro Rof > Ro
But there are several advantages of Negative feedback
(a) stability increases
(b) lower cutoff decreases
(c) upper cutoff frequency increases
(d) Bw increases
Bwf = Bw(1+ kAv)
But gain bandwidth product remains same
N
(e) noise decrease N f 
1  kAv
D
(f) distortion decrease D f 
1  kAV
(g) Zin may increase or decrease

Two types of feedback

Voltage and current, further subdivided as voltage series, voltage shunt and current series and
current shunt. The first word referring to the quantity sampled and second to the input
connection.
Voltage feedback: If the signal feedback is proportional to the o/p voltage
volt of the amplifier it is
voltage feedback
Current feedback: If the signal feedback is proportional to the o/p current of the amplifier it is
current feedback.
Zin and Zout in various feedback configuration
(i) Voltage series:

(This feedback n/w is purely resistive in nature)

exactly in phase
Z inf  Z in 1  kAv  i.e.Z in 
 Z 
Z outf   out  Z out 
1  kAv 
(ii) Current series:
Z in 
Z out 

(iii) Voltage shunt:

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Z in 
Z out 

(iv) current-shunt
Z in 
Z out 
Voltage series feedback arrangement
angement

Vf
k  1V f  V ' 0 
V 'o
 A I f  1  h fe   Z inf  hie  1  h fe RL
100% feedback in this amplifier 1  h R  h  Rs 
 Z outf   ie 
fe L
 Av f 
hie  1  h R
fe L
 1 h
 fe



Current series feedback

1  h fe  Re  Re 
k
h fe  RL   RL 
 AIf   h fe
 Z outf  , Z ' outf   || R L  R L
 Z in f  hie  1  h fe Re
 h fe R L
 Avf 
hie  1  h fe Re

Voltage-Shunt feedback
k  V f / V ' o Vf = (V’0- V’i)
 1 
 k  1  ~ 1 for AV  1
 Av 
Sensitivity:-
 dAvf   dAv 
Sensitivity:- =  /
 A   dv 
 vf 
 1 
= 
 1  kAv 
de-Sensitivity =D= | 1+kAV|

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Feedback Amplifier Analysis

Characteristic Voltage Series Current Series Current Shunt Voltage Shunt

Xf Voltage Voltage Current Current

(feedback Signal)
Sampled Signal Voltage Current Current Voltage
Xo
xf vf vf If If

xo vo Io Io vo
x vo Io Io vo
A o AV  GM  AI  RM 
xi vi vi Ii Ii
D = 1+Aβ 1 +Avβ 1 + GMβ 1 + AI β 1 + RMβ
Af Av GM AI RM
D D D D
Rif Ri D Ri D Ri Ri
D D
Rof Ro R(1 + GMβ) R(1 + AI β) Ro
1  Av  1  RM 

OSCILLATORS
Positive feedback
Here the feedback voltage is given in phase of the input voltage so that without giving any input
voltage the o/p voltage in the sinusoidal form is
received.
Also note that since the amplifier produces a
phase shift of 1800 therefore an additional
phase shift of 1800 has to be provided, by the
feedback circuit.
 Such network has to be a reactive network.
In oscillators, principle of positive feedback is
used.
AV
For positive feedback Avf 
1  kAV
If kAV  1

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V '0
Avf  
V 'i
V 'i  0
hence barkhausan criteria for oscillation is
kAv  1
  2n, n  1,2.....

RF oscillators , their frequency of oscillation and condition for oscillation

Hartley oscillator:
1
f0  .... frequency of oscillation
2 L1  L2 C 3
L2
condition for oscillation  
L1
Collpitt’s oscillator:

1 1 1 1
f0     ..... frequency of oscillation
2 L3  c1 c 2 
C1
     condition for osc.
C2
Clapp oscillator:
1 1 1 1 1
f0      frequency of oscillation
2 L3  c1 c 2 c3 
C1
    condition for oscillation
C2
wein bridge oscillator
-AF oscillator:
Note: Rf provides negative feedback to stablise the
oscillations
Hence it uses positive and negative feedback both frequency of
oscillation:-
1
f0 
2RC
and condition for oscillation AV  3

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RC phase shift oscillator
FET phase shift oscillation:-
1
 f     frequency of oscillation

2RC 6 
 A FET with μ <29 cannot be made to oscillate in such a circuit

Transistor phase-shift
shift oscillato
oscillator
Frequency of oscillation
1 1
f 
2RC 6  4k
k=Rc/R
29
h fe  4k  23 
k
The value of k which gives the minimum hfe turns out to 2.7 and for
this optimum value of Rc/R we find hfe=44.5

POWER AMPLIFIERS
Class A AB B C
1. Output waveform is Between half & full For half cycle Less than half cycle
available for full cycle. cycle
2. used as untruned Untuned power Untuned power Tuned radio frequecy
audio or vedio Amplifier Amplifier amplifier
amplifier
3. Maximum efficiency  max  54%  Vmin   max  88%
 V  Vmin   max  25 1  
  50 max %  Vc 
 Vmax  Vmin  Amax  78.5%

Class A operation
In class A operation, the operating point Q and the
signal are such that current flows at all times in the o/p
circuit. Q is located sothat the signal has equal swings in the
o/p circuit for distortionless operation.
Class A transformer coupled
η= conversion efficiency
signal power delivered to load
=  100  50%
DC power sup plied to output circuit

Class A series Fed

η= 25%

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 
 DC powersup plied  AC power developedin load
  
 VCCI C   1 
VmI m
 2 
 powerdissipatedin load R  dissipatio n in the
 dc  
 
 collectorPD 
I 2c R 
 dc 
with no signal
PD max =VCIC
1
 Pac delivered  P0 max
2

This statement is true in both series fed and transformer coupled cases.
Given PD max= 20 watts
Then in series fed Pac to load =10 watts
Pdc = 40 watts (=25%)

In transformer coupling with PD max =20 watts

Pdc= 20 watts (=50%)

Class B : push-pull amplifier

Output load current =k(ic1-ic2) =2k (B1 cos ω t + B3
cos 3 ωt+…)
Only odd harmonics are present. The push pull
system has balanced out the even harmonics.
 In class B operation, the operating point is at
cutoff so that the signal is amplified by one
transistor only for one half of the cycle.
P to load  VCC  Vmin
  ac   100
Pdc 4 Vcc
 PD max 4
Theoretical max.    max   100  78.5% also 
 0.4
4 Pac max  2
Under these maximum valuess of Pac, PD per transistor =0.2 Pac.
PD max = 1/5 Pac max.
Maximum AC power obtainable in class B push pull
= 5 PD (of the transistor)
Features of class B push-pullpull operation
 Greater power output  Higher power efficiency  No power loss at zero signal
Class AB operation
From the iB-vB input characteristics, the o/p current i
of the one transistor is shown when it conducts due to
one half of the input base voltage (sinusoidal). For the
initial time, the o/p current is zero till the signal
reaches the value Vγ. This is called cross over
distortions.
It is for this reason that the system is operated in class
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AB so that with no signal a small current is following in the o/p. Class AB improves distortions. There
is DC power used under zero signal condition power efficiency is also reduced.
Class ‘C’ operation
Dc bias is adjusted than its cutoff value so that the o/p current flows for less than half of the i/p voltage
cycle therefore the o/p represents narrow sinusoidal pulses which will be highly rich in harmonics.

Features:
(i) Max. distortion
(ii) Max. power o/p
(iii) Max. conversion efficiency
(iv) Used only as modulated power amplifiers
in high power transmitters where the o/p
power is the main criteria and distortion is
of no consideration.

Distortion in Amplifiers
Non linear Distortion:- This is due to production of harmonics (new frequencies) in output.
linear Dynamic curve transfer characteristic of circuit. To reduce this push-Pull
This is because of non-linear
amplifier is used.
freq. Distortion:- when signal component of different frequencies are amplified differently.
Phase shift distortion:- unequal phase shift of signals of different frequencies. Because the
phase angle of complex gai
gain A depends upon the frequencies.

MULTIVIBRATORS

BJT bistable multivibrator:

Operation:
Assume I2 > I1

I 2  I 2 PL  VC 2  V B 1  VC 1  I1 R L  I1 

I 2  I 2 R L  VC 2  V B 2  
BJT monostable multivibrations:
Operation:
We first show that in normal opration, Q1 is ON an
Q2 is OFF. With a +ve trigger pulse applied to base
of Q2, Q2 switches ON and Q1 is OFF. The elements
in the circuit specifically C and R along with the

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supply voltages decide the duration T1 for which Q2 is ON.
At the end of T1the monostable multivibrator reverts
reverts to the normal state namely Q1 ON and Q2 OFF.
BJT Astable Multivibrator:
A stable multivibrators has two BJT s capacitively
coupled with base and collector connected to supply
voltage VCC through resistors. At any time, one
transistor Q1 is ON and other Q2 is OFF for a time T1
depending on the C,R values. Switching takes place
at the end of T1, Q1 turns OFF and Q2 turns ON for a
time T2 and again switching takes place. It is free
running with a period given by T1 plus T2.
T= T1+T2

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