ZEAL EDUCATION SOCIETY’S

ZEAL POLYTECHNIC,PUNE
NARHE │PUNE -41 │ INDIA
DEPARTMENT OF COMPUTER ENGINEERING

Question Bank for Multiple Choice Questions

Program: Diploma in Computer engineering Program Code:- CO

Scheme:-I Semester:- 3
Course:- Digital Techniques Course Code:- 22320

01 – Number Systems Marks:-6

Content of Chapter:-
Number System Binary system, DecimalSystem, Octal Number, Hexadecimal Addition Subtraction,
multiplicationdivision
Subtractions using 1‘s and 2‘s complement BCD, Gray
Code, Excess-3, and ASCIICode.
BCD Addition
02 – Logic Gat s & Logic families Marks:-10
Content of Chapter:-
2.1. Logic gates Symbol, T.T & Logical Expression, truth table of basic gates (AND OR, Not ),Universal gates (NAND & NOR) 7
special purpose gates (EXOR-EXNOR),Tristate logic.
2.2 Boolean algebra: Laws of Boolean algebra, Duality theorem, De-Morgan‘s theorem
2.3 Logic families: Characteristics of logic families: Noise margin, Power dissipation, Figure of Merit, Fan-in &fan-out, Speed of operation,
Comparison of TTL & CMOS families, Types of TTL & NAND gate
3-Combinational logic circuit. Marks:-20
Content of Chapter:
3.1 Standard Boolean representation: Sum of Product (SOP) and Product of Sum( POS), Min-term and Max- term, conversion
between SOP and POS forms, realization using NAND /NOR gates
3.2 K-map reduction technique for the Boolean expression: Minimization of Boolean functions up to 4 variables(SOP and POS form)
3.3 Design of arithmetic circuits and code converter using K-map: Half and full Adder, half and full Subtractor , gray to binary and
binary to gray (up to 4 bits)
3.4 Arithmetic circuits: (IC 7483 ) Adder and Subtractor, BCD adder
3.5 Encoder/Decoder: Basics of encoder, decoder, comparison, (IC 7447) BCD to 7 segment decoder/driver
3.6 Multiplexer and Demultiplexer: working , truth table and applications of Multiplexers and Demultipleres, MUX tree. 1C 74151 as MUX;
DEMUX tree, DEMUX as decoder, IC 74155 as DEMUX
3.7 Buffer: Tristate logic, unidirectional and bidirectional buffer (1
C74LS244,74LS245)

Page 1 of 104
04- Sequential Logic circuit Marks:-18
Content of Chapter:-
4.1 Basic memory cell:RS latch using NAND and NOR
4.2 Triggering Methods: Edge trigger and level trigger.
4.3 SR Flip Flop: SR –Flipflop ,clocked SR flip flop with preset and clear ,drawbacks of SR flip flop
4.4 JK flipflops: Clocked JK Flopflop with Prest and clear racearound condition in JK flip flop, Master slave JK flip flop, D & Ttype
flipflop Excitation table of flip flops ,Block schematic and function table of IC 7474,7475
4.5 Shift register:Logic diagram of 4-bit Shift register-SISO,PISO,PIPO,4 bit Universal shift register
4.6 Counters :Asynchronous counter:4 Bit Ripple Counter,4 Bit up/downCounter,modulus of counter Synchronous
counter:Design of 4 bit synchronous Up/Down counter
5. Data Conve ters and PLC Marks:-16
Content of Chapter:-
5.1. Data Converters : DAC: Types, weighted resistor circuit and R-2R ladder circuit, DAC IC 0808/0809,specifications
ADC:Block Diagram ,Types and working of dual slope ADC,SAR ADC ,ADC IC
0808/0809,specification
Memory :RAM and ROM basic building blocks, read and write operations, types of semiconductor andmemories
PLD :basic Building blkocks and types of PLDs, PLA, PAL, GAL
CPLD: Basic Building Blocks,Functionality.

1. The Base of Binary no. system is...

A) 2 C)10
B) 8 D 16
Answer: - Option A
Explanation: - Radix /Base of binary no system is 2.

2. Convert the following binary number to decimal. (01010)

A)11 C)15
B)35 D)10

Answer: - Option D
Explanation: - The conversion of (1010) according to 8421 rule is (10) in decimal.

3. The Binary Addition of 1+1 is

A) 0 With 0 Carry C) 1 With Carry 0
B) 0 With Carry 1 D) 1 With Carry 0

Answer: - Option B
Explanation: - Binary addition rules 1+1=0 with carry 1.

4. Convert (214)8 into decimal

A) (140)10 C)(142)10
B) (141)10 D)(130)10

Answer: - Option C
Explanation: - After conversion 214 in octal is equal to 142 in decimal.
Page 2 of 104
 5. Convert binary to octal: (110110001010)2
A) (5512)8 C)(4532)8
B) (6612)8 D)(130)10
Answer: - Option B
Explanation: - The binary equivalent is segregated into groups of 3 bits, starting from left. And then for each group, the
respective digit is written. Thus, the octal equivalent is obtained. (110110001010)2
= (6612)8.

6.The decimal equivalent of the binary number (1011.011)2 is

A) (11.375)10 C)(11.175)10
B) (10.123)10 D)(9.23)10

Answer: - Option C
Explanation :- 1011.011 from binary to decimal is 11.375

7. Binary coded decimal is a combination of

A) 2 Binary Digits C)4 Binary Digits
B) 3s Binary Digits D)5 Binary Digits
Answer: - Option C
Explanation: - The decimal number 10 is represented in its BCD form as 0001 0000, in accordance to8421 for each of the two
digits.

8.The given hexadecimal number (1E.53)16 is equivalent to

A) (35.684)8 C) (34.340)8
B) (36.246)8 D) (35.599)8
Answer:-Option B
Explanation:- First, the hexadecimal number is converted to it‘s equivalent binary form, by writing the binary equivalent of each
digit in form of 4 bits. Then, the binary equivalent bits are grouped in terms of 3 bits and then for each of the 3-bits, the respective
digit is written. Thus, the octal equivalent is obtained. (1E.53)16 = (0001 1110.0101 0011)2
= (00011110.01010011)2
= (011110.010100110)2
= (011 110.010 100 110)2
= (36.246)8.

9. The octal number (651.124)8 is equivalent to A)

(1A9.2A)16 C) (1A8.A3)16
B) (1B0.10)16 D) (1B0.B0)16
Answer: - Option A
Explanation:-First, the octal number is converted to it‘s equivalent binary form, by writing the binary equivalent of each digit in
form of 3 bits. Then, the binary equivalent bits are grouped in terms of 4 bits and then for each of the 4-bits, the respective digit is
written. Thus, the hexadecimal equivalent is obtained. (651.124)8 = (110 101 001.001 010 100)2
= (110101001.001010100)2
= (0001 1010 1001.0010 1010)2
= (1A9.2A)16

Page 3 of 104
 10. The octal equivalent of the decimal number (417)10 is
A) (641)8 C) (640)8
B) (619)8 D) (598)8
Answer: Option A
Explanation: - Octal equivalent of decimal number is obtained by dividing the number by 8 and collecting the remainders in
reverse order.
8 | 417
8 | 52 — 1
8|6–4
So, (417)10 = (641)8.

11. Convert the hexadecimal number (1E2)16 to decimal:

A) 480 C) 482
B) 483 D) 484
Answer: - Option C
Explanation: -Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base index along with the value at that
index position. = 256 + 224 + 2 = (482)10.

12. (170)10 is equivalent to

A) (FD)16 C) (AA)16
B) (DF)16 D) (AF)16
Answer: - Option C
Explanation:-Hexadecimal equivalent of decimal
number is obtained by dividing the number by 16 and
collecting the remainders in reverse order. Hence,
(170)10 = (AA)16

13. Convert (214)8 into decimal:

A) (140)10 C) (142)10
B) (141)10 D) (130)10
Answer: - Option A
Explanation:-
Step by step solution
Step 1: Write down the octal number:214
Step 2: Multiply each digit of the octal number by the corresponding power of eight:2x82 + 1x81 + 4x80 Step 3: Solve the
powers:2x64 + 1x8 + 4x1
Step 4: Add up the numbers written above:128 + 8 + 4 = 140 So, 140 is the
decimal equivalent of the octal number 214.

14. Convert (0.345)10 into an octal number:

A) (0.16050)8 C) (0.19450)8
B) (0.26050)8 D) (0.24040)8
Answer: - Option B
Explanation:-Converting decimal fraction into octal number is achieved by multiplying the fraction part by 8 eve and collecting the
integer part of the result, unless the result is 1. So, (0.345)10 = (0.26050)8

Page 4 of 104
15. Convert the binary number (01011.1011)2 into decimal:
A) (11.6875)10 C) (10.9876)10
B) (11.5874)10 D) (10.7893)10
Answer: - Option B
Explanation:-Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along with the value at that index
position. So, (01011.1011)2 = (11.6875)10.

16. Octal to binary conversion: (24)8 =?

A) (111101)2 C) (111100)2
B) (010100)2 D) (101010)2
Answer: - Option B
Explanation:-Each digit of the octal number is expressed in terms of group of 3 bits. Thus, the binary equivalent of the octal
number is obtained. (24)8 = (010100)2.

17. Convert binary to octal: (110110001010)2 =?

A) (5512)8 C) (4532)8
B) (6612)8 D) (6745)8
Answer: - Option B
Explanation:- The binary equivalent is segregated into groups of 3 bits, starting from left. And then for each group, the respective
digit is written. Thus, the octal equivalent is obtained. (110110001010)2 = (6612)8

18. Any signed negative binary number is recognized by its

A) MSB C) Byte
B) LSB D) Nibble
Answer: - Option A
Explanation:-Any negative number is recognized by its MSB (Most Significant Bit) ..................................... Nibble is a combination
of four bits and Byte is a combination of 8 bits

19. The parameter through which 16 distinct values can be represented isknown as
A) Bit C) Word
B) Byte D) Nibble
Answer: - Option C
Explanation:- It can be represented up to 16 different values with the help of a Word. Nibble is a combination of four bits and Byte
is a combination of 8 bits. It is ―word‖ which is said to be a collection of 16- bits on most of the systems

20. If the decimal number is a fraction then its binary equivalent is obtainedby the number
continuously by 2.
A) Dividing C) Adding
B) Multiplying D) Subtracting
Answer: - Option B
Explanation:- On multiplying the decimal number continuously by 2, the binary equivalent is obtained by the collection of the
integer part

Page 5 of 104
21. The representation of octal number (532.2)8 in decimal is
A) (346.25)10 C) (340.67)10
B) (532.864)10 D) (531.668)10
Answer: - Option A
Explanation:- Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that
index position.
(532.2)8 = 5 * 8^2 + 3 * 8^1 + 2 * 8^0 + 2 * 8^-1 = (346.25)10

22. The decimal equivalent of the binary number (1011.011)2 is

A) (11.375)10 C) (11.175)10
B) (10.123)10 D) (9.23)10
Answer: - Option A
Explanation:- 1011.011 from binary to decimal is 11.375

23. The decimal equivalent of the octal number (645)8 is

A) (450)10 C) (421)10
B) (451)10 D) (501)10
Answer: - Option B
Explanation:- Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along
with the value at that index position. The decimal equivalent of the octal number (645)8 is
6 * 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 * 8 + 5
= 384 + 32 + 5 = (421)10

24. The largest two digit hexadecimal number is

A) (FE)16 C) (FF)16
B) (FD)16 D) (EF)16
Answer: - Option C
Explanation:- The largest two-digit hexadecimal number is (FF)16

25. The quantity of double word is

A) 16 Bits C) 4 Bits
B) 32 Bits D) 8 Bits
Answer: - Option B
Explanation:-The quantity of double word is 32 bits

26. The binary number 11011 is equivalent to decimal number

A)19 C) 27
B)12 D) 21
Answer: - Option C
Explanation:-11011=(1×2⁴)+(1+2³)+(0×2²)+(1×2¹)+(1×2⁰) =27

27. The largest two-digit hexadecimal number is

A) FE C)EF
B) FD D) FF
Answer: - Option D
Explanation:-The largest two-digit hexadecimalnumber is (FF)16
Page 6 of 104
 28. A Nibble is equal to
A) 1 C) 4
B) 2 D) 8
Answer: - Option C
Explanation:-A Nibble is equal to 4

29.1 Kilobits are equal to

A) 1000 Bits C) 1012 Bits
B) 1024 Bits D) 1008 Bits
Answer: - Option B
Explanation:-1 Kilobits are equal to 1024 Bits

30. The number of digits in octal system is ………

a) 8
b) 7
c) 9
d) 10
Answer : a
Explanation: The octal system has 8 digits 0 to 7.

31. Decimal 43 in hexadecimal and BCD number system is respectively……. and ……..
a) B2 and 01000011
b) 2B and 01000011
c) 2B and 00110100
d) B2 and 01000100
Answer : b
32. The greatest negative number which can be stored is 8 bit computer using 2’s complementarithmetic is ……..
a) -256
b) -128
c) -255
d) -127
Answer: b
Explanation: The largest negative number is 1000 0000 = -128.

33. The binary number 10101 is equivalent to decimal number …………..

a) 19
b) 12
c) 27
d) 21
Answer : d

34. 2’s complement of binary number 0101 is ………..

a) 1011
b) 1111
c) 1101
d) 1110
Answer : a
Explanation: 1‘s complement of 0101 is 1010 and 2‘s complement is 1010+1 = 1011

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35. Decimal number 10 is equal to binary number ……………
a) 1110
b) 1010
c) 1001
d) 1000
Answer : b
Explanation: 1010 = 8 + 2 = 10 in decimal

36. In 2’s complement representation the number 11100101 represents the decimal number
……………
a) +37
b) -31
c) +27
d) -27
Answer : d
Explanation:
A = 11100101. Therefore Ā = 00011010 and A‘ = Ā + 1 = 00011011 = 16 + 8 + 2 + 1 = 27. Therefore A = -
27

37. Decimal 43 in hexadecimal and BCD number system is respectively……. and ……..
a) B2 and 01000011
b) 2B and 01000011
c) 2B and 00110100
d) B2 and 01000100
Answer : b
Explanation:

38. 7BF16 = 2
a) 0111 1011 1110
b) 0111 1011 1111
c) 0111 1011 0111
d) 0111 1011 0011
Answer : b
Explanation:
7BF16 = 7 x 162 + 11 x 161 + 15 x 160 = 1983 in decimal = 0111 1011 1111 in binary

39. The hexadecimal number (3E8)16 is equal to decimal number ………

a) 1000
b) 982
c) 768
d) 323
Answer : a
Explanation: 3 x 162 + 14 x 161 + 8 = 1000

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40. . 1’s complement of 11100110 is ……………….
a) 00011001
b) 10000001
c) 00011010
d) 00000000
Answer: a
Explanation: By replacing 1 by 0 and 0 by 1.

Page 9 of 104
 02 – Logic Gat s & Logic families Marks:-10
Content of Chapter:-
2.1. Logic gates Symbol, T.T & Logical Expression, truth table of basic gates (AND OR, Not ),Universal gates (NAND & NOR) 7
special purpose gates (EXOR-EXNOR),Tristate logic.
2.2 Boolean algebra: Laws of Boolean algebra, Duality theorem, De-Morgan‘s theorem
2.3 Logic families: Characteristics of logic families: Noise margin, Power dissipation, Figure of Merit, Fan-in &fan-out, Speed of operation,
Comparison of TTL & CMOS families, Types of TTL & NAND gate

1. The expression for Absorption law is given by

A) A + AB = A C) AB + AA‘ = A
B) A + AB = B D) A + B = B + A
Answer: - Option A
Explanation: - The expression for Absorption Law is given by: A+AB = A. Proof: A + AB = A(1+B) = A(Since 1 + B = 1 as per
1's Property)

2. According to boolean law: A + 1 = ?

A) 1 C) 0
B) A D) A‘
Answer: - Option A
Explanation: - Explanation: A + 1 = 1, as per 1's Property. Explanation: The involution of A means double
inversion of A (i.e. A‖) and is equal to A.

3. DeMorgan‘s theorem states that

A) (AB)’ = A’ + B’ C) A‘ + B‘ = A‘B‘
B) (A + B)‘ = A‘ * B D)(AB)‘ = A‘ + B
Answer: - Option A
Explanation: - the complement of the product of all the terms is equal to the sum of the complement
of each term.

4. In boolean algebra, the OR operation is performed by which properties?

A) Associative PropertiesB)Commutative Properties Answer: - Option A
C) Distributive Properties
D) All Of Above
Explanation: - The expression for Associative property is given by A+(B+C) = (A+B)+C & A*(B*C) =
(A*B)*C.

5. How many AND gates are required to realize Y = CD + EF + GA)4 C)3

B)5 D)2
Answer: - Option A
Explanation: - Y = CD + EF + G
The number of two input AND gate = 2.

6. The NOR gate output will be high if the two inputs are
A) 00 C)10
B) 01 D)11
Answer: - Option A
Explanation: - A HIGH output (1) results if both the inputs to the gate are LOW (0
Page 10 of 104
7. Universal gates are
A) NAND & NOR C) XOR & OR
B) AND & OR D) EX-NOR & XOR
Answer: - Option A
Explanation: - Universal gates are NAND & NOR

8. How many two input AND gates and two input OR gates are required to realize Y =
BD + CE + AB?
A) 3, 2 C) 1, 1
B) 4, 2 D) 2, 3
Answer: - Option A
Explanation: - There are three product terms. So, three AND gates of two inputs are required.

9. The gates required to build a half adder are

A) EX-OR Gate And NOR Gate C) EX_OR Gate And AND Gate
B) EX-OR Gate And OR Gate D) EX-NOR Gate And AND Gate
Answer: - Option A
Explanation: - The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the SUM of the two input bits
whereas AND outputs the CARRY of the two input bits.

10. The inverter is ……………

A) NOT Gate C) AND Gate
B) OR Gate D) None Of The Above
Answer: - Option A
Explanation: - The inverter is NOT gate

11. The inputs of a NAND gate are connected together. The resulting circuit is ………….
A) OR Gate C) NOT Gate
B) AND Gate D) None Of The Above
Answer: - Option A
Explanation: - The two inputs of the NAND gate are connected, only two input combinations can be used. The NAND Gate will emit a
LOW if any input is HIGH. The NAND gate would be output HIGH if all inputs are LOW

12. The NOR gate is OR gate followed by ………………

A) AND Gate C) NOT Gate
B) NAND Gate D) None Of The Above
Answer: - Option A
Explanation: - The NOR gate is OR gate followed by NOT gate

13. The NAND gate is AND gate followed by …………………

A) NOT Gate C) AND Gate
B) OR Gate D) None Of The Above
Answer: - Option A
Explanation: - The NAND gate is AND gate followed by NOT gate

14. Digital circuit can be made by the repeated use of ………………

A) OR Gates C) NAND Gates
B) NOT Gates D) None Of The Above
Answer: - Option C
Explanation: - NAND gate is universal gate.
Page 11 of 104
15. The only function of NOT gate is to ……………..
A) Stop Signal C) Act As A Universal Gate
B) Invert Input Signal D) None Of The Above
Answer: - Option A
Explanation: - The only function of NOT gate is to Invert Input signal

16. When an input signal 1 is applied to a NOT gate, the output is ……

A) 0 C) Either 0 & 1
B) 1 D) None Of The Above
Answer: - Option A

17. In Boolean algebra, the bar sign (-) indicates ………………..

a) OR operation c)NOT operation
b) AND operation d) None of the above
Answer: - Option a

22. An OR gate has 4 inputs. One input is high and the other three are low.
The output is …….
A) Low
B) High
C) Alternately High And Low
D) )May Be High Or Low Depending On Reative Magnitude Of Inputs
Answer: - Option B

23. Both OR and AND gates can have only two inputs.
A) True B) False
Answer: - Option B

24. The output will be a LOW for any case when one or more inputs are
zero in a/an …………
A) OR Gate C) AND Gate
B) NOT Gate D) NAND Gate
Answer: - Option C

25 NAND circuits are contained in a 7400 NAND IC.

A) 1 C) 4
B) 2 D) 8
Answer: - Option C

26 Truth table entries are necessary for a four-input circuit.

A) 4 C)12
B) 8 D)16
Answer: - Option D
27. The basic logic gate whose output is the complement of the input is ………….
A) OR Gate C) INVERTER Gate
B) AND Gate D) Comparator
Answer: - Option C

Page 12 of 104
28 ................. input values will cause an AND logic gate to produce a HIGH output.
A) At Least One Input Is HIGH C)All Inputs Are HIGH
B)At Least One Input Is LOW D) All Inputs Are LOW
Answer: - Option C

29. A NAND gate has …….. inputs and ...................... output.

A) LOW Inputs And LOW Outputs
B) HIGH Inputs And HIGH Outputs
C) Low Inputs And High Outputs
D) None Of The Above
Answer: - Option C

30 ................. truth table entries are necessary for a four-input circuit.

A) 4 C) 12
B) 8 D) 16
Answer: - Option D

31. Exclusive-OR (XOR) logic gates can be constructed from ....................................... logic gates.
A) OR Gates Only C)AND Gates, OR Gates, And NOT Gates
B) AND Gates And NOT Gates D) OR Gates And NOT Gates
Answer: - Option C

32 .................... NAND circuits are contained in a 7400 NAND IC.

A) 1 C) 4
B) 2 D) 8
Answer: - Option C

33. The inputs of a NAND gate are connected together. The resulting circuit is ………….
A) OR gate B) AND gate
C) NOT gate D) none of the above
Answer: Option C

34. How many OR gates are required to realize Y = CD + EF + GA)4

C)3
B)5 D)2
Answer : Option D
Explanation:-The number of two input OR gate = 2

35 The only function of NOT gate is to ……………..

a) Stop signal
b) Invert input signal
c) Act as a universal gate
d) None of the above
Answer : b

Page 13 of 104
36. When an input signal 1 is applied to a NOT gate, the output is ………………
a) 0
b) 1
c) Either 0 & 1
d) None of the above
Answer : a

37. In Boolean algebra, the bar sign (-) indicates ………………..

a) OR operation
b) AND operation
c) NOT operation
d) None of the above
Answer : c

38. An OR gate has 4 inputs. One input is high and the other three are low. The output is …….
a) Low
b) High
c) alternately high and low
d) may be high or low depending on relative magnitude of inputs
Answer : b
Explanation: In OR any input high means high output.

39. Both OR and AND gates can have only two inputs.
a) True
b) False
Answer : b
Explanation: Any number of inputs are possible

40. For the gate in the given figure the output will be ………..

a) 0
b) 1
c) A
d) Ā
Answer : 4
Explanation: If A = 0, Y = 1 and A = 1, Y = 0 Therefore Y = Ā

Page 14 of 104
3-Combinational logic circuit. Marks:-20
Content of Chapter:
3.1 Standard Boolean representation: Sum of Product (SOP) and Product of Sum( POS), Min-term and Max- term, conversion
between SOP and POS forms, realization using NAND /NOR gates
3.2 K-map reduction technique for the Boolean expression: Minimization of Boolean functions up to 4 variables(SOP and POS form)
3.3 Design of arithmetic circuits and code converter using K-map: Half and full Adder, half and full Subtractor , gray to binary and
binary to gray (up to 4 bits)
3.4 Arithmetic circuits: (IC 7483 ) Adder and Subtractor, BCD adder
3.5 Encoder/Decoder: Basics of encoder, decoder, comparison, (IC 7447) BCD to 7 segment decoder/driver
3.6 Multiplexer and Demultiplexer: working , truth table and applications of Multiplexers and Demultipleres, MUX tree. 1C 74151 as MUX;
DEMUX tree, DEMUX as decoder, IC 74155 as DEMUX
3.7 Buffer: Tristate logic, unidirectional and bidirectional buffer (1
C74LS244,74LS245)

1.A full adder logic circuit will have

a) Two inputs and one output c) Two inputs and two outputs
b) Three inputs and three outputs d)Three inputs and two outputs
Answer: - Option d
Explanation: - Full adder have three input A,B and C and Two output sum and carry.

2. The gates required to build a half adder are

a) EX-OR gate and NOR gate c)EX-OR gate and AND gate
b) EX-OR gate and OR gate d) EX-NOR gate and AND gate
Answer: - Option c
Explanation: - SUM=A ExOR B, CARRY=A.B

3. There are cells in a 4-variable K-map.

a) 12 c) 18
b) 16 d) 8
Answer: - Option b

4. Don’t care conditions can be used for simplifying Boolean expressions in

a) Registers c) K-maps
b) Terms d) Latches
Answer: - Option c

5. No. of Inputs available for Half Substractors are

a) 1 c) 3
b) 2 d) 4
Answer: - Option b

Page 15 of 104
 6. No.of Outputs of Full Adders are
a) 1 c) 3
b) 2 d) 4
Answer: - Option b
Explanation: - Output of full adder are sum and carry.

7. Multiplexer is a
a) Type of decoder which decodes several inputs and gives one output
b) Device which converts many signals into one
c) Takes one input and results into many output
d) Type of encoder which decodes several inputs and gives one output
Answer: - Option b
Explanation: - Multiplexer have many input and only one output.

8. The function of an enable input on a multiplexer chip is

a) To apply Vcc c) To active the entire chip
b) To connect ground d) To active one half of the chip
Answer: - Option b
Explanation: - Enable input used in multiplexer to active the entire chip.

9. Number of select lines would be required for an 8-line-to-1-line multiplexer?

a) 2 c) 8
b) 4 d) 3
Answer: - Option d
Explanation: - No of input =2^n (n= no of select lines)

10. The word Demultiplexer means

a) One into many c) both a & b
b) Many into one d) One into one
Answer: - Option a
Explanation: - Demultiplexer means one to many.

11. In 1-to-4 Demultiplexer, how many select lines are required ?

a) 2 c) 1
b) 3 d) 4
Answer: - Option a
Explanation: - No of input =2^n (n= no of select lines)

Page 16 of 104
 12. Which of the following logic expressions represents the logic diagram shown?

a) X=AB‘+A‘B c) X=(AB)‘+A‘B‘
b) X=(AB)‘+AB d) X=A’B’+AB
Answer: - Option d
Explanation: - Logical diagram is constructed using AND ,OR and NOT Gate.

13. Which of the following combinations of logic gates can decode binary 1101?

a) One 4-input AND gate c) One 4-input NOT gate

b) One 4-input AND gate, one inverter d) One 4-input NAND gate.
Answer: - Option b
Explanation: - One 4-input AND gate and one inverter is required to decode binary 1101.

14. For the device shown here, assume the D input is LOW, both S inputs are LOW and the input isLOW. What is the
status of the Y’ outputs?
a) All are HIGH c) All but Y0 are LOW
b) All are LOW d) All but Y0 are HIGH
Answer: - Option d

15. 3 bits full adder contains

a) 3 combinational inputs c) 6 combinational inputs
b) 4 combinational inputs d) 8 combinational inputs
Answer: - Option d
Explanation: - No of input =2^n (n= no of combinational inputs )

16. The basic building blocks of the arithmetic unit in a digital computers are
a) Subtractors c) Multiplexer
b) Adders d) Comparator
Answer: - Option b
Explanation: -Adders are acts as basic building blocks of the arithmetic unit in a digital computers.

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 17. A digital system consists of types of circuits.
a) 2 c) 4
b) 3 d) 5
Answer: - Option a
Explanation: - A digital system consists of Combinational circuit and sequential circuit.

18. In a combinational circuit, the output at any time depends only on the
at that time.
a) Voltage c) Input values
b) Intermediate values d) Clock puls
Answer: - Option c
Explanation: - combinational circuit dose not have memory.

19. In a sequential circuit, the output at any time depends only on the input valuesat that time.
a) Past output values c) Both past output and present input
b) Intermediate values d) Present input values
Answer: - Option c
Explanation: - sequential circuit have memory.

20. All logic operations can be obtained by means of

a) AND and NAND operations c) OR and NOT operations
b) OR and NOR operations d) NAND and NOR operations
Answer: - Option d
Explanation: - NAND and NOR Gate acts as a universal gate.

21. The flag bits in an ALU is defined as

a) The total number of registers c) The total number of control lines
b) The status bit conditions d) All of the Mentioned
Answer: - Option b
Explanation: -The flag bits is defined as the status bit conditions.

22. How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3 c) 2
b) 4 d) 5
Answer: - Option c
Explanation: - For the construction of a 4-to-1 multiplexer two 1-input NOT gates and one 4-inputs OR gate is required.

23. The enable input is also known as

a) Select input c) Strobe
b) Decoded input d) Sink
Answer: - Option C
Explanation: - strobe is also known as enable.

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 24. In which of the following gates, the output is 1, if and only if at least one input is 1?a)NOR c)OR
b)AND d)NAND
Answer: - Option c
Explanation: - Logic of OR Gate is-‖ if any input is high ,then output is also high‖.

25. The time required for a gate or inverter to change its state is called
a) Rise time c)Propagation time
b) Decay time d)Charging time
Answer: - Option c
Explanation: - The time required for a gate or inverter to change its state is called as Propagation time.

26. The time required for a pulse to change from 10 to 90 percent of its maximumvalue is called
a) Rise time c)Propagation time
b) Decay time d)Operating speed
Answer: - Option a
Explanation: -The time required for a pulse to change from 10 to 90 percent of its maximumvalue is called as Rise time.

27. What is the minimum number of two-input NAND gates used to perform the function of two input ORgate ?
a) one c)three
b) two d)four
Answer: - Option c
Explanation: -NAND Gate is acts as a universal gate.

28. Odd parity of word can be conveniently tested by

a) OR gate c)NOR gate
b) AND gate d)XOR gate
Answer: - Option d
Explanation: -XOR Gate is used as a parity tester.

29. Which of the following gates would output 1 when one input is 1 and other input is 0 ?
a) OR gate c)NAND gate
b) AND gate d)both (a) and ©
Answer: - Option d
Explanation: - Logic of OR Gate is ―if any input is high ,then output is also high‖ and Logic of NAND Gate is ―if any input is low
,then output is also high‖.

30. Which of the following gates are added to the inputs of the OR gate to convertit to the NAND gate
?
a) NOT c)OR
b) AND d)XOR
Answer: - Option a
Explanation: - NAND Gate is called as bubbled OR Gate.

31. The EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter ?
a) OR c)NAND
b) AND d)XOR
Answer: - Option d Explanation: - XOR Gate +NOT Gate=XNOR Gate.
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 32. A positive AND gate is also a negative
a) NAND gate c)AND gate
b) NOR gate d)OR gate
Answer: - Option d
Explanation: - A positive AND gate is also a negative OR gate.

33. An OR gate can be imagined as

a) Switches connected in series c)MOS transistors connected in series
b) Switches connected in parallel d)None of these
Answer: - Option b
Explanation: - An OR gate can be imagined as Switches connected in parallel.

34. Which combination of gates does not allow the implementation of an arbitrary boolean function?
a) OR gates and AND gates only c)OR gates and NOT gates only
b) OR gates and exclusive OR gate d)NAND gates only
Answer: - Option b
Explanation: - OR gates and exclusive OR gate are not allow the implementation of an arbitrary booleanfunction.

35. Which one of the following will give the sum of full adders as output ?
a) Three point majority circuit
b) Three bit parity checker
c) Three bit comparator
d) Three bit counter
Answer: - Option d
Explanation: - Three bit counter will give the sum of full adders as output .

36. The maximum frequency at which digital data can be applied to gate is called
a)Operating speed c) Binary level transaction period
b)Propagation speed d) Charging time
Answer: - Option a
Explanation: - The maximum frequency at which digital data can be applied to gate is called as Operating speed.

37. If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero
indication and
a) An underflow condition c) An overflow condition
b) A neutral condition d) One indication
Answer: - Option c
Explanation: - If the two numbers include a sign bit in the highest order position then it is an overflow condition

38. In the expression A + BC, the total number of minterms will be ………
a) 2
b) 3
c) 4
d) 5
Answer : d

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39. Which of the following is non-saturating?
a) TTL
b) CMOS
c) ECL
d) Both 1 and 2
Answer : c

40. The circuit in the given figure is a .................................gate.

a) positive logic OR gate

b) negative logic OR gate
c) negative logic AND gate
d) positive logic AND gate
Answer : b
Explanation: Since V(1) is lower state than V(0) it is a negative logic circuit. Since diodes are in parallel, it is an OR gate.

41. Algebra of logic is termed as

a) Numerical logic
b) Boolean algebra
c) Arithmetic logic
d) Boolean number
Answer: c
Explanation: The variables that can have two discrete values False(0) and True(1) and the operations of logical significance are dealt with
Boolean algebra.

42. Boolean algebra can be used

a) For designing of the digital computers
b) In building logic symbols
c) Circuit theory
d) Building algebraic functions
Answer: a
Explanation: For designing digital computers and building different electronic circuits boolean algebra is accepted widely

43. What is the definition of Boolean functions?

a) An arithmetic function with k degrees such that f:Y–>Yk
b) A special mathematical function with n degrees such that f:Yn–>Y
c) An algebraic function with n degrees such that f:Xn–>X
d) A polynomial function with k degrees such that f:X2–>Xn
Answer: b
Explanation: A Boolean function is a special mathematical function with n degrees and where Y = {0,1} is the Boolean domain with being a non-
negative integer. It helps in describing the way in which the Boolean output is derived from Boolean inputs.

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 44. F(X,Y,Z,M) = X`Y`Z`M`. The degree of the function is
a) 2
b) 5
c) 4
d) 1
Answer: c
Explanation: This is a function of degree 4 from the set of ordered pairs of Boolean variables to the set {0,1}.

45. A value is represented by a Boolean expression.

a) Positive
b) Recursive
c) Negative
d) Boolean
Answer: d
Explanation: A Boolean value is given by a Boolean expression which is formed by combining Boolean variables and logical connectives.

46. Which of the following is a Simplification law?

a) M.(~M+N) = M.N
b) M+(N.O) = (M+N)(M+O)
c) ~(M+N) = ~M.~N
d) M.(N.O) = (M.N).O
Answer: a
Explanation: By Simplification Law we can have X.(~X+Y) = X.Y and X+(~X.Y) = X+Y. By, De‘ Morgan‘s law ~(X+Y) =
~X.~Y. By commutative law we can say that A.(B.C) = (A.B).C.

47. What are the canonical forms of Boolean Expressions?

a) OR and XOR
b) NOR and XNOR
c) MAX and MIN
d) SOM and POM
Answer: d
Explanation: There are two kinds of canonical forms for a Boolean expression-> 1)sum of minterms(SOM) form and 2)product of
maxterms(SOM) form.

48. Which of the following is/are the universal logic gates?

a) OR and NOR
b) AND
c) NAND and NOR
d) NOT
Answer: c
Explanation: NAND and NOR gates are known as the universal logic gates. A universal gate is a gate which can implement any Boolean
function without the help of 3 basic gate types.

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49. The logic gate that provides high output for same inputs
a) NOT
b) X-NOR
c) AND
d) XOR
Answer: b
Explanation: The logic gate which gives high output for the same inputs, otherwise low output is known as X-NOR or Exclusive NOR gate.

50. The of all the variables in direct or complemented from is a maxterm.

a) addition
b) product
c) moduler
d) subtraction
Answer: a
Explanation: The Boolean function is expressed as a sum of the 1-minterms and the inverse of function is represented as 0-minterms.

51. A Karnaugh map (K-map) is an abstract form of diagram organized as a matrix of squares.
a) Venn Diagram
b) Cycle Diagram
c) Block diagram
d) Triangular Diagram
Answer: a
Explanation: A Karnaugh map (K-map) is an abstract form of Venn diagram organized as a matrix of squares, where each square represents
a Maxterm or a Minterm.

52. There are cells in a 4-variable K-map.

a) 12
b) 16
c) 18
d) 8
Answer: b
Explanation: There are 16 = (24) cells in a 4-variable K-map.

53. The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ = 1.
a) Impact
b) Non Impact
c) Force
d) Complementarity
Answer: b
Explanation: The given expression A +A‘ = 1 is based on non-impact unifying theorem.

54. Each product term of a group, w’.x.y’ and w.y, represents the in that group.
a) Input
b) POS
c) Sum-of-Minterms
d) Sum of Maxterms
Answer: c
Explanation: In a minterm, each variable w, x or y appears once either as the variable itself or as the inverse. So, the given expression
satisfies the property of Sum of Minterm.
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55. The prime implicant which has at least one element that is not present in any other implicant is known as

a) Essential Prime Implicant

b) Implicant
c) Complement
d) Prime Complement
Answer: a
Explanation: Essential prime implicants are prime implicants that cover an output of the function that no combination of other prime implicants is
able to cover.

56. Product-of-Sums expressions can be implemented using

a) 2-level OR-AND logic circuits
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits
d) Both 2-level OR-AND and NOR logic circuits
Answer: d
Explanation: Product-of-Sums expressions can be implemented using 2-level OR-AND & NOR logic circuits.

57. Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible product term ofthe given
a) Function
b) Value
c) Set
d) Word
Answer: a
Explanation: Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible product term of the given function.

58. Don’t care conditions can be used for simplifying Boolean expressions in
a) Registers
b) Terms
c) K-maps
d) Latches
Answer: c
Explanation: Don‘t care conditions can be used for simplifying Boolean expressions in K-maps which helps in pairing with 1/0.

59. It should be kept in mind that don’t care terms should be used along with the terms that are present in

a) Minterms
b) Expressions
c) K-Map
d) Latches
Answer: a
Explanation: It should be kept in mind that don‘t care terms should be used along with the terms that are present in minterms as well as
maxterms which reduces the complexity of the boolean expression.

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60. Using the transformation method you can realize any POS realization of OR-AND with only.
a) XOR
b) NAND
c) AND
d) NOR
Answer: d
Explanation: Using the transformation method we can realize any POS realization of OR-AND with only NOR.

61. There are many situations in logic design in which simplification of logic expression is possible in terms of XOR and
operations.
a) X-NOR
b) XOR
c) NOR
d) NAND
Answer: a
Explanation: There are many situations in logic design in which simplification of logic expression is possible in terms of XOR and XNOR
operations.
Expression of XOR : AB‘ + A‘B
Expression of XNOR : AB + A‘B‘

62. These logic gates are widely used in design and therefore are available in IC form.
a) Sampling
b) Digital
c) Analog
d) Systems
Answer: b
Explanation: These logic gates(XOR, XNOR, NOR) are widely used in digital design and therefore are available in IC form as digital circuits
deal with data transmission in the form of binary digits.

63. In case of XOR/XNOR simplification we have to look for the following

a) Diagonal Adjacencies
b) Offset Adjacencies
c) Straight Adjacencies
d) Both diagonal and offset adjencies
Answer: d
Explanation: In case of XOR/XNOR simplification we have to look for the following diagonal and offset adjacencies. XOR gives output 1 when odd
number of 1s are present in input while XNOR gives output 1 when even number of 1s or all 0s are present in input.

64. Entries known as mapping.

a) Diagonal
b) Straight
c) K
d) Boolean
Answer: a
Explanation: Entries known as diagonal mapping. The diagonal mapping holds true when for any relation, there is a projection of product
on the factor.

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65. Which statement below best describes a Karnaugh map?
a) It is simply a rearranged truth table
b) The Karnaugh map eliminates the need for using NAND and NOR gates
c) Variable complements can be eliminated by using Karnaugh maps
d) A Karnaugh map can be used to replace Boolean rules
Answer: a
Explanation: K-map is simply a rearranged truth table. It is a pictorial representation of truth table having a specific number of cells or
squares, where each cell represents a Maxterm or a Minterm.

66. Which of the examples below expresses the commutative law of multiplication?
a) A + B = B + A
b) A • B = B + A
c) A • (B • C) = (A • B) • C
d) A • B = B • A
Answer: d
Explanation: The commutative law of multiplication is (A * B) = (B * A). The commutative
law of addition is (A + B) = (B + A).

67. The Boolean expression Y = (AB)’ is logically equivalent to what single gate?
a) NAND
b) NOR
c) AND
d) OR
Answer: a
Explanation: If A and B are the input for AND gate the output is obtained as AB and after inversion we get (AB)‘, which is the expression of NAND
gate. NAND gate produces high output when any of the input is 0 and produces low output when all inputs are 1.

68. The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is referredto as
a) A Karnaugh map
b) DeMorgan’s second theorem
c) The commutative law of addition
d) The associative law of multiplication
Answer: b
Explanation: DeMorgan‘s Law: ~(P+Q) <=> (~P).(~Q) Also,
~(P.Q) <=> (~P)+(~Q).

69. The systematic reduction of logic circuits is accomplished by

a) Symbolic reduction
b) TTL logic
c) Using Boolean algebra
d) Using a truth table
Answer: c
Explanation: The systematic reduction of logic circuits is accomplished by using boolean algebra.

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 70. Each “1” entry in a K-map square represents
a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON‘T CARE condition for all possible input truth table combinations
Answer: a
Explanation: Each ―1‖ entry in a K-map square represents a HIGH for each input truth table condition that produces a HIGH output. Thus, it represents
a minterm.

71. Each “0” entry in a K-map square represents

a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON‘T CARE condition for all possible input truth table combinations
Answer: c
Explanation: Each ―0‖ entry in a K-map square represents a LOW output for all possible HIGH input conditions. Thus, it represents Maxterm.

72. Which of the following statements accurately represents the two BEST methods of logic circuit simplification?
a) Actual circuit trial and error evaluation and waveform analysis
b) Karnaugh mapping and circuit waveform analysis
c) Boolean algebra and Karnaugh mapping
d) Boolean algebra and actual circuit trial and error evaluation
Answer: c
Explanation: The two BEST methods of logic circuit simplification are Boolean algebra and Karnaugh mapping. Boolean Algebra uses the Laws of
Boolean Algebra for minimization of Boolean expressions while Karnaugh Map is a pictorial representation and reduction of the Boolean
expression.

73. Looping on a K-map always results in the elimination of

a) Variables within the loop that appear only in their complemented form
b) Variables that remain unchanged within the loop
c) Variables within the loop that appear in both complemented and uncomplemented form
d) Variables within the loop that appear only in their uncomplemented form
Answer: c
Explanation: Looping on a K-map always results in the elimination of variables within the loop that appear in both complemented and uncomplemented
form.

74. Which of the following expressions is in the sum-of-products form?

a) (A + B)(C + D)
b) (A * B)(C * D)
c) A* B *(CD)
d) A * B + C * D
Answer: d
Explanation: Sum of product means that it is the sum of all product terms. Thus, the number is multiplied first and then it is added: A * B + C * D.

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 75. Which of the following is an important feature of the sum-of-products form of expressions?
a) All logic circuits are reduced to nothing more than simple AND and OR operations
b) The delay times are greatly reduced over other forms
c) No signal must pass through more than two gates, not including inverters
d) The maximum number of gates that any signal must pass through is reduced by a factor of two
Answer: a
Explanation: An important feature of the sum-of-products form of expressions in the given option is that all logic circuits are reduced to nothing
more than simple AND and OR operations. Sum Of Product means it is the sum of product terms containing variables in complemented as well as
uncomplemented forms.

76. In boolean algebra, the OR operation is performed by which properties?

a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
Answer: d
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C & A*(B*C) = (A*B)*C. The expression for
Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.

77. The expression for Absorption law is given by

a) A + AB = A
b) A + AB = B
c) AB + AA‘ = A
d) A + B = B + A
Answer: a
Explanation: The expression for Absorption Law is given by: A+AB = A. Proof: A + AB =
A(1+B) = A (Since 1 + B = 1 as per 1‘s Property).

78. According to boolean law: A + 1 = ?

a) 1
b) A
c) 0
d) A‘
Answer: a
Explanation: A + 1 = 1, as per 1‘s Property.

79. The involution of A is equal to

a) A
b) A‘
c) 1
d) 0
Answer: a
Explanation: The involution of A means double inversion of A (i.e. A‖) and is equal to A.Proof: ((A)‘)‘ = A

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80. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
Answer: d
Explanation: A(A + B) = AA + AB (By Distributive Property) = A + AB (A.A = A By Commutative Property) = A(1 + B) = A*1 (1 + B = 1 by 1‘s
Property) = A.

81. DeMorgan’s theorem states that

a) (AB)’ = A’ + B’
b) (A + B)‘ = A‘ * B
c) A‘ + B‘ = A‘B‘
d) (AB)‘ = A‘ + B
Answer: a
Explanation: The DeMorgan‘s law states that (AB)‘ = A‘ + B‘ & (A + B)‘ = A‘ * B‘, as per the Dual Property.

82. (A + B)(A’ * B’) = ?

a) 1
b) 0
c) AB
d) AB‘
Answer: b
Explanation: The DeMorgan‘s law states that (AB)‘ = A‘ + B‘ & (A + B)‘ = A‘ * B‘, as per the Dual Property.

83. Complement of the expression A’B + CD’ is

a) (A‘ + B)(C‘ + D)
b) (A + B’)(C’ + D)
c) (A‘ + B)(C‘ + D)
d) (A + B‘)(C + D‘)
Answer: b
Explanation: (A‘B + CD‘)‘ = (A‘B)'(CD‘)‘ (By DeMorgan‘s Theorem) = (A‖ + B‘)(C‘ + D‖) (By DeMorgan‘s Theorem) = (A +B‘)(C‘ + D).

84. Simplify Y = AB’ + (A’ + B)C.

a) AB’ + C
b) AB + AC
c) A‘B + AC‘
d) AB + A
Answer: a
Explanation: Y = AB‘ + (A‘ + B)C = AB‘ + (AB‘)‘C = (AB‘ + C)( AB‘ + AB‘) = (AB‘ + C).1 = (AB‘ + C).

85. The boolean function A + BC is a reduced form of

a) AB + BC
b) (A + B)(A + C)
c) A‘B + AB‘C
d) (A + C)B
Answer: b
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC (By Commutative Property) = A(1 + C + B) + BC
= A + BC (1 + B + C =1 By 1‘s Property).
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86. What is the use of Boolean identities?
a) Minimizing the Boolean expression
b) Maximizing the Boolean expression
c) To evaluate a logical identity
d) Searching of an algebraic expression
Answer: a
Explanation: Boolean identities are used for minimizing the Boolean expression and transforming into an equivalent expression.

87. is used to implement the Boolean functions.

a) Logical notations
b) Arithmetic logics
c) Logic gates
d) Expressions
Answer: c
Explanation: To implement a Boolean function logic gates are used. Basic logic gates are AND, OR and NOT.

88. Inversion of single bit input to a single bit output using

a) NOT gate
b) NOR gate
c) AND gate
d) NAND gate
Answer: a
Explanation: A NOT gate is used to invert a single bit input (say A) to a single bit of output (~A).

89. There are numbers of Boolean functions of degree n.

a) n
b) 2(2*n)
c) n3
d) n(n*2)
Answer: b
Explanation: There are 2n different n-tuples of 0‘s and 1‘s. A Boolean function is an assignment of 0‘s or 1‘s to each of these 2 n different n-
tuples. Hence, there are 2(2*n) different Boolean functions.

90. A is a Boolean variable.

a) Literal
b) String
c) Keyword
d) Identifier
Answer: a
Explanation: A literal is a Boolean variable or its complement. A maxterm is a sum of n literals and a minterm is a product of n literals.

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91. Minimization of function F(A,B,C) = A*B*(B+C) is
a) AC
b) B+C
c) B`
d) AB
Answer: d
Explanation: AB(B+C)
= ABB + ABC [Applying distributive rule]
= AB + ABC [Applying Idempotent law]
= AB (1+C)
= AB*1 [As, 1+C=1]

92. The set for which the Boolean function is functionally complete is
a) {*, %, /}
b) {., +, -}
c) {^, +, -}
d) {%, +, *}
Answer: b
Explanation: A Boolean function is represented by using three operators ., +, -. We can find a smaller set of functionally
complete operator if one of the three operators of this set can b expressed in terms of the other two.

93. (X+Y`)(X+Z) can be represented by

a) (X+Y`Z)
b) (Y+X`)
c) XY`
d) (X+Z`)
Answer: a
Explanation: (X+Y`) (X+Z)
= XX + XZ + XY`+ Y`Z
= X + XZ + XY`+ Y`Z
= X (1+Z) + XY`+ Y`Z
= X.1 + XY`+ Y`Z
= X (1+Y`) + Y`Z
= X + Y`Z.

94. is a disjunctive normal form.

a) product-of-sums
b) product-of-subtractions
c) sum-of-products
d) sum-of-subtractions
Answer: c
Explanation: The sum of minterms that represents the function is called the sum-of-products expansion or the disjunctive normal form. A Boolean sum
of minterms has the value 1 when exactly one of the minterms in the sum has the value 1. It has the value 0 for all other combinations of values
of the variables.

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95. a ⊕ b =
a) (a+b)(a`+b`)
b) (a+b`)
c) b`
d) a` + b`
Answer: a Explanation: a
⊕b
= a`b + ab`
= a`b+aa` + bb` + ab` [As, a*a` = 0 and b*b` = 0]
= a`(a+b) + b`(a+b)
= (a+b)(a`+b`).

96. In parts of the processor, adders are used to calculate

a) Addresses
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned
Answer: d
Explanation: Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used to calculate addresses, table
indices, increment and decrement operators, and similar operations.

97. Total number of inputs in a half adder is

a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: Total number of inputs in a half adder is two. Since an EXOR gates has 2 inputs and carry is connected with the input of EXOR
gates. The output of half-adder is also 2, them being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.

98. In which operation carry is obtained?

a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
Answer: b
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st
addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 – 1 = 1 (borrow 1).

99. If A and B are the inputs of a half adder, the sum is given by
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: c
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is given by A AND B.

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100. If A and B are the inputs of a half adder, the carry is given by
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: a
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the sum is given by A XOR B.

101. Half-adders have a major limitation in that they cannot

a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Answer: c
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be
chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and
carry both being high.

102. The difference between half adder and full adder is

a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned
Answer: c
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference between them, while both have two outputs SUM
and CARRY.

103. If A, B and C are the inputs of a full adder then the sum is given by
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Answer: c
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.

104. If A, B and C are the inputs of a full adder then the carry is given by
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Answer: a
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B) AND C, which is equivalent to (A AND
B) OR (B AND C) OR (C AND A).

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105. How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Answer: b
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided using half adder. Otherwise,
configuration of full adder would require 3 AND, 2 OR and 2 EXOR.

106. A code converter is a logic circuit that

a) Inverts the given input
b) Converts into decimal number
c) Converts data of one type into another type
d) Converts to octal
Answer: c
Explanation: A code converter is a logic circuit that changes data presented in one type of binary code to another type of binary code.

107. Use the weighting factors to convert the following BCD numbers to binary
0101 0011 & 0010 0110 1000

a) 01010011 001001101000
b) 11010100 100001100000
c) 110101 100001100
d) 101011 001100001
Answer: c
Explanation: Firstly, convert every 4 sets of binary to decimal from the given: 0101=5, 0011=3. Then convert 53 to binary, which will give
110101. Again, do the same with the next 4 set of binary digits.

108. The primary use for Gray code is

a) Coded representation of a shaft’s mechanical position
b) Turning on/off software switches
c) To represent the correct ASCII code to indicate the angular position of a shaft on rotating machinery
d) To convert the angular position of a shaft on rotating machinery into hexadecimal code
Answer: a
Explanation: Gray code is useful because only one bit changes at a time, which is implemented easily in Coded representation of a shaft‘s
mechanical position. In Gray Code, every sequence of successive bits differs by 1 bit only.

109. The primary use for Gray code is

a) Coded representation of a shaft’s mechanical position
b) Turning on/off software switches
c) To represent the correct ASCII code to indicate the angular position of a shaft on rotating machinery
d) To convert the angular position of a shaft on rotating machinery into hexadecimal code
Answer: a
Explanation: Gray code is useful because only one bit changes at a time, which is implemented easily in Coded representation of a shaft‘s
mechanical position. In Gray Code, every sequence of successive bits differs by 1 bit only.

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110. Code is a symbolic representation of
a) Discrete information
b) Continuous information
c) Decimal information into binary
d) Binary information into decimal
Answer: a
Explanation: Code is a symbolic representation of discrete information. Codes can be anything like numbers, letter or words, written in terms
of group of symbols.

111. One way to convert BCD to binary using the hardware approach is
a) With MSI IC circuits
b) With a keyboard encoder
c) With an ALU
d) UART
Answer: a
Explanation: One way to convert BCD to binary using the hardware approach is MSI IC (i.e. medium scale integration) circuits.

112. Why is the Gray code more practical to use when coding the position of a rotating shaft?
a) All digits change between counts
b) Two digits change between counts
c) Only one digit changes between counts
d) Alternate digit changes between counts
Answer: c
Explanation: The Gray code is more practical to use when coding the position of a rotating shaft because only one digit changes between
counts that is reflected to the next count.

113. Reflected binary code is also known as

a) BCD code
b) Binary code
c) ASCII code
d) Gray Code
Answer: d
Explanation: The reflected binary code is also known as gray code because one digit reflected to the next bit. In Gray Code, every sequence
of successive bits differs by 1 bit only.

114. Why do we use gray codes?

a) To count the no of bits changes
b) To rotate a shaft
c) Error correction
d) Error Detection
Answer: c
Explanation: Today, Gray codes are widely used to facilitate error correction in digital communications such as digital terrestrial television
and some cable TV systems.

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 115. Earlier, reflected binary codes were applied to
a) Binary addition
b) 2‘s complement
c) Mathematical puzzles
d) Binary multiplication
Answer: c
Explanation: The reflected binary code is also known as gray code because one digit reflected to the next bit. In Gray Code, every sequence of
successive bits differs by 1 bit only. Reflected binary codes were applied to mathematical puzzles before they became known to engineers.

116. The binary representation of BCD number 00101001 (decimal 29) is

a) 0011101
b) 0110101
c) 1101001
d) 0101011
Answer: a
Explanation: The given BCD number 00101001 has three 1s. So, it can be rewritten as 0000001-1, 0001000-8, 0010100-20 and after
addition, we get 0011101 as output.

117. Convert binary number into gray code: 100101.

a) 101101
b) 001110
c) 110111
d) 111001

Answer: c
Explanation: Conversion from Binary To Gray Code:
1 (XOR) 0 (XOR) 0 (XOR) 1 (XOR) 0 (XOR) 1

↓ ↓ ↓ ↓ ↓

1 1 0 1 1 1

118. The de imal number system represents the decimal number in the form of
a) Hexadecimal
b) Binary coded
c) Octal
d) Decimal
Answer: b
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed
number of bits, usually four or eight. Hexadecimal and Octal are number systems having base 16 and 8 respectively.

119. 29 input circuit will have total of

a) 32 entries
b) 128 entries
c) 256 entries
d) 512 entries
Answer: d
Explanation: 29 input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.
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120. BCD adder can be constructed with 3 IC packages each of
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits

Answer: c
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed
number of bits, usually four or eight. BCD adder can be constructed with 3 IC packages. Each of 4- bit adders is an MSI(Medium scale Integration)
function and 3 gates for the correction logic need one SSI (Small Scale Integration) package.

121. The output sum of two decimal digits can be represented in

a) Gray Code
b) Excess-3
c) BCD
d) Hexadecimal
Answer: c
Explanation: The output sum of two decimal digits can be represented in BCD(Binary-coded decimal). Binary-coded decimal (BCD) is a class of
binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight.

122. The addition of two decimal digits in BCD can be done through
a) BCD adder
b) Full adder
c) Ripple carry adder
d) Carry look ahead
Answer: a
Explanation: The addition of two decimal digits in BCD can be done through BCD adder. Every input inserted, in addition by the user converted into
binary and then proceed for the addition. Whereas, Full Adder, Ripple Carry Adder and Carry Look Adder are for the addition of binary bits.

123. 3 bits full adder contains

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
Answer: d
Explanation: 3 bits full adder contains 23 = 8 combinational inputs.

124. The simplified expression of full adder carry is

a) c = xy+xz+yz
b) c = xy+xz
c) c = xy+yz
d) c = x+y+z
Answer: a
Explanation: A full adder is a combinational circuit having 3 inputs and 2 outputs, namely SUM and CARRY. The simplified expression of
full adder carry is c = xy+xz+yz.
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 125. Complement of F’ gives back
a) F‘
b) F
c) FF
d) FF‘
Answer: b
Explanation: Complement means inversion. So, complement of F‘ gives back F, as per the Law of Involution.

126. Decimal digit in BCD can be represented by

a) 1 input line
b) 2 input lines
c) 3 input lines
d) 4 input lines
Answer: d
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of
bits, usually four or eight. Decimal digit in BCD can be represented by 4 input lines.
Since it is constructed with 4-bits.

127. The number of logic gates and the way of their interconnections can be classified as
a) Logical network
b) System network
c) Circuit network
d) Gate network
Answer: a
Explanation: The number of different levels of logic gates is represented in a fashion which is known as a logical network.

128. Half subtractor is used to perform subtraction of

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
Answer: a
Explanation: Half subtractor is a combinational circuit which is used to perform subtraction of two bits, namely minuend and subtrahend and
produces two outputs, borrow and difference.

129. For subtracting 1 from 0, we use to take a from neighbouring bits.

a) Carry
b) Borrow
c) Input
d) Output

Answer: b
Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because carry is taken into consideration during
addition process.

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130. How many outputs are required for the implementation of a subtractor?
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: There are two outputs required for the implementation of a subtractor. One for the difference and another for borrow.

131. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
Answer: a
Explanation: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In both of the situation subtractor gives 0 as the
output.

132. Let A and B is the input of a subtractor then the output will be
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
Answer: a
Explanation: The subtractor has two outputs BORROW and DIFFERENCE. Since the difference output of a subtractor is given by AB‘ + BA‘ and this
is the output of a XOR gate. So, the final difference output is AB‘ + BA‘.

133. Let A and B is the input of a subtractor then the borrow will be
a) A AND B‘
b) A’ AND B
c) A OR B
d) A AND B
Answer: b
Explanation: The borrow of a subtractor is received through AND gate whose one input is inverted. On that basis the borrow will be (A‘ AND
B).

134. What does minuend and subtrahend denotes in a subtractor?

a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits
Answer: c
Explanation: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the two inputs of a subtractor then A is called
minuend and B as subtrahend.

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135. Full subtractor is used to perform subtraction of
a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
Answer: b
Explanation: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit, subtrahend bit and borrow from the previous stage.
However, it also produces 2 outputs BORROW and DIFFERENCE.

136. The full subtractor can be implemented using

a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate
Answer: b
Explanation: A full subtractor has 3 input bits and two outputs bits BORROW and DIFFERENCE. The full subtractor can be implemented using
two half subtractors and an OR gate.

137. The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
Answer: b
Explanation: The difference output of a subtractor is given by (if A, B and X are the inputs) A XOR B XOR X.

138. The output of a full subtractor is same as

a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
Answer: b
Explanation: The sum and difference output of a full adder and a full subtractor are same. If A, B and C are the input of a full adder and a full
subtractor then the output will be given by (A XOR B XOR C), respectively.

139. The code where all successive numbers differ from their preceding number by single bit is
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Answer: d
Explanation: The code where all successive numbers differ from their preceding number by single bit is gray code. It is an unweighted code. The
most important characteristic of this code is that only a single bit change occurs when going from one code number to next. BCD Code is one in
which decimal digits are represented by a group of 4-bits each, whereas, in Excess-3 Code, the decimal numbers are incremented by 3 and then
written in their BCD format.

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 140. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
Answer: c
Explanation: 4 to 16 line decoder as the minte ms are ranging from 1 to 14.

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04- Sequential Logic circuit Marks:-18
Content of Chapter:-
4.1 Basic memory cell:RS latch using NAND and NOR 4.2Triggering Methods:
Edge trigger and level trigger.
4.3 SR Flip Flop: SR –Flipflop ,clocked SR flip flop with preset and clear ,drawbacks of SR flip flop
4.4 JK flipflops: Clocked JK Flopflop with Prest and clear racearound condition in JK flip flop, Master slave JK flip flop, D & Ttype
flipflop Excitation table of flip flops ,Block schematic and function table of IC 7474,7475 4.5Shift register:Logic diagram of 4-bit Shift
register-SISO,PISO,PIPO,4 bit Universal shift register
4.6Counters :Asynchronous counter:4 Bit Ripple Counter,4 Bit up/downCounter,modulus of counterSynchronous counter:Design of 4 bit
synchronous Up/Down counter

1. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which
configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are directly connected to the
other‘s output. Such types of structure is called cross coupling and due to which latches remain in the latched condition.

2. One example of the use of an S-R flip-flop is as

a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused
during the switching of electronic devices.

3. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or Undefined State occurs
at both S and R being at 1.

4. When both inputs of a J-K flip-flop cycle, the output will

a) Be invalid
b) Change
c) Not change
d) Toggle
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle, it becomes
as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K flip- flop has 4 stable states: Latch, Reset, Set
and Toggle.

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5. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGHAnswer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. In a state of
clock high, when D is high the output Q also high, if D is ‗0‘ then output is also zero. Like SR flip-flop, the D-flip-flop also have an
invalid state at both inputs being 1.

6. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross coupling means the
output of second gate is fed to the input of first gate and vice-versa.

7. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past
outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of
time depends only on the present input but also on the past outputs are called sequential circuits. Unlike sequential circuits, if output
depends only on the present state, then it‘s known as combinational circuits.

8. Whose operations are more faster among the following?

a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since the combinational circuits do not require
memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. Latches and
Flip-flops come under sequential circuits.

9. How many types of sequential circuits are?

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked.
Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits
function in the absence of a clock signal.

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10. The sequential circuit is also called
a) Flip-flop
b) Latch
c) Strobe
d) Adder
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit
of information.

11. The basic latch consists of

a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the second output Q‘ = 1
and vice versa.

12. In S-R flip-flop, if Q = 0 the output is said to be

a) Set
b) Reset
c) Previous state
d) Current state
Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.

13. The output of latches will remain in set/reset untill

a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don‘t get any pulse more
d) The pulse is edge-triggered
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change thestate.

14. What is a trigger pulse?

a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation Answer:
a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.

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15. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionalityAnswer: c
Explanation: The cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path.
For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits. Moreover, they are referred to
as asynchronous because they function in the absence of a clock pulse.This set of Digital Electronics/Circuits Multiple Choice
Questions & Answers (MCQs) focuses on ―Triggering of Flip Flops‖.

16. The characteristic equation of J-K flip-flop is

a) Q(n+1)=JQ(n)+K‘Q(n)
b) Q(n+1)=J‘Q(n)+KQ'(n)
c) Q(n+1)=JQ'(n)+KQ(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
Answer: d
Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table.
The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ'(n)+K‘Q(n).

17. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as

a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
Answer: c
Explanation: In J-K flip-flop, if both the inputs are same then it behaves like T flip-flop.

18. In J-K flip-flop, the function K=J is used to realize

a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
Answer: c
Explanation: T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.

19. The only difference between a combinational circuit and a flip-flop is that
a) The flip-flop requires previous state
b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) The flip-flop depends on the past as well as present states Answer: c
Explanation: Both flip-flop and latches are memory elements with clock/control inputs. They depend on the past as well as present
states. Whereas, in case of combinational circuits, they only depend on the present state.
20. How many stable states combinational circuits have?
a) 3
b) 4
c) 2
d) 5
Answer: c
Explanation: The two stable states of combinational circuits are 1 and 0. Whereas, in flip-flops there is an additional state
known as Forbidden State.
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21. The flip-flop is only activated by
a) Positive edge trigger
b) Negative edge trigger
c) Either positive or Negative edge trigger
d) Sinusoidal trigger
Answer: c
Explanation: Flip flops can be activated with either a positive or negative edge trigger.

22. The S-R latch composed of NAND gates is called an active low circuit because
a) It is only activated by a positive level trigger
b) It is only activated by a negative level trigger
c) It is only activated by either a positive or negative level trigger
d) It is only activated by sinusoidal trigger
Answer: b
Explanation: Active low indicates that only an input value of 0 sets or resets the circuit.

23. Both the J-K & the T flip-flop are derived from the basic
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
Answer: b
Explanation: The SR latch is the basic block for the D latch/flip flop from which the JK and T flip flops are derived. A latch is
similar to a flip-flop, only without a clock input.

24. The flip-flops which has not any invalid states are
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
Answer: d
Explanation: Unlike the SR latch, these circuits have no invalid states. The SR latch or flip-flop has an invalid or forbidden state
where no output could be determined.

25. What does the triangle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Edge triggered
c) Both Level enabled & Edge triggered
d) Level triggered
Answer: b
Explanation: The triangle on the clock input of a J-K flip-flop mean edge triggered. Whereas the absence of triangle symbol implies that
the flip-flop is level-triggered.
26. What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
Answer: c
Explanation: The circle on the clock input of a J-K flip-flop mean negative edge triggered. Whereas the absence of triangle
symbol implies that the flip-flop is level-triggered.
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27. What does the direct line on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
Answer: d
Explanation: The direct line on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol
implies that the flip-flop is edge-triggered.

28. What does the half circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
Answer: d
Explanation: The half circle on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol
implies that the flip-flop is edge-triggered.

29. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave
Answer: d
Explanation: As one flip flop is used so there are two states available. So, 20/2 = 10Hz frequency is available at the output.

30. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
Answer: C
Explanation: Edge triggered device will follow the input condition when there is a transition. It is said to be positive edge triggered
when transition occurs from LOW to HIGH. While it is said to be a negative edge triggered when a transition occurs from HIGH
to LOW.

31. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration
feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are directly connected to the
other‘s output. Such types of structure is called cross coupling and due to which latches remain in the latched condition.

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32. One example of the use of an S-R flip-flop is as
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused
during the switching of electronic devices.

33. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or Undefined State occurs
at both S and R being at 1.

34. When both inputs of a J-K flip-flop cycle, the output will
a) Be invalid
b) Change
c) Not change
d) Toggle
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle, it becomes
as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K flip- flop has 4 stable states: Latch, Reset, Set
and Toggle.

35. Which of the following is correct for a gated D-type flip-flop?

a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGHAnswer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. In a state of
clock high, when D is high the output Q also high, if D is ‗0‘ then output is also zero. Like SR flip-flop, the D-flip-flop also have an
invalid state at both inputs being 1.

36. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross coupling means the
output of second gate is fed to the input of first gate and vice-versa.

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37. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are
called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of
time depends only on the present input but also on the past outputs are called sequential circuits. Unlike sequential circuits, if output
depends only on the present state, then it‘s known as combinational circuits.

38. Whose operations are more faster among the following?

a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since the combinational circuits do not require
memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. Latches and
Flip-flops come under sequential circuits.

39. How many types of sequential circuits are?

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked.
Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits
function in the absence of a clock signal.

40. The sequential circuit is also called

a) Flip-flop
b) Latch
c) Strobe
d) Adder
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of
information.

41. The basic latch consists of

a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the second output Q‘ = 1
and vice versa.

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42. In S-R flip-flop, if Q = 0 the output is said to be
a) Set
b) Reset
c) Previous state
d) Current state
Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.The output of latches will remain in set/reset untill
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don‘t get any pulse more
d) The pulse is edge-triggered
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change thestate.

43. What is a trigger pulse?

a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation Answer:
a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.

44. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionalityAnswer: c
Explanation: The cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path.
For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits. Moreover, they are referred to
as asynchronous because they function in the absence of a clock pulse.

45. Based on how binary information is entered or shifted out, shift registers are classified into
categories.
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: The registers in which data can be shifted serially or parallelly are known as shift registers. Based on how binary
information is entered or shifted out, shift registers are classified into 4 categories, viz., Serial-In/Serial-Out(SISO), Serial-
In/Parallel-Out (SIPO), Parallel-In/Serial-Out (PISO), Parallel- In/Parallel-Out (PIPO).

46. The full form of SIPO is

a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out
Answer: a
Explanation: SIPO is always known as Serial-in Parallel-out.

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47. A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
Answer: c
Explanation: A shift register can shift it‘s data either left or right. The universal shift register is capable of shifting data left, right
and parallel load capabilities.

48. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
Answer: d
Explanation: Because no other flip-flops are connected with the output Q, therefore one can use the Q out of each FF to take
out parallel data.

49. What is meant by the parallel load of a shift register?

a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
Answer: a
Explanation: At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus input is definitely 1.

50. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state
01110. After three clock pulses, the register contains
a) 01110
b) 00001
c) 00101
d) 00110
Answer: c
Explanation: LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.

51. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit
pattern after the second clock pulse? (Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111
Answer: c
Explanation: In Serial-In/Serial-Out shift register, data will be shifted one at a time with every clock pulse. Therefore,
Wait | Store 1100 |
0000
110 | 0000 1st clock
11 | 0000 2nd clock.
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52. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four
clock pulses, the register contains
a) 0000
b) 1111
c) 0111
d) 1000
Answer: c
Explanation: In Serial-In/Parallel-Out shift register, data will be shifted all at a time with every clock pulse. Therefore,
Wait | Store 0111 |
0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk X |
1111 4th clk.

53. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
Answer: b
Explanation: f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be loaded = 8 * 5 = 40 micro-sec.

54. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of
a) 16 us
b) 8 us
c) 4 us
d) 2 us
Answer: c
Explanation: One clock period is = (1⁄2) micro-s = 0.5 microseconds. In serial transmission, data enters one bit at a time. So, the
total delay = 0.5*8 = 4 micro seconds time is required to transmit information of 8 bits.

55. In digital logic, a counter is a device which

a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) Counts the number of inputs
Answer: b
Explanation: In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal.

56. A counter circuit is usually constructed of

a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade formAnswer: c
Explanation: A counter circuit is usually constructed of a number of flip-flops connected in cascade. Preferably, JK Flip-flops are
used to construct counters and registers.

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57. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‗n‘
number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
Answer: c
Explanation: The maximum possible range of bit-count specifically in n-bit binary counter consisting of ‗n‘ number of flip-flops is 0 to
2n-1. For say, there is a 2-bit counter, then it will count till 22-1 = 3. Thus, it will count from 0 to 3.

58. How many types of the counter are there?

a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and multi-mode & (iii)modulus counter.
These further can be subdivided into Ring Counter, Johnson Counter, Cascade Counter, Up/Down Counter and such like.

59. A decimal counter has states.

a) 5
b) 10
c) 15
d) 20
Answer: b
Explanation: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is also known as Decade Counter
counting from 0 to 9.

60. Ripple counters are also called

a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
Answer: b
Explanation: Ripple counters are also called asynchronous counter. In Asynchronous counters, only the first flip-flop is connected
to an external clock while the rest of the flip-flops have their preceding flip-flop output as clock to them.

61. Synchronous counter is a type of

a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
Answer: c
Explanation: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous Counters, the clock pulse is supplied to
all the flip-flops simultaneously.

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62. Three decade counter would have
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
Answer: b
Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it would require 3 BCD counters. Thus,
a three decade counter will count from 0 to 29.
63. BCD counter is also known as
a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
Answer: b
Explanation: BCD counter is also known as decade counter because both have the same number of stages and both count from 0
to 9.
64. The parallel outputs of a counter circuit represent the
a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count
Answer: d
Explanation: The parallel outputs of a counter circuit represent the clock count. A counter counts the number of times an event
takes place in accordance to the clock pulse.

65. A latch is an example of a

a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) 555 timer
Answer: c
Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is one in which the circuit is stable in of two states. It can be
flipped from one state to the other state and vice-versa.
66. Latch is a device with
a) One stable state
b) Two stable state
c) Three stable state
d) Infinite stable states
Answer: b
Explanation: Since a latch works on the principal of bistable multivibrator. A Bistable multivibrator is one in which the circuit stable in either of two
states. It can be flipped from one state to the other state and vice-versa. So a latch has two stable sta

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 67. Why latches are called memory devices?
a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) It can store infinite amount of data
Answer: c
Explanation: Latches can be memory devices, and can store one bit of data for as long as the device is powered. Once dev turned off, the memory
gets refreshed.

68. Two stable states of latches are

a) Astable & Monostable
b) Low input & high output
c) High output & low output
d) Low output & high input
Answer: c
Explanation: A latch has two stable states, following the principle of Bistable Multivibrator. There are two stable states of lat and these states are
high-output and low-output.

69. How many types of latches are

a) 4
b) 3
c) 2
d) 5
Answer: a
Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D latch is a modified form of SR latch whereas, T latch is an
advanced form of JK latch.

70. The full form of SR is

a) System rated
b) Set reset
c) Set ready
d) Set Rated
Answer: b
Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.

71. The SR latch consists of

a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs

Answer: b
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states.

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The diagram of SR latch is shown below:

73. The outputs of SR latch are

a) x and y
b) a and b
c) s and r
d) q and q’
Answer: d
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states. The inputs of SR are s and r while
outputs are q and q‘. It is clear from the diagram:

74. The NAND latch works when both inputs are

a) 1
b) 0
c) Inverted
d) Don‘t cares
Answer: a
Explanation: The NAND latch works when both inputs are 1. Since both of the inputs are inverted in a
NAND latch.

75. The first step of the analysis procedure of SR latch is to

a) label inputs
b) label outputs
c) label states
d) label tables
Answer: b
Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so because the flip flops
have inverting gates inside them, hence in order to have both Q and Q complement available, we have
atleast one output labelled.

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 76. The inputs of SR latch are
a) x and y
b) a and b
c) s and r
d) j and k
Answer: c
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states. The
inputs of SR latch are s and r while outputs are q and q‘. It is clearfrom the diagram:

77. When a high is applied to the Set line of an SR latch, then

a) Q output goes high
b) Q‘ output goes high
c) Q output goes low
d) Both Q and Q‘ go high
[
Answer: a
Explanation: S input of an SR latch is directly connected to the output Q. So when a high is applied Q
output goes high and Q‘ low.

78. When both inputs of SR latches are low, the latch

a) Q output goes high
b) Q‘ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
Answer: c
Explanation: When both inputs of SR latches are low, the latch remains in it‘s present state. There is no
change in output.

79. When both inputs of SR latches are high, the latch goes
a) Unstable
b) Stable
c) Metastable
d) Bistable
Answer: c
Explanation: When both gates are identical and this is ―metastable‖, and the device willbe in an undefined
state for an indefinite period.

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80. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to
which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are
directly connected to the other‘s output. Such types of structure is called cross coupling and due to which
latches remain in the latched condition.

81. One example of the use of an S-R flip-flop is as

a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which is the
unwanted noise caused during the switching of electronic devices.

82. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or
Undefined State occurs at both S and R being at 1.

83. When both inputs of a J-K flip-flop cycle, the output will
a) Be invalid
b) Change
c) Not change
d) Toggle
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1.
After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K
flip-flop has 4 stable states: Latch, Reset, Setand Toggle.

84. Which of the following is correct for a gated D-type flip-flop?

a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Answer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input otherwise reminds
previous output. In a state of clock high, when D is high the output Q also high, if D is ‗0‘ then output is also
zero. Like SR flip-flop, the D-flip-flop also have aninvalid state at both inputs being 1.
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85. A basic S-R flip-flop can be constructed by cross-coupling of which basic logicgates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross
coupling means the output of second gate is fed to the input of firstgate and vice-versa.

86. The logic circuits whose outputs at any instant of time depends only on the present input but also on
the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits whose
outputs at any instant of time depends only on the present input but also on the past outputs are called
sequential circuits. Unlike sequential circuits, if output depends only on the present state, then it‘s known as
combinational circuits.

87. Whose operations are more faster among the following?

a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since the combinational
circuits do not require memory elements whereas the sequential circuits need memory devices to perform
their operations in sequence. Latches and Flip-flops come under sequential circuits.

88. How many types of sequential circuits are?

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous
or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas,
Asynchronous Sequential Circuits function in the absence of a clock signal.

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89. The sequential circuit is also called
a) Flip-flop
b) Latch
c) Strobe
d) Adder
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell, which are capable
of storing one bit of information.
90. The basic latch consists of
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the
second output Q‘ = 1 and vice versa.

91. In S-R flip-flop, if Q = 0 the output is said to be

a) Set
b) Reset
c) Previous state
d) Current state
Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.

92. The output of latches will remain in set/reset untill

a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don‘t get any pulse more
d) The pulse is edge-triggered
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change the
state.

93. What is a trigger pulse?

a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
Answer: a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.

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94. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
Answer: c
Explanation: The cross-coupled connections from the output of one gate to the input of the other gate
constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as asynchronous
sequential circuits. Moreover, they are referred to as asynchronous because they function in the absence of a
clock pulse.

95. What is an ambiguous condition in a NAND based S‘-R‘ latch? a) S‘=0,

R‘=1
b) S‘=1, R‘=0
c) S‘=1, R‘=1
d) S’=0, R’=0
Answer: d
Explanation: In a NAND based S-R latch, If S‘=0 & R‘=0 then both the outputs (i.e. Q &Q‘) goes HIGH and
this condition is called an ambiguous/forbidden state. This state is also known as an Invalid state as the
system goes into an unexpected situation.

96. In a NAND based S‘-R‘ latch, if S‘=1 & R‘=1 then the state of the latch is

a) No change
b) Set
c) Reset
d) Forbidden
Answer: a
Explanation: In a NAND based S‘-R, latch if S‘=1 & R‘=1 then there is no any change in the state. It
remains in its prior state. This state is used for the storage of data.

97.A NAND based S‘-R‘ latch can be converted into S-R latch by placing
a) A D latch at each of its input
b) An inverter at each of its input
c) It can never be converted
d) Both a D latch and an inverter at its input
Answer: d
Explanation: A NAND based S‘-R‘ latch can be converted into S-R latch by placing either a D latch or an
inverter at its input as it‘s operations will be complementary.
98. One major difference between a NAND based S‘-R‘ latch & a NOR based S-R latchis
a) The inputs of NOR latch are 0 but 1 for NAND latch
b) The inputs of NOR latch are 1 but 0 for NAND latch
c) The output of NAND latch becomes set if S‘=0 & R‘=1 and vice versa for NOR latch
d) The output of NOR latch is 1 but 0 for NAND latch
Answer: a
Explanation: Due to inverted input of NAND based S‘-R‘ latch, the inputs of NOR latch are 0 but 1 for
NAND latch
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99.The characteristic equation of S-R latch is
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S‘R + Q(n)R
d) Q(n+1) = S‘R + Q'(n)R
Answer: a
Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to
satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) = (S + Q(n))R‘.

100.The difference between a flip-flop & latch is

a) Both are same
b) Flip-flop consist of an extra output
c) Latches has one input but flip-flop has two
d) Latch has two inputs but flip-flop has one
Answer: c
Explanation: Flip-flop is a modified version of latch. To determine the changes in states, an additional
control input is provided to the latch.

101. How many types of flip-flops are?

a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an advanced version of S-R
flip-flop, while T flip-flop is an advanced version of J-K flip-flop.

102.The S-R flip flop consist of

a) 4 AND gates
b) Two additional AND gates
c) An additional clock input
d) 3 AND gates

Answer: b
Explanation: The S-R flip flop consists of two additional AND gates at the S and R inputsof S-R latch.

103. What is one disadvantage of an S-R flip-flop?

a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State
Answer: d
Explanation: The main drawback of s-r flip flop is invalid output when both the inputs are high, which is
referred to as Invalid State.

Page 62 of 104
104.One example of the use of an S-R flip-flop is as
a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator
Answer: c
Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is referred to as
binary storage element. It functions as memory storage during the No Change State.

105.When is a flip-flop said to be transparent?

a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) When the Q output is complementary of the input
Answer: b
Explanation: Flip-flop have the property of responding immediately to the changes in its inputs. This
property is called transparency.

106.On a positive edge-triggered S-R flip-flop, the outputs reflect the input conditionwhen
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW

Answer: c
Explanation: Edge triggered device will follow when there is transition. It is a positive edge triggered when
transition takes place from low to high, while, it is negative edgetriggered when the transition takes place
from high to low.

107.What is the hold condition of a flip-flop?

a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active
Answer: b
Explanation: The hold condition in a flip-flop is obtained when both of the inputs are LOW. It is the No
Change State or Memory Storage state if a flip-flop.

108.If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and thenthe R input goes
to 0, the latch will be
a) SET
b) RESET
c) Clear
d) Invalid
Answer: b
Explanation: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no change. So, it
remains in reset. If S=1, R=0, the flip flop is at the set condition.

Page 63 of 104
109.The circuit that is primarily responsible for certain flip-flops to be designated asedge-triggered is
the
a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit
Answer: a
Explanation: The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered
is the edge-detection circuit.

110. The characteristic equation of J-K flip-flop is

a) Q(n+1)=JQ(n)+K‘Q(n)
b) Q(n+1)=J‘Q(n)+KQ'(n)
c) Q(n+1)=JQ'(n)+KQ(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
Answer: d
Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to
satisfy the truth table. The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ'(n)+K‘Q(n).

111.In a J-K flip-flop, if J=K the resulting flip-flop is referred to as

a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
Answer: c
Explanation: In J-K flip-flop, if both the inputs are same then it behaves like T flip-flop.

112. In J-K flip-flop, the function K=J is used to realize

a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop

Answer: c
Explanation: T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work asT flip-flop.

113.The only difference between a combinational circuit and a flip-flop is that

a) The flip-flop requires previous state

b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) The flip-flop depends on the past as well as present statesAnswer: c
Explanation: Both flip-flop and latches are memory elements with clock/control inputs. They depend on the
past as well as present states. Whereas, in case of combinational circuits, they only depend on the
present state.

Page 64 of 104
114.How many stable states combinational circuits have?
a) 3
b) 4
c) 2
d) 5
Answer: c
Explanation: The two stable states of combinational circuits are 1 and 0. Whereas, in flip- flops there is an
additional state known as Forbidden State.

115.The flip-flop is only activated by

a) Positive edge trigger
b) Negative edge trigger
c) Either positive or Negative edge trigger
d) Sinusoidal trigger
Answer: c
Explanation: Flip flops can be activated with either a positive or negative edge trigger.

116.The S-R latch composed of NAND gates is called an active low circuit because

a) It is only activated by a positive level trigger

b) It is only activated by a negative level trigger
c) It is only activated by either a positive or negative level trigger
d) It is only activated by sinusoidal trigger
Answer: b
Explanation: Active low indicates that only an input value of 0 sets or resets the circuit.

117. Both the J-K & the T flip-flop are derived from the basic
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
Answer: b
Explanation: The SR latch is the basic block for the D latch/flip flop from which the JK and T flip flops are
derived. A latch is similar to a flip-flop, only without a clock input.

118.The flip-flops which has not any invalid states are

a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
Answer: d
Explanation: Unlike the SR latch, these circuits have no invalid states. The SR latch or flip-flop has an
invalid or forbidden state where no output could be determined.

Page 65 of 104
119.What does the triangle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Edge triggered
c) Both Level enabled & Edge triggered
d) Level triggered
Answer: b
Explanation: The triangle on the clock input of a J-K flip-flop mean edge triggered. Whereas the absence
of triangle symbol implies that the flip-flop is level-triggered.

120.What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
Answer: c
Explanation: The circle on the clock input of a J-K flip-flop mean negative edge triggered. Whereas the
absence of triangle symbol implies that the flip-flop is level-triggered.

121.What does the direct line on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
Answer: d
Explanation: The direct line on the clock input of a J-K flip-flop mean level triggered.Whereas the presence
of triangle symbol implies that the flip-flop is edge-triggered.

122. What does the half circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
Answer: d
Explanation: The half circle on the clock input of a J-K flip-flop mean level triggered. Whereas the
presence of triangle symbol implies that the flip-flop is edge-triggered.

123. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is

a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave
Answer: d
Explanation: As one flip flop is used so there are two states available. So, 20/2 = 10Hz frequency is
available at the output.

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124.On a positive edge-triggered S-R flip-flop, the outputs reflect the input conditionwhen
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
Answer: c
Explanation: Edge triggered device will follow the input condition when there is a transition. It is said to be
positive edge triggered when transition occurs from LOW to HIGH. While it is said to be a negative edge
triggered when a transition occurs from HIGH to LOW.

125.In D flip-flop, D stands for

a) Distant
b) Data
c) Desired
d) Delay
Answer: b
Explanation: The D of D-flip-flop stands for ―data‖. It stores the value on the data line.

126.The D flip-flop has input.

a) 1
b) 2
c) 3
d) 4
Answer: a
Explanation: The D flip-flop has one input. The D of D-flip-flop stands for ―data‖. It stores the value on the
data line.

127.The D flip-flop has output/outputs.

a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: The D flip-flop has two outputs: Q and Q complement. The D flip-flop has one input. The D
of D-flip-flop stands for ―data‖. It stores the value on the data line.

128.A D flip-flop can be constructed from an flip-flop.

a) S-R
b) J-K
c) T
d) S-K
Answer: a
Explanation : A D flip-flop can be constructed from an S-R flip-flop by inserting an inverterbetween S and R
and assigning the symbol D to the S input.

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129. In D flip-flop, if clock input is LOW, the D input
a) Has no effect
b) Goes high
c) Goes low
d) Has effect
Answer: a
Explanation: In D flip-flop, if clock input is LOW, the D input has no effect, since the set and reset inputs
of the NAND flip-flop are kept HIGH.

130.In D flip-flop, if clock input is HIGH & D=1, then output is

a) 0
b) 1
c) Forbidden
d) Toggle
Answer: a
Explanation: If clock input is HIGH & D=1, then output is 0. It can be observed from thisdiagram:

131.Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?

a) The logic level at the D input is transferred to Q on NGT of CLK
b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH
c) The Q output is ALWAYS identical to the D input when CLK = PGT
d) The Q output is ALWAYS identical to the D input
Answer: a
Explanation n: By the truth table of D flip flop, we can observe that Q always depends on
D. Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q.

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132.Which of the following is correct for a gated D flip-flop?
a) The output toggles if one of the inputs is held HIGH
b) Only one of the inputs can be HIGH at a time
c) The output complement follows the input when enabled
d) Q output follows the input D when the enable is HIGH
Answer: d
Explanation: If clock is high then the D flip-flop operate and we know that input is equals to output in case
of D flip-flop. It stores the value on the data line.

133.With regard to a D latch

a) The Q output follows the D input when EN is LOW
b) The Q output is opposite the D input when EN is LOW
c) The Q output follows the D input when EN is HIGH
d) The Q output is HIGH regardless of EN‘s input state
Answer: c
Explanation n: Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip- flop output
follows the input. It stores the value on the data line.

134.Which of the following is correct for a D latch?

a) The output toggles if one of the inputs is held HIGH
b) Q output follows the input D when the enable is HIGH
c) Only one of the inputs can be HIGH at a time
d) The output complement follows the input when enabled
Answer: b
Explanation: If the clock is HIGH then the D flip-flop operates and we know that input equals to output in
case of D flip flop. It stores the value on the data line.

135.Which of the following describes the operation of a positive edge-triggered D flip-flop?

a) If both inputs are HIGH, the output will toggle
b) The output will follow the input on the leading edge of the clock
c) When both inputs are LOW, an invalid state exists
d) The input is toggled into the flip-flop on the leading edge of the clock and is passed tothe output on the
trailing edge of the clock
Answer: b
Explanation: Edge-triggered flip-flop means the device will change state during the rising or falling edge of
the clock pulse. The main phenomenon of the D flip-flop is that the o/p will follow the i/p when the enable
pin is HIGH.

136. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following inputactions will
cause it to change states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1
Answer: d
Explanation: PGT refers to Positive Going Transition and NGT refers to negative Going Transition.
Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage output will be 1 and
hence the stage will be changed.

Page 69 of 104
137. A positive edge-triggered D flip-flop will store a 1 when
a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH.
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH
Answer: b
Explanation: A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and the clock
transitions from LOW to HIGH. While a negative edge-triggered D flip-flop will store a 0 when the D input is
HIGH and the clock transitions from HIGH to LOW.

138. Why do the D flip-flops receive its designation or nomenclature as ‗Data Flip-flops‘?
a) Due to its capability to receive data from flip-flop
b) Due to its capability to store data in flip-flop
c) Due to its capability to transfer the data into flip-flop
d) Due to erasing the data from the flip-flop
Answer: c
Explanation: Due to its capability to transfer the data into flip-flop. D-flip-flops stores the value on the data
line.

139. The characteristic equation of D-flip-flop implies that

a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state
Answer: d
Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to
satisfy the truth table. The characteristic equation of D flip-flop is given by Q(n+1) = D; which indicates that
the next state is independent of the present state.

140. The asynchronous input can be used to set the flip-flop to the
a) 1 state
b) 0 state
c) either 1 or 0 state
d) forbidden State
Answer: c
Explanation: The asynchronous input can be used to set the flip-flop to the 1 state or clear the flip-flop to
the 0 state at any time, regardless of the condition at the other inputs.

141. Input clock of RS flip-flop is given to

a) Input
b) Pulser
c) Output
d) Master slave flip-flop
Answer: b
Explanation: Pulser behaves like an arithmetic operator, to perform the operation or determination of
corresponding states.

Page 70 of 104
142.D flip-flop is a circuit having
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates

Answer: c
Explanation: D flip-flop is a circuit having 4 NAND gates. Two of them are connectedwith each other.

143. In JK flip flop same input, i.e. at a particular time or during a clock pulse, the outputwill oscillate back
and forth between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The situation
is referred to as?
a) Conversion condition
b) Race around condition
c) Lock out state
d) Forbidden State
Answer: b
Explanation: A race around condition is a flaw in an electronic system or process whereby the output and
result of the process is unexpectedly dependent on the sequence or timing of other events.

144.Master slave flip flop is also referred to as?

a) Level triggered flip flop
b) Pulse triggered flip flop
c) Edge triggered flip flop
d) Edge-Level triggered flip flop
Answer: b
Explanation: The term pulse triggered means the data is entered on the rising edge of the clock pulse, but
the output does not reflect the change until the falling edge of the clock pulse.

145.In a positive edge triggered JK flip flop, a low J and low K produces?
a) High state
b) Low state
c) Toggle state
d) No Change State
Answer: d
Explanation: In JK Flip Flop if J = K = 0 then it holds its current state. There will be no change.

146.If one wants to design a binary counter, the preferred type of flip-flop is

a) D type
b) S-R type
c) Latch
d) J-K type
Answer: d
Explanation: If one wants to design a binary counter, the preferred type of flip-flop is J-K type because it has
capability to recover from toggle condition. SR flip-flop is not suitable as it produces the ―Invalid State‖.
Page 71 of 104
147. S-R type flip-flop can be converted into D type flip-flop if S is connected to R through

a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
Answer: c
Explanation: S-R type flip-flop can be converted into D type flip-flop if S is connected to R through an
Inverter gate.

148.Which of the following flip-flops is free from the race around the problem?
a) T flip-flop
b) SR flip-flop
c) Master-Slave Flip-flop
d) D flip-flop
Answer: a
Explanation: T flip-flop is free from the race around condition because its output depends only on the input;
hence there is no any problem creates as like toggle.

149. Which of the following is the Universal Flip-flop?

a) S-R flip-flop
b) J-K flip-flop
c) Master slave flip-flop
d) D Flip-flop
Answer: b
Explanation: There are lots of flip-flops can be prepared by using J-K flip-flop. So, thename is a universal
flip-flop. Also, the JK flip-flop resolves the Forbidden State.

150.How many types of triggering take place in a flip flops?

a) 3
b) 2
c) 4
d) 5
Answer: a
Explanation: There are three types of triggering in a flip-flop, viz., level triggering, edge triggering and
pulse triggering.

151.Flip-flops are
a) Stable devices
b) Astable devices
c) Bistable devices
d) Monostable devices
Answer: c
Explanation: Flip-flops are synchronous bistable devices known as bistable multivibrators as they have 2
stable states.

Page 72 of 104
152.The term synchronous means
a) The output changes state only when any of the input is triggered
b) The output changes state only when the clock input is triggered
c) The output changes state only when the input is reversed
d) The output changes state only when the input follows it
Answer: b
Explanation: The term synchronous means the output changes state only when the clock input is triggered.
That is, changes in the output occur in synchronization with the clock.

153.The S-R, J-K and D inputs are called

a) Asynchronous inputs
b) Synchronous inputs
c) Bidirectional inputs
d) Unidirectional inputs
Answer: b
Explanation: The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are
transferred to the flip-flop‘s output only on the triggering edge or level triggering of the clock pulse.
Moreover, flip-flops have a clock input whereas latches don‘t. Hence, known as synchronous inputs.

154.The circuit that generates a spike in response to a momentary change of input signal is called

a) R-C differentiator circuit

b) L-R differentiator circuit
c) R-C integrator circuit
d) L-R integrator circuit
Answer: a
Explanation: The circuit that generates a spike in response to a momentary change of input signal is
called R-C differentiator circuit.

155.Based on how binary information is entered or shifted out, shift registers are classified into
categories.
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: The registers in which data can be shifted serially or parallelly are known as shift registers.
Based on how binary information is entered or shifted out, shift registers are classified into 4 categories, viz.,
Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO), Parallel-In/Serial-Out (PISO), Parallel-In/Parallel-Out
(PIPO).

156.The full form of SIPO is

a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out
Answer: a
Explanation: SIPO is always known as Serial-in Parallel-out.
Page 73 of 104
157.A shift register that will accept a parallel input or a bidirectional serial load and internal shift features
is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
Answer: c
Explanation: A shift register can shift it‘s data either left or right. The universal shift register is capable of
shifting data left, right and parallel load capabilities.

158. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
Answer: d
Explanation: Because no other flip-flops are connected with the output Q, therefore one can use the Q out
of each FF to take out parallel data.

159. What is meant by the parallel load of a shift register?

a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
Answer: a
Explanation: At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus input is
definitely 1.

160.The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift
register with an initial state 01110. After three clock pulses, the register contains
a) 01110
b) 00001
c) 00101
d) 00110
Answer: c
Explanation: LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.

Page 74 of 104
161.Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100.
What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111
Answer: c
Explanation: In Serial-In/Serial-Out shift register, data will be shifted one at a time with every clock
pulse. Therefore,
Wait | Store 1100 |
0000
110 | 0000 1st clock
11 | 0000 2nd clock.

162. . A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting
to enter. After four clock pulses, the register contains
a) 0000
b) 1111
c) 0111
d) 1000
Answer: c
Explanation: In Serial-In/Parallel-Out shift register, data will be shifted all at a time with every clock
pulse. Therefore,
Wait | Store 0111 |
0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk X |
1111 4th clk.
163. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
Answer: b
Explanation f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be loaded = 8 * 5 =
40 micro-sec.
164 . An 8 bit serial in/serial out shift register is used with a clock frequency of 2MHz to achieve a
time delay (td) of
a) 16 us
b) 8 us
c) 4 us
d) 2 us
Answer: c
Explanation: One clock period is = (1⁄2) micro-s = 0.5 microseconds. In serial transmission, data enters one bit at a time. So, the total delay = 0.5*8
= 4 micro secondstime is required to transmit information of 8 bits.
Page 75 of 104
 5. Data Conve ters and PLC Marks:-16
Content of Chapter:-
5.1. Data Converters : DAC: Types, weighted resistor circuit and R-2R ladder circuit, DAC IC 0808/0809,specifications
ADC:Block Diagram ,Types and working of dual slope ADC,SAR ADC ,ADC IC
0808/0809,specification
Memory :RAM and ROM basic building blocks, read and write operations, types of semiconductor andmemories
PLD :basic Building blkocks and types of PLDs, PLA, PAL, GAL CPLD: Basic
Building Blocks,Functionality.

1. ADC has a fixed conversion time

A) Counter Comparator ADC C) Double Ramp ADC
B) Wilkinson ADC D) Successive Approximation ADC
Answer : Option D

2. The R-2R ladder DAC has the drawback

A) Higher Values Of Resistance AreRequired C) Non-Linearity Due To Power
Dissipation
B) Lesser Word Length D) None Of The Above
Answer : Option C

3. Resolution of a 6 bit DAC can be stated as

A) Resolution Of 1 Part In 63 C) Resolution Of 1.568% Of Full Scale
B) 6-Bit Resolution D) All Of The Mentioned
Answer : Option A

4. The resolution of a 0–5 V 6-bit digital-to-analog converter (DAC) is

A) 63 % C) 1.56 %
B) 64 % D) 15.6%
Answer : Option C

5. Settling time for DAC 0808 is

A) 20msec C) 100nsec
B) 50nsec D) 150nsec
Answer : Option D

6. Conversion time of ADC 0809 is

a) 50us c) 100us
b) 75us d) 20ms
Answer : Option C

Page 76 of 104
7. Widely used ADC are
a) ADC0809 c) ADC 0805
b) ADC 0806 d) ADC0808
Answer : Option D

8. Widely used DAC are

a) DAC0808 c) DAC0805
b) DAC0804 d) DAC0807
Answer : Option A

9. How many control lines are present in analog to digital converter in addition toreference voltage?
a) Three c) One
b) Two d) None of the mentioned
Answer : Option B

10. Find out the integrating type analog to digital converter?

a) Flash type converter c) Counter type converter
b)Tracking converter d) Dual slope ADC
Answer : Option D

11. Which type of ADC follow the conversion technique of changing the analoginput signal to a linear function of
frequency?
a) Direct type ADC c) Both integrating & direct type ADC
b) Integrating type ADC d) None of the mentioned
Answer : Option B

12. Which A/D converter is considered to be simplest, fastest and most expensive?
a) Servo converter c) Flash type ADC
b) Counter type ADC d) All of the mentioned
Answer : Option C

13. Drawback of counter type A/D converter

a) Counter clears automatically c) High conversion time
b) More complex d) Low speed
Answer : Option D

14. How to overcome the drawback of the charge balancing ADC?

a) By using precision integrator c) By using voltage comparator
b) By using Voltage to frequencyconverter d) By using dual slope converter
Answer : Option D

15. The first step in the design of memory decoder is

a) Selection of a EPROM c) Address assignment
b) Selection of a RAM d) Data insertion
Answer : Option C
Page 77 of 104
16. How many address bits are required to select memory location in the Memorydecoder?
a) 4 KB c) 12 KB
b) 8 KB d) 16 KB
Answer : Option C

17. IC 4116 is organised as

a) 512 * 4 c) 32 * 4
b) 16 * 1 d) 64 * 2
Answer : Option C

18. PLD contains a large number of

a) Flip-flops c) Registers
b) Gates d) All of the Mentioned
Answer : Option D

19. Logic circuits can also be designed using

a) RAM c) PLD
b) ROM d) PLA
Answer : Option C

20. In PLD, there are provisions to perform interconnections of the gates internally,because of
a) High reliability c) The desired logic implementation
b) High conductivity d) The desired output
Answer : Option C

21. How many types of PLD is?

a) 2 c) 4
b) 3 d) 5
Answer : Option D

22. How many types of PLD is?

a) 2 c) 4
b) 3 d) 5
Answer : Option A

23. The full form of PLD is

a) Programmable Load Devices c) Programmable Logic Devices
b) Programmable Logic Data d) Programmable Loaded Devices
Answer : Option C

24. The inputs in the PLD is given through

a) NAND gates c) NOR gates
b) OR gates d) AND gates
Answer : Option D
Page 78 of 104
25. PAL refers to
a) Programmable Array Loaded c) Programmable Array Logic
b) Programmable Logic Array d) Programmable AND Logic
Answer : Option c

26. Outputs of the AND gate in PLD is known as

a) Input lines c) Strobe lines
b) Output lines d) Control lines
Answer : Option b

27. PLA contains

a) AND and OR arrays c) NOT and AND arrays
b) NAND and OR arrays d) NOR and OR arrays
Answer : Option a

28. PLA is used to implement

a) A complex sequential circuit c) A complex combinational circuit
b) A simple sequential circuit d) A simple combinational circuit
Answer : Option c

29. For programmable logic functions, which type of PLD should be used?
a) PLA c) CPLD
b) PAL d) SLD
Answer : Option b

30. The difference between a PAL & a PLA is

a) PALs and PLAs are the same.
b) The PLA has a programmable OR plane and a programmable ANDplane, while the PAL only has a programmable
AND plane
c) The PAL has a programmable OR plane and a programmable AND plane, while the PLA
only has a programmable AND plane
d) The PAL has more possible product terms than the PLA
Answer : Option b

31. If a PAL has been programmed once

a) Its logic capacity is lost c) Its outputs are only active LOW
b) Its outputs are only active. d) It cant be reprogrammed.
Answer : Option D

32. The FPGA refers to

a) First programmable Gate Array c) First Program Gate Array
b) Field Programmable GateArray d) Field Program Gate Array
Answer : Option C

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33. The full form of VLSI is
a) Very Long Single Integration c) Very Large Scale Integration
b) Very Least Scale Integration d) Very Long Scale Integration
Answer : Option C

34. In FPGA, vertical and horizontal directions are separated by

a) A line c) A strobe
b) A channel d) A flip-flop
Answer : Option B

35. Applications of PLAs are

a) Registered PALs c) PAL programming
b) Configurable PALs d) All of the Mentioned
Answer : Option D

36. Which type of ADC is chosen for noisy environment?

a) Successive approximation ADC c) Charge balancing ADC
b) Dual slope d) All of the mentioned
Answer : Option C

37. Which among the following has long conversion time?

a) Servo converter c) Flash converter
b) Dual ramp converter d) None of the mentioned
Answer : Option B

38. At what condition error occurs in the servo tracking A/D Converter?
a) Slow change input c) No change in input
b) Rapid change in input d) All of the mentioned
Answer : Option B

39. The number of comparator required for flash type A/D converter
a) Triples for each added bit
b) Reduce by half for each added bit
c) Double for each added bit
d) Doubles exponentially for each added bit
Answer : Option C

40. The flash type A/D converters are called as

a) Parallel non-inverting A/D converter
b) Parallel counter A/D converter
c) Parallel inverting A/D converter
d) Parallel comparator A/D converter
Answer : Option D

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 41. What is the advantage of using flash type A/D converter?
a) High speed conversion c) Nominal speed conversion
b) Low speed conversion d) None of the mentioned
Answer : Option A

42. In a servo tracking A/D converter, the input voltage is greater than the DACoutput signal at
this condition
a) The counter count up c) The counter back and forth
b) The counter count down d) None of the mentioned
Answer : Option A

43. Typical conversion speed of ADC is

a) Less than 1µs
b) Less than 100 µs
c) Less than 500 µs
d) Greater than 1000 µs
Answer: b
Explanation: Typical conversion speed of ADC is between 1µs and 100 µs.

44. Which of the following type output is provided by ADC?

a) Serial type
b) Parallel type
c) Both serial and parallel type
d) None of the mentioned

Answer: c
Explanation: ADC provides both serial and parallel type output according to application.

45. Which of the following method is employed for ADC?

a) Ladder network
b) Successive approximation type
c) PWM type
d) None of the mentioned
Answer: b
Explanation: In successive approximation method input value is constantly compared with a reference value.

46. Successive approximation is slow for large bit application.

a) True
b) False

Answer: b
Explanation: Successive approximation method is much faster in large bit application.

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47. Which of the following represents range of frequency measured by ADC?
a) Bandwidth
b) Threshold frequency
c) Peak frequency
d) None of the mentioned

Answer: a
Explanation: Bandwidth of ADC is the maximum range of frequency measured by ADC.

48. Dynamic range of ADC is depended on

a) Resolution
b) Linearity
c) Accuracy
d) All of the mentioned

Answer: d
Explanation: Dynamic range of ADC is depended on both resolution, linearity and accuracy.

49. Small timing errors in ADC additional to noise is known as

a) Jitter
b) Aliasing
c) Super noise
d) None of the mentioned

Answer: a
Explanation: Jitter is a type of noise that is produced additional to noise.

50. ENOB in ADC stand for

a) Effective number of bytes
b) Effective number of bits
c) Effective nibble baud
d) None of the mentioned

Answer: b
Explanation: Effective number of bits (ENOB) represents the number of bits measured by ADC.

51. ENOB is a negation of resolution.

a) True
b) False

Answer: b
Explanation: ENOB or effective number of bits is the number of bits measured by ADC and it is equal to resolution.

52. Rotary encoder is an ADC.

a) True
b) False
Answer: a
Explanation: Rotary encoder can be treated as an encoder which converts analog quantity to digital quantity.

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53.What is the main role of an ADC?
a) Amplify
b) Convert analog to digital
c) Reduce noise
d) Increase range
Answer: b
Explanation: ADC corresponds to Analog to Digital Converter which is used to convert an analog signal into a digital. Digital signal can
be processed and manipulated.

54. The process of converting a continuous analog signal to a discrete digital signal is called?
a) Discretisation
b) Sampling
c) Preemphasis
d) Reduction
Answer: b
Explanation: An analog signal is continuous and hence contains an infinite number of points. The process in which this continuous
signal is discretized is called as sampling. The sampling period determines the accuracy of conversion.

55. What is the minimum frequency of sampling so that the analog waveform is adequately expressed?
a) Minimum sampling rate
b) Minimum sampling frequency
c) Nyquist frequency
d) Conversion rate
Answer: c
Explanation: The minimum frequency at which an analog wave should be sampled is given by Nyquist frequency. If the sampling
frequency is below this limit then the analog waveform is not fully represented and leads to data loss.

56. What is the minimum rate at which an analog signal of frequency 6000Hz is sampled?
a) 6000Hz
b) 60Hz
c) 120Hz
d) 12000Hz
Answer: d

Explanation: Minimum sampling frequency= Nyquist frequency = 2x(frequency of analog waveform)

= 2x 6000Hz = 12000Hz.

57. What is the number of voltage increments that can be represented in an 8-bit system?
a) 255
b) 256
c) 215
d) 126
Answer: a
Explanation: The number of voltage increments that can be in an N bit system is given by 2N-1 = 28-1 =255.
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58. What is the error that occurs when the number of bits is not sufficient enough to represent the analogvoltages?
a) Data error
b) Sampling error
c) Acquisition error
d) Quantization error
Answer: d
Explanation: When the number of bits is not sufficient enough to represent the analog voltage levels, quantization error occurs.
The greater the number of bits, the greater the number of increments over the analog range and the smaller the quantizing
error.

59. What is the maximum amount of quantization error that can occur in a 10bit system in the input analog voltage is from 0V
to 6V?
a) 10mV
b) 6mV
c) 0.5mV
d) 1mV
Answer: b
Explanation: The minimum voltage step input is 6/(2N-1) = 6/1023 =5.865mV ≈6mV. This is the maximum
error that can occur during the conversion process.

60. What is the rms noise voltage if the weight of the LSB is 0.005865?
a) 5mV
b) 1mV
c) 1.7mV
d) 0.7mV
Answer:c
Explanation:

61. What is the signal frequency if the rectangular digital wave has a time period of 71.4μs?
a) 14,006Hz
b) 15,036Hz
c) 14Hz
d) 21,436Hz
Answer: a
Explanation: Signal frequency = 1/ time period of the wave = 1/71.4μs = 14,006Hz.
62. What is the 5th harmonic of the rectangular digital wave if the frequency is 14kHz?
a) 21kHz
b) 45kHz
c) 25kHz
d) 70kHz
Answer: d
Explanation: Fifth harmonic = 5 x signal frequency = 5 x 14kHz = 70kHz.
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63. What is the output of a digital to analog converter?
a) Smooth continuous wave
b) Stairstep wave
c) Triangular waves
d) Circular waves
Answer: b
Explanation: The Digital to analog converter takes the binary number as an input and produces the analog voltage proportional to the
binary number. These analog voltages represent specific analog voltage levels and have stairstep characters.

64. Which of the following has the capability to store the information permanently?
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
Answer: b
Explanation: ROM (Read Only Memory) has the capability to store the information permanently. RAM provides random access to
memory. Storage cells are responsible for the transfer of data from and into the memory.

65. ROM has the capability to perform

a) Write operation only
b) Read operation only
c) Both write and read operation
d) Erase operation
Answer: b
Explanation: ROM means ―Read Only Memory‖. Hence, it has the capability to perform read operation only. No write or erase
operation could be performed in the ROM.

66. Since, ROM has the capability to read the information only then also it has been designed, why?
a) For controlling purpose
b) For loading purpose
c) For booting purpose
d) For erasing purpose
Answer: c
Explanation: ROM means ―Read Only Memory‖. Hence, it has capability to perform read operation only. No write or erase operation
could be performed in the ROM. It has designed to provide the computer with resident programmes and for booting purpose.

67. The ROM is a

a) Sequential circuit
b) Combinational circuit
c) Magnetic circuit
d) Static circuit
Answer: b
Explanation: ROM is a combination of different ICs. So, it is a combinational circuit. It depends on present input and not past
states.

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68. ROM is made up of
a) NAND and OR gates
b) NOR and decoder
c) Decoder and OR gates
d) NAND and decoder

Answer: c
Explanation: ROM (Read Only Memory) has the capability to store the information permanently. ROM is made up of decoder and OR
gates within a single IC package.

69. Why are ROMs called non-volatile memory?

a) They lose memory when power is removed
b) They do not lose memory when power is removed
c) They lose memory when power is supplied
d) They do not lose memory when power is supplied

Answer: b
Explanation: Volatile memory stores data as long as it is powered. ROMs are called non-volatile memory because of they do
not lose memory when power is removed.

70. In ROM, each bit is a combination of the address variables is called

a) Memory unit
b) Storage class
c) Data word
d) Address
Answer: d
Explanation: In ROM, each bit combination that comes out of the output lines is called data word. Usually, a word consists of 16-bits
or 2-bytes.

71. Which is not a removable drive?

a) Zip
b) Hard disk
c) Super Disk
d) Jaz

Answer: c
Explanation: Hard disk is present inside a computer. So, it is not a removable drive.

72 In ROM, each bit combination that comes out of the output lines is called
a) Memory unit
b) Storage class
c) Data word
d) Address

Answer: c
Explanation: In ROM, each bit combination that comes out of the output lines is called data word. Usually, a word consists of 16-bits
or 2-bytes.

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73. VLSI chip utilizes
a) NMOS
b) CMOS
c) BJT
d) All of the Mentioned

Answer: d
Explanation: Very Large Scale Integration (VLSI) (ranging from 10,000 to 100,000 gates per IC) is a memory chip which is made up of
NMOS, CMOS, BJT, and BiCMOS.

74. What is the access time?

a) The time taken to move a stored word from one bit to other bits after applying the address bits
b) The time taken to write a word after applying the address bits
c) The time taken to read a stored word after applying the address bits
d) The time taken to erase a stored word after applying the address bits
Answer: c
Explanation: The access time is the time taken to read a stored word after applying the address bits in a MOS EPROM. It is the time
required to fetch data from the memory.

75. What are the typical values of tOE?

a) 10 to 20 ns for bipolar
b) 25 to 100 ns for NMOS
c) 12 to 50 ns for CMOS
d) All of the Mentioned
Answer: d

Explanation: The access time is the time taken to read a stored word after applying the address bits in a MOS EPROM. It is the time
required to fetch data from the memory. The typical values of tOE (i.e. access time) are 10 to 20 ns for bipolar, 25 to 100 ns for
NMOS and 12 to 50 ns for CMOS.

76. Which of the following is not a type of memory?

a) RAM
b) FPROM
c) EEPROM
d) ROM
Answer: c
Explanation: EEPROM (Electrical Erasable Programmable ROM) is not a type of memory because it is used for erasing purpose
only. Through EEPROM, data can be erased electrically, thereby consuming less time.

77. The chip by which both the operation of read and write is performed
a) RAM
b) ROM
c) PROM
d) EPROM
Answer: a
Explanation: A Random Access Memory (RAM) is a volatile chip memory in which both the read and write operations can be
performed. Since it is volatile, therefore it stores data as long as power is on.
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78. RAM is also known as
a) RWM
b) MBR
c) MAR
d) ROM
Answer: a
79. Explanation: A Random Access Memory (RAM) is a volatile chip memory in which both the read and write operations can be
performed. Since it is volatile, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write
Memory).

80. If a RAM chip has n address input lines then it can access memory locations upto
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
Answer: c
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write
Memory). If a RAM chip has n address input lines then it can access memory locations upto 2n.

81. The n-bit address is placed in the

a) MBR
b) MAR
c) RAM
d) ROM
Answer: b
Explanation: The n-bit address is placed in the Memory Address Register (MAR) to select one of 2n memory locations. It stores the
address of the instruction which is to be executed next.

82. Which of the following control signals are selected for read and write operations in a RAM?
a) Data buffer
b) Chip select
c) Read and write
d) Memory
Answer: c
Explanation: Read and write are control signals that are used to enable memory for read and write operations respectively.

83. Computers invariably use RAM for

a) High complexity
b) High resolution
c) High speed main memory
d) High flexibility
Answer: c
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write
Memory). Computers invariably use RAM for their high high-speed main memory and then use backup or slower-speed memories to
hold auxiliary data.
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 84. How many types of RAMs are?
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two types of RAM and these are static and dynamic. Static RAM(SRAM) is faster than dynamic RAM(DRAM) as
the access time for DRAM is more compared to that of SRAM.

85. Static RAM employs

a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
Answer: d
Explanation: Static RAM employs bipolar or MOS flip-flops because both the semiconductor has storing capacity. Thus, it‘s
access time is less and it is faster in operation.

86. Dynamic RAM employs

a) Capacitor or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
Answer: a
Explanation: Dynamic RAM employs a capacitor or MOSFET. Thus, it‘s access time is more and it is slower in operation.

87. Which one of the following is volatile in nature?

a) ROM
b) EROM
c) PROM
d) RAM
Answer: d
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write
Memory). RAMs are volatile because the stored data will be lost once the d.c. power applied to the flip-flops is removed.

88. The magnetic core memories have been replaced by semiconductor RAMs, why?
a) Semiconductor RAMs are highly flexible
b) Semiconductor RAMs have highest storing capacity
c) Semiconductor RAMs are smaller in size
d) All of the Mentioned
[

Answer: d

Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write
Memory). The magnetic core memories have been replaced by semiconductor RAMs because of smaller in size, high storing capacity
as well as flexibility.

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89. The data written in flip-flop remains stored as long as
a) D.C. power is supplied
b) D.C. power is removed
c) A.C. power is supplied
d) A.C. power is removed
Answer: a
Explanation: Since flip-flops are made up of semiconductor materials. So, it can‘t accept A.C. source and the data written in flip-flop
remains stored as long as the dc power is maintained.

90. Memory is a/an

a) Device to collect data from other computer
b) Block of data to keep data separately
c) Indispensable part of computer
d) Device to connect through all over the world
Answer: c
Explanation: Memory is an indispensable unit of a computer and microprocessor based systems which stores permanent or
temporary data.

91The instruction used in a program for executing them is stored in the

a) CPU
b) Control Unit
c) Memory
d) Microprocessor
Answer: c
Explanation: All of the program and the instructions are stored in the memory. The processor fetches it as and when required.

92.A flip flop stores

a) 10 bit of information
b) 1 bit of information
c) 2 bit of information
d) 3-bit information
Answer: b
Explanation: A flip-flop has capability to store 1 bit of information. It can be used further after erasing previous information.

93.A register is able to hold

a) Data
b) Word
c) Nibble
d) Both data and word
Answer: b
Explanation: Register is also a part of memory inside a computer. It stands there to hold a word. A word is a group of 16-bits or 2-
bytes.

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94.A register file holds
a) A large number of word of information
b) A small number of word of information
c) A large number of programs
d) A modest number of words of information
Answer: d
Explanation: A register file is different from a simple register because of capability to hold a modest number of words of information. A
word is a group of 16-bits or 2-bytes.

95.The very first computer memory consisted of

a) A small display
b) A large memory storage equipment
c) An automatic keyboard input
d) An automatic mouse input
Answer: b
Explanation: The very first computer memory consisted of a minute magnetic toroid, which required large, bulky circuit boards
stored in large cabinates.

96.A minute magnetic toroid is also called as

a) Large memory
b) Small memory
c) Core memory
d) Both small and large memory
Answer: c
Explanation: A minute magnetic toroid is also called as core memory which is made up of a semiconductor. A semiconductor is a
device whose electrical conductivity lies between that of conductor and insulator.

97.Which one of the following has capability to store data in extremely high densities?
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
Answer: c
Explanation: Semiconductor has capability to store data in extremely high densities.

98.A large memory is compressed into a small one by using

a) LSI semiconductor
b) VLSI semiconductor
c) CDR semiconductor
d) SSI semiconductor

Answer: b
Explanation: VLSI (Very Large Scale Integration) semiconductor is used in modern computers to short the size of memory.

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 99. VLSI chip utilizes
a) NMOS
b) CMOS
c) BJT
d) All of the Mentioned
Answer: d
Explanation: VLSI (Very Large Scale Integration) is a memory chip which is made up of NMOS, CMOS, BJT, and BiCMOS. It can
include 10,000 to 100,000 gates per IC.

100. CD-ROM refers to

a) Floppy disk
b) Compact Disk-Read Only Memory
c) Compressed Disk-Read Only Memory
d) Compressed Disk- Random Access Memory
Answer: b
Explanation: CD-ROM refers to Compact Disk-Read Only Memory.

101. Data stored in an electronic memory cell can be accessed at random and on demand using
a) Memory addressing
b) Direct addressing
c) Indirect addressing
d) Control Unit
Answer: b
Explanation: Direct addressing eliminates the need to process a large stream of irrelevant data in order to the desired data word.

102. The full form of PLD is

a) Programmable Large Device
b) Programmable Long Device
c) Programmable Logic Device
d) Programmable Lengthy Device
[

Answer: c
Explanation: The full form of PLD is Programmable Logic Device.

103. The evolution of PLD began with

a) EROM
b) RAM
c) PROM
d) EEPROM
Answer: a
Explanation: The evolution of PLD (Programmable Logic Device) began with Programmable Read Only Memory (i.e. PROM).
Here, the ROM can be externally programmed as per the user.

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 104. A ROM is defined as
a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory
Answer: c
Explanation: A ROM is defined as Read Only Memory which can read the instruction stored in a computer.

105. If the transistor gate is closed, then the ROM stores a value of 1.
a) True
b) False
Answer: b
Explanation: If the gate of the transistor is closed then, the value of zero is stored in the ROM.

106. PROM stands for

a) Programmable Read Only Memory
b) Pre-fed Read Only Memory
c) Pre-required Read Only Memory
d) Programmed Read Only Memory
Answer: a
Explanation: It allows the user to program the ROM.

107. The PROM is more effective than ROM chips in regard to

a) Cost
b) Memory management
c) Speed of operation
d) Both Cost and Speed of operation
[

Answer: d
Explanation: The PROM is cheaper than ROM as they can be programmed manually.

108. The difference between the EPROM and ROM circuitry is

a) The usage of MOSFET‘s over transistors
b) The usage of JFET‘s over transistors
c) The usage of an extra transistor
d) None of the mentioned
Answer: c
Explanation: The EPROM uses an extra transistor where the ground connection is there in the ROM chip.

109. The ROM chips are mainly used to store

a) System files
b) Root directories
c) Boot files
d) Driver files
Answer: c
Explanation: The ROM chips are used to store boot files required for the system startup.

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110. The contents of the EPROM are erased by
a) Overcharging the chip
b) Exposing the chip to UV rays
c) Exposing the chip to IR rays
d) Discharging the Chip
Answer: b
Explanation: To erase the contents of the EPROM the chip is exposed to the UV rays, which dissipate thecharge on the transistor.

111. The disadvantage of the EPROM chip is

a) The high cost factor
b) The low efficiency
c) The low speed of operation
d) The need to remove the chip physically to reprogram it
Answer : d

112. EEPROM stands for Electrically Erasable Programmable Read Only Memory.
a) True
b) False
Answer: a
Explanation: The disadvantages of the EPROM led to the development of the EEPROM.

113. The disadvantage of the EEPROM is/are

a) The requirement of different voltages to read, write and store information
b) The Latency read operation
c) The inefficient memory mapping schemes used
d) All of the mentioned
Answer : a
.
114. The memory devices which are similar to EEPROM but differ in the cost effectiveness is
a) Memory sticks
b) Blue-ray devices
c) Flash memory
d) CMOS
Answer: c
Explanation: The flash memory functions similar to the EEPROM but is much cheaper.

115. The only difference between the EEPROM and flash memory is that the latter doesn‘t allow bulk data tobe written.
a) True
b) False

Answer: a
Explanation: This is not permitted as the previous contents of the cells will be overwritten.

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116. The flash memories find application in
a) Super computers
b) Mainframe systems
c) Distributed systems
d) Portable devices
Answer: d
Explanation: The flash memories low power requirement enables them to be used in a wide range of hand held devices.

117. The memory module obtained by placing a number of flash chips for higher memory storage called as

a) FIMM
b) SIMM
c) Flash card
d) RIMM
Answer :c

118. The flash memory modules designed to replace the functioning of a hard disk is
a) RIMM
b) Flash drives
c) FIMM
d) DIMM
Answer: b
Explanation: The flash drives have been developed to provide faster operation but with lesser space

119. The reason for the fast operating speeds of the flash drives is
a) The absence of any movable parts
b) The integrated electronic hardware
c) The improved bandwidth connection
d) All of the mentioned
Answer: a
Explanation: Since the flash drives have no movable parts their access and seek times are reasonably reduced

120. Any electronic holding place where data can be stored and retrieved later whenever required is

a) memory
b) drive
c) disk
d) circuit
Answer: a
Explanation: Memory is the place where data can be stored and later retrieved. Memory can be of classified into register, cache,
main memory, etc.

121. Cache memory is the onboard storage.

a) True
b) False
Answer: a

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Explanation: Cache Memory is the memory closest to the CPU. Registers, Cache and the main memory are the means of onboard
storage in the computer system.

122. Which of the following is the fastest means of memory access for CPU?
a) Registers
b) Cache
c) Main memory
d) Virtual Memory
Answer: a
Explanation: Registers are the fastest means of access for CPU. Registers are the small memory locations which are present
closest to the CPU.

123. The memory implemented using the semiconductor chips is

a) Cache
b) Main
c) Secondary
d) Registers
Answer: b
Explanation: The main memory is implemented using semiconductor chips. Main memory is located on the motherboard. It mainly
consists of RAM and small amount of ROM.

124. Size of the memory mainly depends on the size of the address bus.
a) Main
b) Virtual
c) Secondary
d) Cache
Answer: a
Explanation: The size of the main memory depends on the size of the address bus of the CPU. The main memory mainly consists of
RAM and ROM, where RAM contains the current data and programs and ROMcontains permanent programs like BIOS.

125. Which of the following is independent of the address bus?

a) Secondary memory
b) Main memory
c) Onboard memory
d) Cache memory
Answer: a
Explanation: The secondary memory is independent of the address bus. It increases the storage space. It is implemented in the form
of magnetic storage devices.

126. storage is a system where a robotic arm will connect or disconnect off-line mass storage media
according to the computer operating system demands.
a) Secondary
b) Virtual
c) Tertiary
d) Magnetic
Answer: c
Explanation: The tertiary storage is the correct option. It is used in the realms of enterprise storage and scientific computing on large

Page 96 of 104
computer systems and business computer networks and is something a typical personal computer never sees firsthand.

127. What is the location of the internal registers of CPU?

a) Internal
b) On-chip
c) External
d) Motherboard

Answer: b
Explanation: The internal registers are present on-chip. They are therefore present inside the CPU. L1 cache is also present on-
chip inside the CPU.

128. MAR stands for

a) Memory address register
b) Main address register
c) Main accessible register
d) Memory accessible register

Answer: a
Explanation: The MAR stands for memory address register. It holds the address of the active memory location.

129. If M denotes the number of memory locations and N denotes the word size, then an expression that denotes the
storage capacity is
a) M*N
b) M+N
c) 2M+N
d) 2M-N
Answer: a
Explanation: Storage capacity is the product of a number of memory locations that is the number of words and the word size or the
number of bits stored per location. Storage capacity should be as large as possible.

130. DRAM is fabricated by using IC

a) 2114
b) 7489
c) 4116
d) 2776

Answer: c
Explanation: DRAM is Dynamic RAM which takes more access time compared to SRAM and is thus, slower in operation comparatively.
Although, in general it offers high speed and is used in most computers nowadays. DRAM is fabricated by using IC 4116.

131. IC 4116 is of storage memory.

a) 16 KB
b) 32 KB
c) 64 MB
d) 2 KB
Answer: a
Explanation: IC 4116 is a DRAM of 16 KB storage memory. It requires three supply voltages (+5V, -5V, and
+12V) to operate the IC unit.
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132. How many supply voltage IC 4116 requires to operate the IC unit?
a) 3
b) 2
c) 1
d) 4
Answer: a
Explanation: IC 4116 is a DRAM of 16 KB storage memory. It requires three supply voltages (+5V, -5V, and
+12V) to operate the IC unit.

133. The full form of PSRAM is

a) Plugged Static RAM
b) Plugged Stored RAM
c) Pseudo Stored RAM
d) Pseudo Static RAM
Answer: d
Explanation: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM which is implemented as a SRAM.

134. Pseudo static RAM is a

a) Static RAM
b) Dynamic RAM
c) Cache
d) ROM

Answer: b
Explanation: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM having built-in fresh logic, which is implemented as
an SRAM.

135. When PSRAM is performing internal refresh

a) The read operation is performed
b) The write operation is performed
c) It can not be accessed for read or write
d) The voltage goes HIGH
Answer: c
Explanation: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM having built-in fresh logic, which is implemented as a
SRAM. So, it can not be accessed for read or write during the refresh operation.

136. RAMs are utilized in the computer as

a) Scratch-pad
b) Buffer
c) Main memory
d) All of the Mentioned

Answer: d

Explanation: RAMs are utilized in the computer as a scratch-pad, buffer and main memories. These are the applications of RAMs.
Mostly, these RAMs are DRAMs as they provide high speed.

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137. The advantages of RAMs are
a) Non destructive read out
b) Fast operating speed
c) Low power dissipation
d) All of the Mentioned

Answer: d
Explanation: The advantages of RAM are Non-destructive read out, Fast operating speed and Low power dissipation.

138. Which one is more economical?

a) ROM
b) RAM
c) EROM
d) PROM

Answer: b
Explanation: RAM is more economical than ROM because MOS memories are more economical than the magnetic core for
small and medium sized systems.

139. Which one is self-compatible?

a) ROM
b) RAM
c) EROM
d) PROM

Answer: b
Explanation: As semiconductor memories enjoy common interface and technology between sensing and decoding circuitry and the
storage element itself, so RAMs are self-compatible. Also, they provide high speed and fast operation.

140. The memory which is used for storing programs and data currently being processed by the CPUis called
a) PROM
b) Main Memory
c) Non-volatile memory
d) Mass memory
Answer: a
Explanation: PROM has the capability to store the data due to the presence of MOSFET which is processed by the CPU. It is one-
time programmable by the user.

141. CD-ROM is a
a) Memory register
b) Magnetic memory
c) Semiconductor memory
d) Non-volatile memory
Answer: d
Explanation: CD-ROM is a non-volatile memory. Once a program is uploaded in it then it can‘t be erasable. Thus, it stores the data
permanently.
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142.A place which is used as storage location in a computer
a) A bit
b) A record
c) An address
d) A byte
Answer: c
Explanation: A storage location of a computer is an address/memory location, used to store instructions and data

143. Which of the following is not a primary storage device?

a) Optical disk
b) Magnetic tape
c) Magnetic disk
d) RAM

Answer: d
Explanation: RAM (i.e. Random Access Memory) is not a primary storage device.

Prepared By Verified By Re-Verified By Approved By

Badadhe P S Navale.S.N. Navale.S.N Tupe S G
Module Coordinator Academic Coordinator HoD E&Tc

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