CHAPTER 5

COMBINATIONAL LOGIC CIRCUIT AND SEQUENTIAL CIRCUIT ANALYSIS

Combinational Logic Circuit

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DECODERS

Discrete quantities of information are represented in digital systems by binary codes. A binary
code of n bits is capable of representing up to 2n distinct elements of coded information. A decoder
is a combinational circuit that converts binary information from n input lines to a maximum of 2
n unique output lines. If the n -bit coded information has unused combinations, the decoder may
have fewer than2 n outputs. The most common decoder circuit is an n -to m decoder or binary
decoder, where m ≤ 2 n. Their purpose is to generate the 2 n (or fewer) minterms of n input
variables. Each combination of inputs will assert a unique output

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 Fig 7.15

As an example, consider the three-to-eight-line decoder circuit of Fig 7.15. The three inputs are
decoded into eight outputs, each representing one of the minterms of the three input variables. The
three inverters provide the complement of the inputs, and each one of the eight AND gates
generates one of the minterms. A particular application of this decoder is binary-to-octal
conversion. The input variables represent a binary number, and the outputs represent the eight
digits of a number in the octal number system. However, a three-to-eight-line decoder can be used
for decoding any three-bit code to provide eight outputs, one for each element of the code.

Figure7.15 Three-to-eight-line decoder

The operation of the decoder may be clarified by the truth table listed in Table above . For each
possible input combination, there are seven outputs that are equal to 0 and only one that is equal
to 1. The output whose value is equal to 1 represents the minterm equivalent of the binary number
currently available in the input lines.

Q) Implement a full adder circuit with a decoder and two or gates.

Encoder
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has
2n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary
code corresponding to the input value. An example of an encoder is the octal-to-binary encoder
whose truth table is given in table below. It has eight inputs (one for each of the octal digits) and
three outputs that generate the corresponding binary number. It is assumed that only one input has
a value of 1 at any given time.

The encoder can be implemented with OR gates whose inputs are determined directly from the
truth table. Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7. Output y is 1 for octal
digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. These conditions can be expressed by
the following Boolean output functions:

z = D1 + D3 + D5 + D7

y = D2 + D3 + D6 + D7

x = D4 + D5 + D6 + D7

The encoder can be implemented with three OR gates

 Figure 7.16 Logic circuitry of 8:3 encoder.

Multiplexer (MUX)
Multiplexing means transmitting a large number of information units over a small number of
channels or lines

It is also called data selector. A multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and
n selection lines whose bit combinations determine which input is selected.

Figure 7.17 Logic Symbol for a 4-input multiplexer (MUX)

a 2-bit code on the data-select (5) inputs will allow the data on the selected data input to pass
through t0 the data output. If a binary 0 (S1 = 0 and So = 0) is applied to the data-select lines. the
data on input Do appear on the data-output line, If a binary 1 (S1 = 0 and So = 1) is applied to the
data-select lines, the data on input D1 appear on the data output. If a binary 2 (S1 = 1 and So = 0)
is applied, the data on D2 appear Oil the output. If a binary 3 (S1 = 1 and So = 1) is applied, the
data on D3) are switched to the output line. A summary of this operation is given in the table bellow

Now let's look at the logic circuitry required to perform this multiplexing operation. The data
Output is equal to the state of the selected data input. You can therefore, derive a logic expression
for the output ill terms of the data input and the select inputs.

The data output is equal to Do only if S1 = 0 and S0 = 0: Y = D0S1S0

The data output is equal to D1 only if S1 = 0 and So = 1: Y = D1S1So.

The data output is equal to D2 only if S1 = 1 and So = 0: Y= D2S1S0

The data output is equal to Dl only if S1 = 1 and So = 1: Y = D3S1S0

When these terms are ORed the total expression for the data output is

Y= D0S1S0 + D1S1S0 + D2S1S0+ D3S1S0

The implementation of this equation requires four 3-input AND gates, a 4-input OR gate, and two
inverters 10 generate the complements of S1 and So as shown in Figure 7.18. Because data can be
selected from anyone of the input lines, this circuit is also referred to as a data selector.

Figure 7.18
DEMULTIPLEXERS
A demultiplexer (DEMUX) basically reverses the multiplexing function. It takes digital
information from one line and distributes it to a given number of output lines. Therefore, it is
known as a Data Distributor. A decoder with enable input can function as a demultiplexer

Figure 7.19
 Sequential circuit
Introduction

In the previous session, we said that the output of a combinational circuit depends solely upon the
input. The implication is that combinational circuits have no memory. In order to build
sophisticated digital logic circuits, including computers, we need more a powerful model. We need
circuits whose output depends upon both the input of the circuit and its previous state. In other
words, we need circuits that have memory.

For a device to serve as a memory, it must have three characteristics:

• The device must have two stable states • There must be a way to set the state at least
once.
• There must be a way to read the state of the
device

It is possible to produce circuits with memory using the digital logic gates we've already seen. To
do that, we need to introduce the concept of feedback. So far, the logical flow in the circuits we've
studied has been from input to output. Such a circuit is called acyclic. Now we will introduce a
circuit in which the output is fed back to the input, giving the circuit memory. (There are other
memory technologies that store electric charges or magnetic fields; these do not depend on
feedback.)

Memory elements are digital circuits that can store and retrieve data in the form of 1's and 0's.The
output of the systems with memory depends not only on present inputs but also on what has
happened in the past. Sequential circuit = Combinational logic + Memory Elements

There are two types of sequential circuits:

Latches and flip-flops
A latch is a type temporary data storage device (memory element) that have two possible states(
i.e. it is bistable device) and the output may change at any time and a flip-flop is synchronous
bistable device(memory element) that changes state at specified point.

In the same way that gates are the building blocks of combinatorial circuits, latches and flip-flops
are the building blocks of sequential circuits.

While gates had to be built directly from transistors, latches can be built from gates, and flip-flops
can be built from latches. This fact will make it somewhat easier to understand latches and flip-
flops.

Both latches and flip-flops are circuit elements whose output depends not only on the current
inputs, but also on previous inputs and outputs. The difference between a latch and a flip-flop is
that a latch does not have a clock signal, whereas a flip-flop always does. Latches are level
sensitive devices and flip-flops are edge sensitive devices In other words, Latches are
asynchronous and flip-flops are synchronous devices.

LATCHES

In order for a logical circuit to "remember" and retain its logical state even after the controlling
input signal(s) have been removed, it is necessary for the circuit to include some form of feedback.
We might start with a pair of inverters, each having its input connected to the other's output. The
two outputs will always have opposite logic levels.

The problem with this is that we don't have any additional inputs that we can use to change the
logic states if we want. We can solve this problem by replacing the inverters with NAND or NOR
gates, and using the extra input lines to control the circuit.
Flip-flops

Latches are asynchronous, which means that the output changes very soon after the
input changes. Most computers today, on the other hand, are synchronous, which
means that the outputs of all the sequential circuits change simultaneously to the
rhythm of a global clock signal.

A flip-flop is a synchronous version of the latch. Flip-flops: synchronous bistable

devices. Output changes state at a specified point on a triggering input called the
clock.

Change state either at the positive edge (rising edge) or at the negative edge (falling
edge) of the clock signal.

Figure

A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops
are shown in Figure 2 and Figure 3. Each flip-flop has two outputs, Q and Q′, and two inputs, set
and reset. This type of flip-flop is referred to as an SR flip-flop or SR latch. The flip-flop in Figure
2 has two useful states. When Q=1 and Q ′=0, it is in the set state (or 1-state). When Q=0 and Q
′=1, it is in the clear state (or 0 -state). The outputs Q and Q ′ are complements of each other and
are referred to as the normal and complement outputs, respectively. The binary state of the flip-
flop is taken to be the value of the normal output.

When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 2, both Q and Q ′
outputs go to 0. This condition violates the fact that both outputs are complements of each other.
In normal operation this condition must be avoided by making sure that 1's are not applied to both
inputs simultaneously.

Clocked SR Flip-Flop

The clocked SR flip-flop shown in Figure 4 consists of a basic NOR flip-flop and
two AND gates. The outputs of the two AND gates remain at 0 as long as the clock
pulse (or CP) is 0, regardless of the S and R input values. When the clock pulse goes
to 1, information from the S and R inputs passes through to the basic flip-flop. With
both S=1 and R=1, the occurrence of a clock pulse causes both outputs to
momentarily go to 0. When the pulse is removed, the state of the flip-flop is
indeterminate, ie., either state may result, depending on whether the set or reset input
of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.
D Flip-Flop

The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes
directly into the S input and the complement of the D input goes to the R input. The D input is
sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state
(unless it was already set). If it is 0, the flip-flop switches to the clear state.

Figure

JK Flip-Flop

A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is
defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note
that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are
applied to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1,
it switches to Q=0 and vice versa.

A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the
flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q′ is ANDed
with J and CP inputs so that the flip-flop is set with a clock pulse only if Q′ was previously 1.

Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1
(while J=K=1) after the outputs have been complemented once will cause repeated and continuous
transitions of the outputs. To avoid this, the clock pulses must have a time duration less than the
propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with
a master-slave or edge-triggered construction. The same reasoning also applies to the T flip-flop
presented next.

Figure

T Flip-Flop

The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 7, the T flip-flop
is obtained from the JK type if both inputs are tied together. The output of the T flip-flop "toggles"
with each clock pulse.