555 Timer as a Monostable Multivibrator

1. Determine the time period of a monostable 555 multivibrator.

a) T = 0.33RC
b) T = 1.1RC
c) T = 3RC
d) T = RC

Answer: b
Explanation: The time period of a monostable 555 timer is T = RC×ln(1/3) = 1.1.RC.
2. Find monostable vibrator circuit using 555 timer.
a)

b)

c)

d) None of the mentioned

Answer: a
Explanation: When 555 timer is configured in monostable operation, the trigger input is
applied through pin2 whereas, upper comparator threshold (pin6) & discharge (pin7) are
shorted and connected at the output.
3. How to overcome mistriggering on the positive pulse edges in the monostable circuit?
a) Connect a RC network at the input
b) Connect an integrator at the input
c) Connect a differentiator at the input
d) Connect a diode at the input

Answer: c
Explanation: To prevent the mistrigger on positive pulse edges, a resister & capacitor
combined of 10kΩ and 0.001µF at the input to form a differentiator

The circuit shows the differentiator to be connected between trigger input and the +VCC.
4. A monostable multivibrator has R = 120kΩ and the time delay T = 1000ms, calculate
the value of C?
a) 0.9µF
b) 1.32µF
c) 7.5µF
d) 2.49µF

Answer: c
Explanation: Time delay for a monostable multivibrator, T = 1.1RC
=> C = T/(1.1R) = 1000ms/(1.1×120kΩ) = 7.57µF.
5. Which among the following can be used to detect the missing heart beat?
a) Monostable multivibrator
b) Astable multivibrator
c) Schmitt trigger
d) None of the mentioned

Answer: a
Explanation: A monostable multivibrator can be used as a missing pulse detector by
connecting a transistor between trigger inputs. If a pulse misses, the discharge trigger
input goes high & transistor become cut-off and the output goes low. So, this type of
circuit can be used to detect missing heart beat.
6. A 555 timer in monostable application mode can be used for
a) Pulse position modulation
b) Frequency shift keying
c) Speed control and measurement
d) Digital phase detector
Answer: c
Explanation: In monostable operation mode, if input trigger pulses are generated from a
rotating wheel, the circuit will determine the wheel speed whenever it drops below a
predetermined value. Therefore, it can be used for speed control and measurement.
7. How can a monostable multivibrator be modified into a linear ramp generator?
a) Connect a constant current source to trigger input
b) Connect a constant current source to trigger output
c) Replace resistor by constant current source
d) Replace capacitor by constant current source

Answer: c
Explanation: The resistor R of the monostable circuit is replaced by a constant current
source. So, that the capacitor is charged linearly and generates ramp signal.
8. Determine time period of linear ramp generator using the specifications
RE = 2.7kΩ, R1 =47kΩ , R2 100kΩ , C= 0.1µF, VCC =5v.

a) 8ms
b) 4ms
c) 2ms
d) 1ms

Answer: d
Explanation: The time period of the linear ramp generator, T= [(2/3)×(V CC×RE)×(R1+
R2)×C]/{(R1×VCC)-[VBE×(R1+R2)]}
= {(2/3)×5v×[2.7kΩ×(4.7kΩ+ 100kΩ)]×(0.1µF)}/{[(47kΩ)×5v]-[(0.7)×(47kΩ+100kΩ)]}
=>T= 132.3/132.100 =1.0015×10 -3 = 1ms.
9. What will be the output, if a modulating input signal and continuous triggering signal
are applied to pin5 and pin22 respectively in the following circuit?

a) Frequency modulated wave form

b) Pulse width modulated wave form
c) Both pulse and frequency modulated wave form
d) None of the mentioned

Answer: b
Explanation: On application of continuous trigger at pin22 and a modulated input signal
at pin5, a series of output pulses are obtained. The duration of which depends on the
modulating signal. Also in the pulse duration, only the duty cycle varies, keeping the
frequency same as that of the continuous input pulse train trigger.
555 Timer as an Astable Multivibrator
1. Free running frequency of Astable multivibrator?
a) f=1.45/(RA+2RB)C
b) f=1.45(RA+2RB)C
c) f=1.45C/(RA+2RB)
d) f=1.45 RA/( RA+RB)

Answer: a
Explanation: The frequency of the Astable multivibrator is T=0.69(R A+2RB)C.
Therefore, f = 1/T =1.45/(RA+2RB)C.
2. Find the charging and discharging time of 0.5µF capacitor.

a) Charging time=2ms; Discharging time=5ms

b) Charging time=5ms; Discharging time=2ms
c) Charging time=3ms; Discharging time=5ms
d) Charging time=5ms; Discharging time=3ms

Answer: b
Explanation: The time required to charge the capacitor is t High=0.69(RA+RB)C
=0.69(10kΩ+5kΩ)x0.5µF =5ms.
The time required to discharge the capacitor is t Low=0.69xRC =0.69x5kΩx0.5µF=2ms.
3. Astable multivibrator operating at 150Hz has a discharge time of 2.5m. Find the duty
cycle of the circuit.
a) 50%
b) 75%
c) 95.99%
d) 37.5%

Answer: d
Explanation: Given f=150Hz.Therefore,T=1/f =1/150 =6.67ms.
∴ Duty cycle, D%=(tLow/T) x 100% = (2.5ms/6.67ms)x100% = 37.5%.
4. Determine the frequency and duty cycle of a rectangular wave generator.

a) Frequency=63.7kHz; Duty cycle=50%

b) Frequency=53.7kHz; Duty cycle=55%
c) Frequency=43.7kHz; Duty cycle=50%
d) Frequency=60kHz; Duty cycle=55%

Answer: b
Explanation: Frequency=1.45/(RA+RB)C .
Where RA=100Ω+50Ω=150Ω,
RB=100Ω+20Ω=120Ω.
=>∴f=1.45/((150+120)x0.1µF) = 53703Hz = 53.7kHz.
Duty cycle, D% = [RB/(RA+RB)] x 100% = 120Ω/(150Ω +120Ω) x 100% = 0.55×100% =
55%.
5. How to achieve 50% duty cycle in adjustable rectangular wave generator? (Assume
R1 –> Resistor connected between supply and discharge and R2 –> Resistor connected
between discharge and trigger input.)
a) R1 < R2
b) R1 > R2
c) R1 = R2
d) R1 ≥ R2

Answer: c
Explanation: The equation of duty cycle, D = R 2/(R1 + R2). If R1 is made equal to R2 then
50% duty cycle is achieved.
6. How to obtain symmetrical waveform in Astable multivibrator?
a) Use clocked RS flip-flop
b) Use clocked JK flip-flop
c) Use clocked D-flip-flop
d) Use clocked T-flip-flop

Answer: b
Explanation: Symmetrical square wave can be obtained by adding a clocked JK flip-flop
to the output of Astable multivibrator. The clocked flip-flop acts as a binary divider to the
times output and produces 50% duty cycle without any restriction on the choice of
resistors.
7. Determine the output frequency of the circuit.

a) 1450Hz
b) 1333Hz
c) 1871Hz
d) 1700Hz

Answer: c
Explanation: The output frequency of the frequency shift keying generator is
f=1.45/[(RA||RC)+2(RB)]xC = 1.45/[(2.3kΩ||2.3kΩ) + (2×3.3kΩ)] x 0.1µF =
1.45/{[(2.3×2.3)/(2.3+2.3)] + 6.6kΩ}x0.1µF = 1.45/(7.75×10-4) = 1870.9 ≅ 1871Hz.
8. How does a monostable multivibrator used as frequency divider?
a) Using square wave generator
b) Using triangular wave generator
c) Using sawtooth wave generator
d) Using sine wave generator

Answer: a
Explanation: Monostable multivibrator can be used as a frequency divider when a
continuously triggered monostable circuit is triggered using a square wave generator.
Provided the timing interval is adjusted to be longer than the period of triggering square
wave input signal.
1. Free running multivibrator is also called as
a) Stable multivibrator
b) Voltage control oscillator
c) Square wave oscillator
d) Pulse stretcher

Answer: b
Explanation: Free running multivibrator operates at a frequency which is determined by
an external tuning capacitor and a resistor. On applying a dc control voltage the
frequency can be shifted on either sides. This frequency deviation is directly proportional
to the dc control voltage and hence it is called as ‘voltage controlled oscillator’.
2. The output voltage of phase detector is
a) Phase voltage
b) Free running voltage
c) Error voltage
d) None of the mentioned
Answer: c
Explanation: The phase detector compares the input frequency with the feedback
frequency and produces output dc voltage called as error voltage.
3. At which state the phase-locked loop tracks any change in input frequency?
a) Free running state
b) Capture state
c) Phase locked state
d) All of the mentioned

Answer: c
Explanation: In the phase-locked, the output frequency is exactly same as the input
signal frequency. So the circuit tracks any change in the input frequency through its
repetitive action.
4. Match the list I with list II which represents the three stages of phase locked
loop.(PLL)

List I List II

1.Before input frequency applied i. PLL-Phase locked state

2.When the input frequency applied ii.PLL=Free running state

3.After input frequency applied iii. PLL-Capture mode

a) 1-ii, 2-iii, 3-i
b) 1-iii, 2-ii, 3-i
c) 1-i, 2-ii, 3-iii
d) 1-ii, 2-i, 3-iii

Answer: a
Explanation: Before the input is applied, the PLL is in a free running state. Once the
input frequency is applied, the VCO frequency start to change & PLL is said to be in
capture mode. When the VCO frequency continues to change until it is equal to the input
frequency, the PLL is said to be in phase locked state.
5. What is the function of low pass filter in phase-locked loop?
a) Improves low frequency noise
b) Removes high frequency noise
c) Tracks the voltage changes
d) Changes the input frequency

Answer: b
Explanation: The output voltage of a phase detector is a dc voltage and is often referred
to as error voltage. This output is applied to the low pass filter which removes the high
frequency noise and produces a dc level.
6. What is the need to generate corrective control voltage?
a) To maintain the lock
b) To track the frequency change
c) To shift the VCO frequency
d) All of the mentioned

Answer: d
Explanation: The output frequency(f o) of VCO is identical to input frequency(f s) except for
a finite phase difference(φ), which generates a corrective control voltage to shift VCO
frequency from fo to fs, thereby maintains the lock once locked and PLL tracks the
frequency changes of the input signal.
7. At what range the PLL can maintain the lock in the circuit?
a) Lock in range
b) Input range
c) Feedback loop range
d) None of the mentioned

Answer: a
Explanation: The change in frequency of the incoming signal can be tracked when the
PLL is locked. So, the range of frequencies over which PLL maintains the lock with the
incoming signal is called as the lock in range.
8. The pull-in time depends on
a) Initial phase and frequency difference between two sign
b) Overall loop gain
c) Loop filter characteristics
d) All of the mentioned

Answer: d
Explanation: The pull-in time depends on the above mentioned characteristics to
establish lock in the PLL circuit.
1. Analog phase detector is often referred as
a) Full wave detector
b) Half wave detector
c) Rectifier wave detector
d) None of the mentioned

Answer: b
Explanation: Analog phase detector is called as half wave detector because, the phase
information for only one-half of the input waveform is detected and averaged.
2. What happens when VCO output is 90 o out of phase with respect to input signal?
a) Perfect lock
b) Attenuation
c) Shift in phase of comparator
d) Error signal is removed

Answer: a
Explanation: The error voltage is zero when the phase shift between the two inputs is
90o. So, for the perfect lock, the VCO output should be 90 o out of phase with respect to
the input signal.
3. Find the error voltage of phase comparator whose input signal is V s= Vssin(2πfst) and
the output signal Vo= Vosin(2πfot+φ).
a) Ve=[k×(Vs/2)]×[cos(-φ)-cos(2πfot+φ)].
b) Ve=[k×Vs×(Vo/2)]×[cos(-φ)-cos(2πfot+φ)].
c) Ve=[k×Vs×(Vo/2)]×[cos(-φ)+cos(2πfot+φ)].
d) Ve=[k×Vs×Vo]×[cos(-φ)-cos(2πfot+φ)].

Answer: b
Explanation: A phase comparator is basically a multiplier which multiplies the input
signal by the VCO signal. Thus, the phase comparator output = V s×Vo = Vs×Vosin(2πfst)×
sin(2πfot+φ) =k×Vs×Vo ×sin(2πfst)×sin(2πfot+φ)
Where k – phase comparator gain.= k×V s×Vo/2[cos(-φ)-cos(2πfot+φ)] When at lock, fs =fo
=> Ve = Ve={k×Vs× Vo/2}x[cos(-φ)-cos(2πfot+φ)].
4. How to overcome the problem associated with switch type phase detective?
a) Increase loop gain depending on input signal
b) Phase shift is made linear
c) Limit the amplifier of input signal
d) All of the mentioned

Answer: c
Explanation: The problems can be eliminated by limiting the amplifier of the input signal
that is converting the input to a constant amplified square wave. This can be achieved
by using a balanced modulator used as full wave switching phase detector.
5. If the average error voltage & the phase shift are given as 6.2v & π/4.Determine the
phase angle to voltage transfer coefficient of full wave switching phase detector.
a) -0.19
b) -0.09
c) -0.03
d) -0.13

Answer: d
Explanation: The phase angle to voltage transfer coefficient
=>kφ = (φ-π/2)/ Ve (avg) =[π/4-π/2]/6.2 =[π-2π/4]/6.2 = -(π/4)/6.2 = -π/24.8
=>kφ = -0.13.
6. When does a digital phase detector can be used, where f o->output frequency, fs->input
frequency.
a) Both fo & fs signals should be square wave
b) fo should be square wave & fs can be any non-sinusoidal wave
c) fs should be square wave & fo can be any non-sinusoidal wave
d) Both fo & fs can be any non-sinusoidal wave

Answer: a
Explanation: The XOR gate produces high output when only one of the input signal f o or
fs is high. So, to detect high or low value of waveform, square waves are used.
7. The maximum dc output voltage in digital phase detector occurs
a) When the phase difference is π/2
b) When the phase difference is π
c) When the phase difference is 3π/4
d) When the phase difference is 2π

Answer: b
Explanation: The maximum dc output voltage occurs when the phase difference is π,
because the output of the XOR gate phase detector remains high throughout.
8. Given the DC output voltage versus phase difference φ curve. Find the conversion
gain values.

a) 15.7V/rad
b) 1.26V/rad
c) 1.59V/rad
d) 0.8V/rad

Answer: c
Explanation: The slope gives the conversion gain. Therefore, conversion gain=V cc/φ
=5V/π =1.59V/rad.
9. Which among the following has better capture tracking & locking characteristics?
a) XOR phase detector
b) Edge triggered phase detector
c) Analog phase detector
d) All of the mentioned

Answer: b
Explanation: Edge triggered phase detector has better capture tracking and locking
characteristics as the dc output voltage is linear upto 360 o compared to other detectors.
1. How to obtain a desired amount of multiplication in frequency multiplier?
a) By decreasing the multiplication factor
b) By increasing the input frequency
c) By selecting proper divide by N-network
d) None of the mentioned

Answer: c
Explanation: The desired amount of multiplication can be obtained by properly selecting
a divide by N-network. For example, to obtain the output frequency f out=5×fin, a divide by
N = 5 network is needed.
2. Calculate the output frequency in a frequency multiplier if, fin = 200Hz is applied to a 7
divide by N-network.
a) 1.2kHz
b) 1.6kHz
c) 1.2kHz
d) 1.9kHz

Answer: c
Explanation: Since the VCO is actually running at a multiple of input frequency.
fout=divide by N-network x fin=7x200Hz=1400Hz
=>fout=1.4kHz.
3. For what kind of input signal, the frequency divider can be avoided frequency
multiplier?
a) Triangular waveform
b) Square waveform
c) Saw tooth waveform
d) Sine waveform

Answer: a
Explanation: VCO can be directly locked to the n th harmonic of the input signal without
connecting any frequency divider in between the input signal rich in harmonics like
square wave.
4. What must the typical value of n for a frequency multiplication / division? (n->order of
harmonics)
a) n ≤ 12
b) n > 11
c) n < 10
d) n = 7

Answer: d
Explanation: As the amplitude of the higher order harmonics becomes less, effective
locking may not take place for high values of n. So, the typical value of n is less than 10
for frequency multiplication / division.
5. Determine the offset frequency of frequency translation, when the output and input
frequency are given as 75kHz and 1000Hz.
a) 35 kHz
b) 20 kHz
c) 29 kHz
d) 14 kHz

Answer: b
Explanation: The output of the frequency translation f o= fs+f1
=> f1 = fo– fs= 75kHz-55kHz =20kHz.
6. The frequency corresponding to logic 1 state in FSK is called
a) Space frequency
b) Mark frequency
c) Both mark and space frequency
d) None of the mentioned

Answer: b
Explanation: Frequency shift is usually accomplished by dividing a VCO with binary data
signal. Therefore, the logic 1 state of the binary data signal corresponds to mark
frequencies.
7. Find the frequency shift in FSK generator?
a) 230 Hz
b) 250 Hz
c) 180 Hz
d) 200 Hz
Answer: d
Explanation: Frequency shift is the difference between FSK signals of 1070 Hz and 1270
Hz frequency, which is 200 Hz.
8. Which filter is chosen to remove the carrier component in the frequency shift keying?
a) Three stage filter
b) Two stage filter
c) Single stage filter
d) All of the mentioned

Answer: a
Explanation: The high cut-off frequency of ladder filter is chosen to be approximately
halfway between the maximum keying rate of 150Hz & twice the input frequency (≅
2200Hz) which can be obtained using three stage filters.