Digital Design & Computer Organisation (BCS302)

EXPERIMENT -1
Given a 4-variable logic expression, simplify it using appropriate technique and
simulate the same using basic gates.

F(W,X,Y,Z)=Sm(0,1,2,4,5,6,8,9,12,13,14)
Solution F = Y1 + W1Z1 +X1Z1

Theory:
Procedure:
1. Open ORCAD CAPTURE.
2. Select new project from file menu.
3. Select analog and mixed A/D.
4. Choose blank project.
5. Make circuit as shown in figure.
6. Place the voltage marker at appropriate node.
7. Create new simulation profile and click on run.
Analysis Type: Transient
Run to time – 10ms
Output waveform

Conclusion :

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EXPERIMENT -2
Design a full adder and subtractor and simulate the same using basic gates.

a) Full adder
Sum = A xor B xor Cin
Cout = AB+BC+CA

Circuit Truth table

Theory :
Procedure:
1. Open ORCAD CAPTURE.
2. Select new project from file menu.
3. Select analog and mixed A/D.
4. Choose blank project.
5. Make circuit as shown in figure.
6. Place the voltage marker at appropriate node.
7. Create new simulation profile and click on run.
Analysis Type: Transient
Run to time – 30ms
Output waveform

b) Full Subtractor

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Sum = A xor B xor Cin

Cout = A1 B+BC+A1C

Circuit Truth table

Procedure:
1. Open ORCAD CAPTURE.
2. Select new project from file menu.
3. Select analog and mixed A/D.
4. Choose blank project.
5. Make circuit as shown in figure.
6. Place the voltage marker at appropriate node.
7. Create new simulation profile and click on run.
Analysis Type: Transient
Run to time – 30ms

Output waveform

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Aim : Design Verilog HDL to implement AND gate, OR gate, not gate, EX-OR gate

AND OR

NOT X-OR

Verilog Code:

module basicgates(a,b, f1,f2,f3,f4);

input a,b;
output f1,f2,f3,f4;
assign f1=a&b;
assign f2=a|b;
assign f3=~a;
assign f4=a ^b;
endmodule

Verilog test fixture:

module basicgates(a,b, f1,f2,f3,f4);
input a,b;
output f1,f2,f3,f4;
assign f1=a&b;
assign f2=a|b;
assign f3=~a;
assign f4=a ^b;

initial begin
A = 0; B = 0;
#100 A = 0; B = 1;
#100 A = 1; B = 0;
#100 A = 1; B = 1;
end

endmodule

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EXPERIMENT-4

Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioral
model.

Circuit:
TRUTH TABLE
Input Output
a a b c f
0 0 0 0
b 0 0 1 1
0 1 0 0
f 0 1 1 0
1 0 0 0
1 0 1 1
c 1 1 0 1
1 1 1 1

Verilog Code:
i)DATA FLOW MODEL
module dataflow(a,b,c, f);
input a,b,c;
output f;
assign f=((a&b)|((~b)&c));
endmodule

ii) STRUCTURAL MODEL

module structural(a,b,c, f);
input a,b,c;
output f;
wire x,y,z;
and(x,a,b);
not(y,b);
and(z,y,c);
or(f,x,z);
endmodule

iii) Behavioral model

module behavioral(a,b,c, f);
input a,b,c;
output f;
reg f;
always @(a,b,c)
if(b==1)
f=a;
else
f=c;

SIMULATION OUTPUT

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EXPERIMENT 4:
Design Verilog HDL to implement Binary adder –Subtractor – Half and Full adder,
Half and Full Subtractor.

Half-Adder
Circuit Truth table

Verilog code

module half_adder (a,b,s,c);

input a,b;
output s,c;

assign s = a ^ b;
assign c = a & b;

endmodule

Half-Subtractor

Circuit Truth table

Verilog code
module half_subtractor (a,b,diff,borrow);
input a,b;
output diff,borrow;

assign diff = a ^ b;
assign borrow = ~a & b;
endmodule

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FULL ADDER
Circuit Truth table

Verilog code:

module fulladder(a,b,cin, s,cout);

input a,b,cin;
output s,cout;
assign s = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule

FULL SUBTRACTOR

Circuit Truth table

Verilog code:

module fullsubtractor(a,b,cin, diff,borrow);

input a,b,bin;
output diff,borrow;
assign diff = a ^ b ^ bin;
assign borrow = (~a & bin) | (~a & b) | (b & bin);
endmodule

SIMULATION OUTPUT

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EXPERIMENT 5:
Design Verilog HDL to implement Decimal adder.

Circuit:

module decimal_adder(a,b,carry_in,sum,carry);
input [3:0] a,b;
input carry_in;
output [3:0] sum;
output carry;
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;

always @(a,b,carry_in)
begin
sum_temp = a+b+carry_in;
if(sum_temp > 9)
begin
sum_temp = sum_temp+6;
carry = 1;
sum = sum_temp[3:0];
end
else begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule

TRUTH TABLE

SIMULATION OUTPUT

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EXPERIMENT 6:
Design Verilog HDL to implement Different types of multiplexer like 2:1, 4:1 and 8:1.

2 to 1 Multiplexerd

Block diagram
En

Truth Table
A
Input Output
2:1-
MUX Y SEL En Y

B X 1 0

0 0 A

1 0 B

SEL

Verilog code:

module MUX2_1(A, B, SEL, Y);

input A, B, SEL ;
output Y;
reg Y;
always @ (SEL, A, B)
if (SEL == 1)

assign Y = B;

else if( SEL == 0)

assign Y = A;
else
assign Y = 1'bz;
endmodule

SIMULATION OUTPUT

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4 to 1 Multiplexer

Verilog code
Verilog code
module mux81(din, sel,
module mux41(din, sel, dout); dout);
input [7:0] din;
input [3:0] din; input [2:0] sel;
input [1:0] sel; output dout;
output dout; reg dout;
always @(din or sel)
reg dout; begin
always @(din or sel) case (sel)
begin 3’b000:dout=din[0];
3’b001:dout=din[1];
case (sel) 3’b010:dout=din[2];
3’b00:dout=din[0]; 3’b011:dout=din[3];
3’b01:dout=din[1]; 3’b100:dout=din[4];
3’b101:dout=din[5];
3’b10:dout=din[2];
3’b110:dout=din[6];
3’b11:dout=din[3];
3’b111:dout=din[7]
default: dout=1’bx;
endcase ;
end default: dout=1’
endmodule bx;
endcase
end
endmodule

SIMULATION OUTPUT

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8 to 1 Multiplexer

Block diagram: Truth Table:

I(0)
Selector O/P
I(1)
I(2) S2 S1 S0 Y
I(3) 0 0 0 I(0)
y
I(4) 8:1 0 0 1 I(1)
MUX
I(5) 0 1 0 I(2)
I(6) 0 1 1 I(3)
I(7) 1 0 0 I(4)
1 0 1 I(5)
s(2) s(0) 1 1 0 I(6)
s(1) 1 1 1 I(7)

Multiplexer (MUX) is a digital switch which connects data from one of n

sources to the output. A number of select inputs determine which data source is
connected to the output.

Verilog code

module mux81(din, sel, dout);

input [7:0] din;
input [2:0] sel;
output dout;
reg dout;
always @(din or sel)
begin
case (sel)
3’b000:dout=din[0];
3’b001:dout=din[1];
3’b010:dout=din[2];
3’b011:dout=din[3];
3’b100:dout=din[4];
3’b101:dout=din[5];
3’b110:dout=din[6];
3’b111:dout=din[7];
default: dout=1’bx;
endcase
end
endmodule

SIMULATION OUTPUT:

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EXPERIMENT 7:
Design Verilog HDL to implement Different types of De-Multiplexer.

THEORY: A demultiplexer is a circuit that receives the information on a single line

and transmits this information on one of 2n possible output lines. The selection of
specific output lines is controlled by the values of n selection lines. For 1: 8
demultiplexers, the single input variable has a path to all the eight outputs, but the
input information is directed to only one of the 8 output lines.

1:2 Demultiplexer

TRUTH TABLE

Verilog code:

module demux1to2(i,sel,y0,y1);
input i,sel;
output y0,y1;
assign {y0,y1} = sel?{1'b0,i}:{i,1'b0};
endmodule

SIMULATION OUTPUT

1:4 Demultiplexer

TRUTH TABLE

Verilog code:

module demux1to4(d,sel,y0,y1,y2,y3);
input d;
input[1:0] sel;
output y0,y1,y2,y3;
assign y0=(sel==2'b00)?d:1'b0;
assign y1=(sel==2'b01)?d:1'b0;
assign y2=(sel==2'b10)?d:1'b0;
assign y3=(sel==2'b11)?d:1'b0;
endmodule

SIMULATION OUTPUT

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1:8 Demultiplexer
Truth Table

Selector Output
e
d S2 S1 S0 y7 y6 y5 y4 y3 y2 y1 y0
n
0 d/0 X X X Z Z Z Z Z Z Z Z
1 d/0 0 0 0 Z Z Z Z Z Z Z d/0
1 d/0 0 0 1 Z Z Z Z Z Z d/0 Z
1 d/0 0 1 0 Z Z Z Z Z d/0 Z Z
1 d/0 0 1 1 Z Z Z Z d/0 Z Z Z
1 d/0 1 0 0 Z Z Z d/0 Z Z Z Z
1 d/0 1 0 1 Z Z d/0 Z Z Z Z Z
1 d/0 1 1 0 Z d/0 Z Z Z Z Z Z
1 d/0 1 1 1 d/0 Z Z Z Z Z Z Z

Verilg code:

module demux1to8(d,sel,y0,y1,y2,y3,y4,y5,y6,y7);
input d;
input[2:0] sel;
output y0,y1,y2,y3,y4,y5,y6,y7;

assign y0=(sel==3’b000)?d:1’b0;
assign y1=(sel==3’b001)?d:1’b0;
assign y2=(sel==3’b010)?d:1’b0;
assign y3=(sel==3’b011)?d:1’b0;
assign y4=(sel==3’b100)?d:1’b0;
assign y5=(sel==3’b101)?d:1’b0;
assign y6=(sel==3’b110)?d:1’b0;
assign y7=(sel==3’b111)?d:1’b0;
endmodule

SIMULATION OUTPUT

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EXPERIMENT 8:
Design Verilog program for implementing various types of Flip-Flops such as SR, JK,
and D.

A. SR Flip-flop
Circuit Truth table
rst pr Clk s r q qb

1 X X X X 0 1

0 1 X X X 1 0

0 0 1 0 0 Qb Qbprevious

0 0 1 0 1 0 1

0 0 1 1 0 1 0

0 0 1 1 1 1 1

Verilog Code B. D Flip-flop:

module srff(reset, clk, s, r, q, qb);
input reset;
input clk;
input s;
input r;
output q;
output qb;
reg temp;
always@(negedge reset, posedge clk) Verilog Code
module dff(data,clk,q);
begin
input data,clk;
if(!reset) output q;
temp<=1’b0; reg q;
else always@(posedge clk)
begin begin
q<=data;
case({s,r}) end
2’b01: temp<=1’b0; endmodule
2’b10: temp<=1’b1;
2’b00: temp<=temp;
2’b11: temp<=1’bx;
default: temp<=1’bz;
endcase
end
end
assign q=temp;
assign qb=~q;
endmodule

SIMULATION OUTPUT

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B. D Flip-flop:
Circuit Truth table

clk d q qb

X 1 1 0

1 1 1 0

1 0 0 1

Verilog Code

module dff(data,clk,q);
input data,clk;
output q;
reg q;
always@(posedge clk)
begin
q<=data;
end
endmodule

SIMULATION OUTPUT

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C JK Flip-flop:

Circuit Truth table

Rst Clk J K Q Qb

1 1 0 0 Previous state

1 1 0 1 0 1

1 1 1 0 1 0

1 1 1 1 Qb Q

1 No +ve edge - - Previous state

0 - - - 0 1

Verilog code

module jkff (clk, reset, j, k, q, qb);

input clk,reset;
input j;
input k;
output q;
output qb;
reg temp;
always@(negedge reset, posedge clk)
begin
if(!reset)
temp<=1’b0;
else
begin
case({j,k})
2'b01:temp=1’b0;
2'b10:temp=1’b1;
2'b11:temp=~temp;
2'b00:temp=temp;
default:temp<=1’bz;
endcase
end
end
assign q=temp;
assign qb=~temp;
endmodule

SIMULATION OUTPUT

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