MIRACLE EDUCATIONAL SOCIETY GROUP

OF INSTITUTIONS
(Approved by AICTE & Affiliated to JNTU-KAKINADA)
Vizianagaram-535216

RTL Simulation and Synthesis with PLD’s Lab

LAB MANUAL

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Regulation : R19

Class : I M.Tech _ I Sem

Branch : VLSI & Embedded Systems

Department : ECE

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 RTL Simulation and Synthesis with PLDs Lab

List of Experiments:

1) Verilog implementation of

i) 8:1 Mux/Demux,

ii) Full Adder, 8-bit Magnitude comparator,

iii) 3-bit Synchronous Counters

iv) Parity generator.

2) Sequence generator/detectors, Synchronous FSM – Mealy and Moore machines.

3) Vending machines - Traffic Light controller, ATM, elevator control.

4) PCI Bus & arbiter and downloading on FPGA.

5) UART/ USART implementation in Verilog.

6) Realization of single port SRAM in Verilog.

7) Verilog implementation of Arithmetic circuits like serial adder/ subtractor, parallel adder/subtractor,
serial/parallel multiplier.

8) Discrete Fourier transform/Fast Fourier Transform algorithm in Verilog.

Course Outcomes: At the end of the laboratory work, students will be able to:

 Identify, formulate, solve and implement problems in signal processing, communication

Systems etc using RTL design tools.

 Use EDA tools like Cadence, Mentor Graphics and Xilinx.

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 1.Logic Gates

Aim:To verify and perform the operation of logic gates using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module allgates_b(a, b, not1, or2, and3, nor4, nand5, xor6, xnor7);

input a;

input b;

output reg not1;

output reg or2;

output reg and3;

output reg nor4;

output reg nand5;

output reg xor6;

output reg xnor7;

always@(a or b)

begin

not1=~a;

or2=a|b;

and3=a&b;

nor4=~(a|b);

nand5=~(a&b);

xor6=(a^b);

xnor7=~(a^b);

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 end

endmodule

module logicgates_d(a, b, c);

input a;

input b;

output[6:0]c;

and(c[0],a,b);

or(c[1],a,b);

not(c[2],a);

nand(c[3],a,b);

nor(c[4],a,b);

xor(c[5],a,b);

xnor(c[6],a,b);

endmodule

Testbench:

module logicgates_v;

reg a,b;

wire[6:0]c;

basicgates uut(.a(a),.b(b),.c(c));

initial begin

#10 a=1'b0;b=1'b0;

#10 a=1'b0;b=1'b1;

#10 a=1'b1;b=1'b0;

#10 a=1'b1;b=1'b1;

#10 $stop;

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 end

endmodule

Output Waveform:

Result:The realization of logic gates is performed using Verilog HDL.

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 2. Adders

Half adder

Aim:To verify and perform the operation of half adder using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module halfadder_b(a, b, sum, carry);

input a;

input b;

output sum;

output carry;

reg sum,carry;

always@(a or b)

begin

sum=a^b;

carry=a&b;

end

endmodule

module halfadder_d(a, b, sum, carry);

input a;

input b;

output sum;

output carry;

assign sum=a^b;

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 assign carry=a&b;

endmodule

Testbench:

module halfadderd_v;

reg a,b;

wire sum,carry;

halfadder uut(.a(a),.b(b),.sum(sum),.carry(carry));

initial begin

#10 a=1'b0;b=1'b0;

#10 a=1'b0;b=1'b1;

#10 a=1'b1;b=1'b0;

#10 a=1'b1;b=1'b1;

#10 $stop;

end

endmodule

Output Waveform:

Result:The truthtable of half adder is verified using Verilog HDL.

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 Full adder:

Aim:To verify and perform the operation of full adder using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module fulladder_b(a, b, cin, sum, carry);

input a;

input b;

input cin;

output reg sum;

output reg carry;

always@(a or b or cin)

begin

case({a,b,cin})

3'b000:begin sum=1'b0;

carry=1'b0;

end

3'b001:begin sum=1'b1;

carry=1'b0;

end

3'b010:begin sum=1'b1;

carry=1'b0;

end

3'b011:begin sum=1'b0;

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 carry=1'b1;

end

3'b100:begin sum=1'b1;

carry=1'b0;

end

3'b101:begin sum=1'b0;

carry=1'b1;

end

3'b110:begin sum=1'b0;

carry=1'b1;

end

3'b111:begin sum=1'b1;

carry=1'b1;

end

default:begin sum=1'b0;

carry=1'b0;

end

endcase

end

endmodule

module fulladder_b(a,b,cin,sum,cout);

input a,b,cin;

output reg sum,cout;

always@(a or b or cin)

begin

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 sum = a^b^cin;

cout = (a&b)|(b&cin)|(a&cin);

end

endmodule

module fulladder_d(a,b,cin,sum,cout);

input a,b,cin;

output sum,cout;

assign sum=a^b^cin;

assign cout=(a&b)|(b&cin)|(a&cin);

endmodule

Testbench:

module fulladder_v;

reg a,b,cin;

wire sum,cout;

fulladder uut(.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));

initial begin

#10 a=1'b0;b=1'b0;cin=1'b0;

#10 a=1'b0;b=1'b0;cin=1'b1;

#10 a=1'b0;b=1'b1;cin=1'b0;

#10 a=1'b0;b=1'b1;cin=1'b1;

#10 a=1'b1;b=1'b0;cin=1'b0;

#10 a=1'b1;b=1'b0;cin=1'b1;

#10 a=1'b1;b=1'b1;cin=1'b0;

#10 a=1'b1;b=1'b1;cin=1'b1;

#10$stop;

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 end

endmodule

Output Waveform:

Result:The truthtable of full adder is verified using Verilog HDL.

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 3. Subtractors

Half Subtractor:

Aim:To verify and perform the operation of Half Subtractor using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module hs_b(a, b, D, Borrow);

input a;

input b;

output reg D;

output reg Borrow;

always@(a or b)

begin

D=a^b;

Borrow=(~a)&b;

End

module hs_d(a,b,D,Bor);

input a,b;

output D,Bor;

assign D=a^b;

assign Bor=!a&b;

endmodule

Testbench:

module halfsubtractor_v;

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 reg a,b;

wire D,Bor;

hs uut(.a(a),.b(b),.D(D),.Bor(Bor));

initial begin

#10 a=1'b0;b=1'b0;

#10 a=1'b0;b=1'b1;

#10 a=1'b1;b=1'b0;

#10 a=1'b1;b=1'b1;

#10 $stop;

end

endmodule

endmodule

Output Waveform:

Result:The truthtable of Half subtractor is verified using Verilog HDL.

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 Full Subtractor:

Aim:To verify and perform the operation of Full Subtractor using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module fs_b(a , b, cin, D, borow);

input a ;

input b;

input cin;

output reg D;

output reg borow;

always@(a or b or cin)

begin

D=a^b^cin;

borow=(cin&~(a^b))|((~a)&b);

end

endmodule

module fs1_d(a , b, cin, D, borow);

input a ;

input b;

input cin;

output D;

output borow;

assign D=a^b^cin;

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 assign borow=(!a&b)|(b&cin)|(!a&cin);

endmodule

Testbench:

module fullsubtractor;

reg a,b,cin;

wire D,borow;

fs1 uut(.a(a),.b(b),.cin(cin),.D(D),.borow(borow));

initial begin

#10 a=1'b0;b=1'b0;cin=1'b0;

#10 a=1'b0;b=1'b0;cin=1'b1;

#10 a=1'b0;b=1'b1;cin=1'b0;

#10 a=1'b0;b=1'b1;cin=1'b1;

#10 a=1'b1;b=1'b0;cin=1'b0;

#10 a=1'b1;b=1'b0;cin=1'b1;

#10 a=1'b1;b=1'b1;cin=1'b0;

#10 a=1'b1;b=1'b1;cin=1'b1;

#10$stop;

end

endmodule

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 Output Waveform:

Result:The truthtable of Full subtractor is verified using Verilog HDL.

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 4.4:1 Multiplexer

Aim:To verify and perform the operation of 4x1 Multiplexer using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module mux41_b(a, s, c);

input [3:0]a;

input [1:0]s;

output c;

reg c;

always@(a or s)

begin

case(s)

2'b00:c=a[0];

2'b01:c=a[1];

2'b10:c=a[2];

2'b11:c=a[3];

default:c=a[0];

endcase

end

endmodule

module mux41_d(a, s, c);

input [0:3]a;

input [1:0]s;

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 output c;

assign c=(!s[0]&!s[1]&a[0])|(s[0]&!s[1]&a[1])|(!s[0]&s[1]&a[2])|(s[0]&s[1]&a[3]);

endmodule

Testbench:

module mux41_tst_v;

reg[3:0]a;

reg[1:0]s;

wire c;

mux41 uut(.a(a),.s(s),.c(c));

initial begin

a=4'b0101;

s=2'b00;

#100s=2'b00;

#100s=2'b01;

#100s=2'b10;

#100s=2'b11;

end

endmodule

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 Output Waveform:

Result:The truthtable of 4x1 Multiplexer is verified using Verilog HDL.

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 5. 1:4 Demultiplexer

Aim:To verify and perform the operation of 1x4 Demultiplexer using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module demux1to4_b(a, s, c);

input a;

input [1:0]s;

output [0:3]c;

reg c;

always@(a or s)

begin

case(s)

2'b00:c={a,3'b000};

2'b01:c={1'b0,a,2'b00};

2'b10:c={2'b00,a,1'b0};

2'b11:c={3'b000,a};

default:c={a,3'b000};

endcase

end

endmodule

module demux1to4_d(a, s, c);

input a;

input [1:0]s;

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 output [0:3] c;

assign c={(!s[0]&!s[1]&a),(s[0]&!s[1]&a),(!s[0]&s[1]&a),(s[0]&s[1]&a)};

endmodule

Testbench:

module demux1to4_tst_v;

reg a;

reg[1:0]s;

wire [0:3]c;

demux1to4 uut(.a(a),.s(s),.c(c));

initial begin

a=1;

s=2'b00;

#100s=2'b00;

#100s=2'b01;

#100s=2'b10;

#100s=2'b11;

end

endmodule

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 Output Waveform:

Result:The truthtable of 1x4 Demultiplexer is verified using Verilog HDL.

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 6.Encoder

Aim:To verify and perform the operation of 4x2 Encoder using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module enc(a, b);

input[3:0] a;

output reg [1:0] b;

always@(a)

begin

case(a)

4'b0001:b=2'b00;

4'b0010:b=2'b01;

4'b0100:b=2'b10;

4'b1000:b=2'b11;

default:b=2'b00;

endcase

end

endmodule

Testbench

module encoder_tst_v;

reg [3:0] a;

wire [1:0]b;

enc uut(.a(a), .b(b));

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 initial

begin

a= 4'b0001;

#100 a=4'b0010;

#100 a=4'b0100;

#100 a=4'b1000;

#100 $stop;

end

endmodule

Output Waveform:

Result:The truthtable of 4x2 Encoder is verified using Verilog HDL.

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 7.Decoder

Aim:To verify and perform the operation of 2x4 Decoder using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module dec(a, b);

input[1:0] a;

output[3:0] b;

reg[3:0]b;

always@(a)

begin

b[3]=a[1]&a[0];

b[2]=!a[1]&a[0];

b[1]=a[1]&!a[0];

b[0]=!a[1]&!a[0];

end

endmodule

Testbench

module dec_v;

reg[1:0]a;

wire[3:0]b;

dec uut(.a(a),.b(b));

initial

begin

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 a=2'b00;

#100a=2'b01;

#100a=2'b10;

#100a=2'b11;

end

endmodule

Output Waveform

Result:The truthtable of 2x4 Decoder is verified using Verilog HDL.

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 8.D Flipflop

Aim:To verify and perform the operation of D Flipflop using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module dff(d, clk, reset, q);

input d;

input clk;

input reset;

output q;

reg q;

always@(posedge clk or posedge reset)

begin

if(reset)

q<=1'b0;

else

q<=d;

end

endmodule

Testbench:

module dff_tst_v;

reg d;

reg clk;

reg reset;

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 wire q;

dff uut(.d(d),.clk(clk),.reset(reset),.q(q));

initial begin

d=0;

clk=1;

reset=1;

#20 reset=0;

d=1;

#10 d=0;

#20 d=1;

#10 d=0;

end

always

#5 clk=~clk;

Endmodule

Output Waveform

Result:The truthtable of D Flipflop is verified using Verilog HDL.

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 9.JK Flipflop

Aim:To verify and perform the operation of JK Flipflop using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module jkff(j, k, clk, reset, q);

input j;

input k;

input clk;

input reset;

output q;

reg q;

always@(posedge clk or posedge reset)

begin

if(reset==1'b1)

q<=1'b0;

else

case({j,k})

2'b00:q<=q;

2'b01:q<=1'b0;

2'b10:q<=1'b1;

2'b11:q<=~q;

default:q<=q;

endcase

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 end

endmodule

Testbench

module jkff_tst_v;

reg j;

reg k;

reg clk;

reg reset;

wire q;

jkff uut(.j(j),.k(k),.clk(clk),.reset(reset),.q(q));

initial begin

j=0;

k=0;

clk=1;

reset=1;

#20 reset=0;

#10j=0;

k=1;

#10j=1;

k=0;

#10j=1;

k=1;

#40 $stop;

end

always

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 #5clk=~clk;

Endmodule

Output Waveform:

Result:The truthtable of JK Flipflop is verified using Verilog HDL.

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 10.SR Flipflop

Aim:To verify and perform the operation of SR Flipflop using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module srff(s, r, clk, reset, q);

input s,r,clk,reset;

output q;

reg q;

reg [1:0]sr;

always@(posedge clk,posedge reset)

begin

sr={s,r};

if(reset==0)

begin

case(sr)

2'd1:q=1'b0;

2'd2:q=1'b1;

2'd3:q=1'bx;

default:begin end

endcase

end

else

q=1'b0;

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 end

endmodule

Testbench

module srff_tst_v;

reg s;

reg r;

reg clk;

reg reset;

wire q;

srff uut(.s(s),.r(r),.clk(clk),.reset(reset),.q(q));

initial begin

s=0;

r=0;

clk=1;

reset=1;

#20 reset=0;

#10s=0;

r=1;

#10s=1;

r=0;

#10s=1;

r=1;

#40 $stop;

end

always

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 #5clk=~clk;

Endmodule

Output Waveform:

Result:The truthtable of SR Flipflop is verified using Verilog HDL.

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 11.SISO Registers

Aim:To verify and perform the operation of SISO registers using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module siso1(sin,clk,reset,sout);

input sin;

input clk;

input reset;

output reg sout;

reg r1,r2,r3;

always@(posedge clk or posedge reset)

begin

if(!reset)

begin

sout<=1'b0;

r1<=1'b0;

r2<=1'b0;

r3<=1'b0;

end

else

begin

r1<=sin;

r2<=r1;

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 r3<=r2;

end

end

endmodule

Testbench:

module siso_tst_v;

reg sin;

reg clk;

reg reset;

wire sout;

siso1 uut(.sin(sin),.clk(clk),.reset(reset),.sout(sout));

initial

begin

sin=0;

clk=1;

reset=1;

#20reset=0;

sin=1'b1;

#40sin=1'b0;

#40sin=1'b1;

#40sin=1'b1;

#80;

end

always

#5clk=~clk;

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 Endmodule

Output Waveform:

Result:The opeartion of SISO register is verified using Verilog HDL.

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 12.SIPO Registers

Aim:To verify and perform the operation of SISO register using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module sipo(sin,clk,reset,pout);

input sin;

input clk;

input reset;

output [3:0]pout;

dff a1(.d(sin),.clk(clk),.reset(reset),.q(pout[0]));

dff a2(.d(pout[0]),.clk(clk),.reset(reset),.q(pout[1]));

dff a3(.d(pout[1]),.clk(clk),.reset(reset),.q(pout[2]));

dff a4(.d(pout[2]),.clk(clk),.reset(reset),.q(pout[3]));

endmodule

Testbench:

module sipo_tst_v;

reg sin;

reg clk;

reg reset;

wire[3:0]pout;

sipo uut(.sin(sin),.clk(clk),.reset(reset),.pout(pout));

initial

begin

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 sin=0;

clk=1;

reset=1;

#300reset=1'b0;

sin=1'b1;

#100sin=1'b0;

#100sin=1'b1;

#100sin=1'b1;

end

always

#50clk=~clk;

Endmodule

Output Waveform:

Result:The operation of SIPO register is verified using Verilog HDL.

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 13.2bit Comparator

Aim:To verify and perform the operation of 2 bit comparator using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module comparator_2bit(a,b,equal,greater,lower);

input [1:0]a;

input [1:0]b;

output equal;

output greater;

output lower;

assign equal=(a==b)?1:0;

assign greater=(a>b)?1:0;

assign lower=(a<b)?1:0;

endmodule

Testbench:

module comparator2_tst_v;

reg [1:0]a;

reg [1:0]b;

wire equal;

wire greater;

wire lower;

comparator_2bit uut(.a(a),.b(b),.equal(equal),.greater(greater),.lower(lower));

initial

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 begin

a=10;

b=01;

#20 a=00; b=01;

#20 a=11; b=11;

#40 $stop;

end

endmodule

Output Waveform:

Result:The operation of two bit comparator is verified using Verilog HDL.

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 14.Decade Counter

Aim:To verify and perform the operation of decade counter using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module decade_counter( input clock,

input reset,

output reg [3:0] q );

always@(posedge clock)

begin

if(reset)

q <=4'b0000;

else if(q<=4'b1000)

q <= q+1'b1;

else

q <= 4'b0000;

end

endmodule

Testbench:

module mod_10_counter_test;

// Inputs

reg clock;

reg reset;

// Outputs

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 wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

decade_counter uut (

.clock(clock),

.reset(reset),

.q(q)

);

always

#50 clock= ~ clock;

initial begin

clock=0;

// Initialize Inputs

reset = 1;

#100;

reset=0;

#100;

reset=0;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

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 Output Waveform:

Result:The operation of decade counter is verified using Verilog HDL.

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 15.4bit parallel adder

Aim:To verify and perform the operation of 4 bit parallel adder using Veilog HDL.

Apparatus:

1.Xilinx ISE 8.1i simulation software

2.Personal Computer

Program:

module parallel_adder(p, q, carry_in, sum, carry_out);

input [3:0]p,q;

input carry_in;

output reg [3:0]sum;

output reg [3:0]carry_out;

wire c1,c2,c3;

fa u1(p[0],q[0],carry_in,sum[0],c1);

fa u2(p[1],q[1],c1,sum[1],c2);

fa u3(p[2],q[2],c2,sum[2],c3);

fa u4(p[3],q[3],c3,sum[3],carry_out);

endmodule

Testbench:

module parallel_adder_tst_v;

reg[3:0]p,q;

reg carry_in;

wire[3:0]sum;

wire carry_out;

parallel_adder(.p(p),.q(q),.carry_in(carry_in),.sum(sum),.carry_out(carry_out));

initial

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 begin

p=4'b0100;

q=4'b0011;

carry_in=1'b1;

#10

#10 p=4'b1010;

#10 q=4'b1010;

#10 carry_in=1'b0;

end

endmodule

Output Waveform:

Result: The operation of 4 bit parallel adder is verified using Verilog HDL.

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 UART

module UART_TX

#(parameter CLKS_PER_BIT = 217)

input i_Clock,

input i_TX_DV,

input [7:0] i_TX_Byte,

output o_TX_Active,

output reg o_TX_Serial,

output o_TX_Done

);

parameter IDLE = 3'b000;

parameter TX_START_BIT = 3'b001;

parameter TX_DATA_BITS = 3'b010;

parameter TX_STOP_BIT = 3'b011;

parameter CLEANUP = 3'b100;

reg [2:0] r_SM_Main = 0;

reg [7:0] r_Clock_Count = 0;

reg [2:0] r_Bit_Index = 0;

reg [7:0] r_TX_Data = 0;

reg r_TX_Done = 0;

reg r_TX_Active = 0;

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 always @(posedge i_Clock)

begin

case (r_SM_Main)

IDLE :

begin

o_TX_Serial <= 1'b1; // Drive Line High for Idle

r_TX_Done <= 1'b0;

r_Clock_Count <= 0;

r_Bit_Index <= 0;

if (i_TX_DV == 1'b1)

begin

r_TX_Active <= 1'b1;

r_TX_Data <= i_TX_Byte;

r_SM_Main <= TX_START_BIT;

end

else

r_SM_Main <= IDLE;

end // case: IDLE

// Send out Start Bit. Start bit = 0

TX_START_BIT :

begin

o_TX_Serial <= 1'b0;

// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)

begin

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 r_Clock_Count <= r_Clock_Count + 1;

r_SM_Main <= TX_START_BIT;

end

else

begin

r_Clock_Count <= 0;

r_SM_Main <= TX_DATA_BITS;

end

end // case: TX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish

TX_DATA_BITS :

begin

o_TX_Serial <= r_TX_Data[r_Bit_Index];

if (r_Clock_Count < CLKS_PER_BIT-1)

begin

r_Clock_Count <= r_Clock_Count + 1;

r_SM_Main <= TX_DATA_BITS;

end

else

begin

r_Clock_Count <= 0;

// Check if we have sent out all bits

if (r_Bit_Index < 7)

begin

r_Bit_Index <= r_Bit_Index + 1;

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 r_SM_Main <= TX_DATA_BITS;

end

else

begin

r_Bit_Index <= 0;

r_SM_Main <= TX_STOP_BIT;

end

end

end // case: TX_DATA_BITS

// Send out Stop bit. Stop bit = 1

TX_STOP_BIT :

begin

o_TX_Serial <= 1'b1;

// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)

begin

r_Clock_Count <= r_Clock_Count + 1;

r_SM_Main <= TX_STOP_BIT;

end

else

begin

r_TX_Done <= 1'b1;

r_Clock_Count <= 0;

r_SM_Main <= CLEANUP;

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 r_TX_Active <= 1'b0;

end

end // case: TX_STOP_BIT

// Stay here 1 clock

CLEANUP :

begin

r_TX_Done <= 1'b1;

r_SM_Main <= IDLE;

end

default :

r_SM_Main <= IDLE;

endcase

end

assign o_TX_Active = r_TX_Active;

assign o_TX_Done = r_TX_Done;

endmodule

TESTBENCH

`timescale 1ns/10ps

`include "UART_TX.v"

module UART_TB ();

// Testbench uses a 25 MHz clock

// Want to interface to 115200 baud UART

// 25000000 / 115200 = 217 Clocks Per Bit.

parameter c_CLOCK_PERIOD_NS = 40;

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 parameter c_CLKS_PER_BIT = 217;

parameter c_BIT_PERIOD = 8600;

reg r_Clock = 0;

reg r_TX_DV = 0;

wire w_TX_Active, w_UART_Line;

wire w_TX_Serial;

reg [7:0] r_TX_Byte = 0;

wire [7:0] w_RX_Byte;

UART_RX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_Inst

(.i_Clock(r_Clock),

.i_RX_Serial(w_UART_Line),

.o_RX_DV(w_RX_DV),

.o_RX_Byte(w_RX_Byte)

);

UART_TX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_Inst

(.i_Clock(r_Clock),

.i_TX_DV(r_TX_DV),

.i_TX_Byte(r_TX_Byte),

.o_TX_Active(w_TX_Active),

.o_TX_Serial(w_TX_Serial),

.o_TX_Done()

);

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 // Keeps the UART Receive input high (default) when

// UART transmitter is not active

assign w_UART_Line = w_TX_Active ? w_TX_Serial : 1'b1;

always

#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;

// Main Testing:

initial

begin

// Tell UART to send a command (exercise TX)

@(posedge r_Clock);

@(posedge r_Clock);

r_TX_DV <= 1'b1;

r_TX_Byte <= 8'h3F;

@(posedge r_Clock);

r_TX_DV <= 1'b0;

// Check that the correct command was received

@(posedge w_RX_DV);

if (w_RX_Byte == 8'h3F)

$display("Test Passed - Correct Byte Received");

else

$display("Test Failed - Incorrect Byte Received");

$finish();

end

initial

begin

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 // Required to dump signals to EPWave

$dumpfile("dump.vcd");

$dumpvars(0);

end

endmodule

OUTPUT WAVEFORMS

Result: The operation of UART is verified using Verilog HDL.

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 Verilog code for the Moore FSM Sequence Detector is designed based on the state
diagram and block diagram of the Moore FSM:

// fpga4student.com: FPGA projects, Verilog projects, VHDL projects

// Verilog project: Verilog code for Sequence Detector using Moore FSM
// The sequence being detected is "1011" or One Zero One One
module Sequence_Detector_MOORE_Verilog(sequence_in,clock,reset,detector_out
);
input clock; // clock signal
input reset; // reset input
input sequence_in; // binary input
output reg detector_out; // output of the sequence detector
parameter Zero=3'b000, // "Zero" State
One=3'b001, // "One" State
OneZero=3'b011, // "OneZero" State
OneZeroOne=3'b010, // "OnceZeroOne" State
OneZeroOneOne=3'b110;// "OneZeroOneOne" State
reg [2:0] current_state, next_state; // current state and next state
// sequential memory of the Moore FSM
always @(posedge clock, posedge reset)
begin
if(reset==1)
current_state <= Zero;// when reset=1, reset the state of the FSM to "Zero"
State
else
current_state <= next_state; // otherwise, next state
end
// combinational logic of the Moore FSM
// to determine next state
always @(current_state,sequence_in)
begin
case(current_state)
Zero:begin
if(sequence_in==1)
next_state = One;
else
next_state = Zero;
end
One:begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = One;
end

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 OneZero:begin
if(sequence_in==0)
next_state = Zero;
else
next_state = OneZeroOne;
end
OneZeroOne:begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = OneZeroOneOne;
end
OneZeroOneOne:begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = One;
end
default:next_state = Zero;
endcase
end
// combinational logic to determine the output
// of the Moore FSM, output only depends on current state
always @(current_state)
begin
case(current_state)
Zero: detector_out = 0;
One: detector_out = 0;
OneZero: detector_out = 0;
OneZeroOne: detector_out = 0;
OneZeroOneOne: detector_out = 1;
default: detector_out = 0;
endcase
end
endmodule

Verilog Testbench for the Moore FSM Sequence Detector:

`timescale 1ns / 1ps

// fpga4student.com: FPGA projects, Verilog projects, VHDL projects
// Verilog project: Verilog code for Sequence Detector using Moore FSM
// Verilog Testbench for Sequence Detector using Moore FSM
module tb_Sequence_Detector_Moore_FSM_Verilog;

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 // Inputs
reg sequence_in;
reg clock;
reg reset;

// Outputs
wire detector_out;

// Instantiate the Sequence Detector using Moore FSM

Sequence_Detector_MOORE_Verilog uut (
.sequence_in(sequence_in),
.clock(clock),
.reset(reset),
.detector_out(detector_out)
);
initial begin
clock = 0;
forever #5 clock = ~clock;
end
initial begin
// Initialize Inputs
sequence_in = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#30;
reset = 0;
#40;
sequence_in = 1;
#10;
sequence_in = 0;
#10;
sequence_in = 1;
#20;
sequence_in = 0;
#20;
sequence_in = 1;
#20;
sequence_in = 0;
// Add stimulus here

end

endmodule

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 Simulation Waveform of the sequence detector using Moore FSM in Verilog:

RESULT: The Moore FSM Sequence Detector is designed and verified using Verilog HDL.

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