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Lec15 Combinational circuits-IV

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9 views9 pages

Lec15 Combinational circuits-IV

Uploaded by

agarwalaayush886
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EE213M Digital Circuits

Combinational Circuits

16/02/2024 EE213M 1
Multiplexer
• A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line.
• There are 2𝑛 input lines and 𝑛 selection lines whose bit combinations determine which input is selected.
• The multiplexer is often labeled “MUX” in block diagrams.

16/02/2024 EE213M 2
Multiplexer
• A multiplexer is also called a data selector, since it selects one of many inputs and steers the binary
information to the output line.

16/02/2024 EE213M 3
Multiplexer
• A 4 × 1 Multiplexer circuit diagram is shown in
Figure.

16/02/2024 EE213M 4
Problem
• Implement a Boolean function F=σ(1, 2, 6, 7) with the Multiplexer

16/02/2024 EE213M 5
Problem
• Implement a Boolean function F(A,B,C,D)=σ(1, 3, 4, 11, 12, 13, 14, 15) with the Multiplexer

16/02/2024 EE213M 6
Demultiplexer
• A De-multiplexer is a combinational circuit that selects information from one input lines and directs it to
a multiple output line.

𝐼0

𝐼1
𝑌 De-Mux 𝐼2

𝐼3

𝑆0 𝑆1

16/02/2024 EE213M 7
Problem
• An ABCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit in BCD to an
appropriate code for the selection of segments in an indicator used to display the decimal digit in a familiar
form. The seven outputs of the decoder (a, b, c, d, e, f, g) select the corresponding segments in the display, as
shown in Fig. P4.9(a) . The numeric display chosen to represent the decimal digit is shown in Fig. P4.9(b) .
Using a truth table and Karnaugh maps, design the BCD-to-seven-segment decoder using a minimum
number of gates. The six invalid combinations should result in a blank display.

16/02/2024 EE213M 8
Problem Set
Q.1 Design a combinational circuit that converts a four-bit Gray code to a bit four binary number. Implement the circuit
with exclusive-OR gates.

Q.2 Design a half-subtractor circuit with inputs x and y and outputs Diff and B out . The circuit subtracts the bits x – y and
places the difference in D and the borrow in Bout

Q.3 Design a full-subtractor circuit with three inputs x , y , B in and two outputs Diff and Bout . The circuit subtracts x – y –
Bin , where B in is the input borrow, Bout is the output borrow, and Diff is the difference.

Q.4 Design a combinational circuit that generates the 9’s complement of a BCD digit.

Q.5 Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to-4-line decoder.

16/02/2024 EE213M 9

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