Organization 1-85

a n d Computer Combinational Logic

national Lo Diaital
Principles

fwo inverters provide the complement of the inputs, and each one of tour
11,15.10 one of the minterms
AND gates generates
The Table 1.15.1 shows the truth table for a 2-to-4 decoder.

tf enable input is 1 (EN = ) , one, and only one, of the outputs Yg to Yy is active

Possible
given input.
output for a

The output Yo is active, 1.e. Yo= l when inputs A = B = 0, the output Y, is active
oulp
Th =0 and B =1,
when inputs A
is 0, 1.e. EN =
0, then all the outputs 0.
ecoder If enable input are

Example 1.15.1 raw the circuit for 3 to 8 decoder and explain.

Drat
tputs
dan :
Solution: Fig. 1.15.3
Fig. 1.15.3 shows 3-to-8 line decoder. Here, 3 inputs are decoded into eight
of the minterms of the 3 input variables. The three
each output represent
one
outpu ifs.

complement of the inputs, and each one of the eight AND gates
provide the
puts inverters

ot the minterms. Enable B C

one
generates
to activate decoded
input is provided
based on data inputs A, B,
and
output
truth table for
C. The
table shows the C
Out 3-to-8 decoder.
D-Y8C
Outputs
tpu EN
Inputs
A B CYYY YY Y, Y,Y D -Y, =ABC

xXX0 0 0 0 0 0 0 0 D--Xet
01
1 00 0 0 0 0 0 0 0 =D--Hsc
1 0 01 0 0 0 0 01 0 0

1 0
1 0 000 0 01 0 0
10 110 0 001 0 0 0 D-YABC
1 1 00 0 0 010 0 00
1 1 0 10 0 10 00 0 0
1 1 1 0 0 1 0 0 0 00 0 Y,ABC
1 1 1 1 1 000 0000 Enable (EN)
Table 1.15.2 Truth table for a 3 to 8
decoder Fig. 1.15.3 3:8 line decoder

Decoders
1.15.2 Expanding Cascading
decoder circuits can be connected together to form a larger decoder circuit
Binary
Fig. 1.154 shows the 4 x 16 decoder using two 3 x 8 decoders.

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 DigitalPrinciples and Computer Organization
- 86 Combiational n d Comp
iples aand Compuler Organization
Loge Prnoples
Digital 1-87
Combinafional Logic
A Og
B-
141381)
A
-O
O1o
3 8 D3 :8 -O11
Decoder Yk
Decoder Ya-O12
-Os -O13 b
-Og Ye-O14
O7 EN .O15
EN 1/2 74LS139 1ALS1382)
EN d 1G 1Yg
Fig. 1.15.4

decoders. 1A -
is used to enable/disable the
D
Here, one input line (D) s-Y
and the other is disabled. Thus
When D 0, the top decoder is enabled
=
th
bottom decoder outputs are all 1s, and the top eight outputs generate minter
erms
-Ys
0000to 0111.
When D=1, the enable conditions are reversed and thus bottom decoder outn 74LS132(3)
decoder all 1s.
minterms 1000 to 1111, while the outputs of the top are Yob-Y18
generate Y Y7
5-to-32 decoder using one 2-to-4 and four 3-to-8 decoder 1Cs.
Example 1.15.2 Design -Y18
AU:Dec.-11,May-15,Marks16 -Y9
Solution: The Fig. 1.15.5 shows the construction of 5-to-32 decoder using four 74LS138 -21
and half 74LS139. The half section of 74LS139 IC is used as a 2-to-4 decoder to decode
28 73
the two higher order inputs, D and E. The four outputs of this decoder are used to
enable one of the four 3 to 8 decoders. The three lower order inputs A, B and Care 4LS138(4)
connected in parallel to four 3 to 8 decoders. This means that the same output pin of
each of the four 3-to-8 decoders is selected but only one is enabled. The remaining
enable signals of four 3-to-8 decoder ICs are connected in parallel to construct enable
signals for 5-to-32 decoder.
EN
(See Fig. 1.15.5 on next page.) ENg

1.15.3 Realization of Boolean Function using Decoder Fig. 1.15.5 5-to-32 decoder using 74LS138 and 74L$139

The combination of decoder and external logic gates be used to

can
implement Examples for Understanding
single or multiple output functions.
.When decoder output is active high, it
generates minterms (product terms) for Example 1.15.3 Implement Boleanfunction F m (1, 2, 3, 7) using 3 :8 decodier.
input variables; i.e. it makes selected output logic 1. In such case to implement Solution:
SOP function we have to take sum of selected
product terms generated by
decoder. Step 1: Connect function variables as inputs to the decoder.

Step 2: Logically OR the outputs correspond to present minterms to obtain the output.

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1 89

Examples with Solutions Combinational Log

F Example 1.15.5 Implement the
following multiple output
3:8
Decoder
4-line to 16-line decoder combinational logic circuit using a
f. = Em (1, 2, 4, 7, 8, 11, 12, 13), f2 2m (2, 3, 9, 11)
=

= Em (10, 12, 13, 14), Ja =

Zm (2, 4, 8)
EN Solution: AUE Dec 08, Mats 10
Fig. 1.15.6

combinational logic using a 4 line

d Inputs
multiple output
Iplement the following
Example 1.15.4
decoder.
+ABCD +ABCD +ABCD
to 16 line
Y-ABCD+ABCD+ABCD

Y 2 - A B C D + A B C D + A B C D + A B C D

4:16
Y3 =ABCD+ABCD +ABCD.

Solution
Decoder Yg

Y40
D
Step 1 :

Y =
Write the

m,3,2 6,
function in their minterm

10, 11) Y
torms

=m (1, 4, 5, 13) Y3 =m (7, 14, 15)

EN
12
11

13
D
of decoder corresponding
to the minterms in
Step 2 : Logically OR the outputs
functions.
Y15
Fig. 1.15.8
Example 1.15.6 Design and
innplement a full adder circuit
O using a 3:8 decoder.
O
O2 Y1 Solution: Truth table for full adder is AU : May-11. Marks 5
O3 as shown in the Table 1.15.3.
Inputs Outputs
D
B Cin Carry Sum
4:16
C
D Decoder Og
7 o Y2
0
1 0 A A
3:8
O10 0 0
Decoder -Cary
O11 0 0
Cin C
O12 Y3
O13 0 0

O14 0 -Sum
O15

Fig. 1.15.7 Table 1.15.3 Truth table for full-adder Fig. 1.15.9

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 Combinational Logic
and Computer
Organi
anizafion - 91
Principles
Digital
90

1 . 1 6 Encoders

AU Dec.06.10.12.14 18 May070510.19
Computer
Organze d e c o d e r
and
ates
Phnciples
and using
encoder is a digital circuit that
DIgital
converter
.
An data
BCD
code

cnerforms the inverse operation of a inputs

Examples for Practice perf n data
e x v e s 3
to
N A N D
gates
fiunctions decoder.
2n outputs
an
the Encoder
using
Design
by a'bcde"
(or fewer) input
1.15.7 defined
encoder has 2
dernder

+
e n p l e

2x4
circuit

+ bcde An Enable
output lines.
abc
Dsign logic =
andn
1.15.8
combinational F2
lines inputs
+ abcd
c x a m p l e

suitable d.
a acd
the output lines generate the
Example 1.15.9
Design
Fl=&bc+

+
abcde using
suitalble
decoder . I n encoder
to the input
g . 1.16.1 General
structure of encoder

F3=abel+ab
cd fiunction
code corresponding
output binary
multiple
following 3) value.
the 7)+d(2,
in the
Implement
4 shows the general structure of the encoder circuit. As shown
1.15.10
B
O=m(0,
5, 6
The Fig. 1.16.1
Example flA. the decoded information is presented as 2" inputs producing n possible
Fig. 1.16.1
)=m(1,

a4,
B 2, 4 6)
C)-m0,
fs(4, B,
outputs.

D e c o d e r s

of
Applications

Decimal to BCD Encoder

1.15.4
are
1.16.1 74XX147
decoders
The uses of decimal to BCD encoder, (11)
circuits .The
Code converters

I m p l e m e n t a t i o n
of
combinational

usually has ten input lines and (121 2

Address decoding
four output lines. (13 3 (9)
BCD to 7-segment
decoder

The decoded
decimal data acts as (1 6 ) BCD outputs
Decimal (2 5
encoder and encoded inputs D(14)
aninput for
1.15.5 Decoder ICs Function
BCD output is available on the (3)
IC number
3 8 Decoder four output lines. (4)
74138
Dual 2: 4
Decoder
. The Fig. 1.16.2 shows the logic 58
74139 decoder
BCD to
decimal symbol for decimal to BCD
7442 decoder
encoder IC, IC 74XX147.
BCD to 7-segment Fig. 1.16.2 Logic symbol for 74XX147 (Decimal
7447
Decoder ICs I t has nine input lines and four to BCD encoder)
Table 1.15.4

output lines.
Review Questions Both input and output lines are asserted active low.
1. Define decoder. When this
I t is important to note that there is no input line for decimal zero.
2. Define binary decoder.
decoder. condition occurs, all output lines are 1.
the working of 2: 4 binary
AU:May-07, Dec.-12, Marks 2
3. Explan
3 8 decoders.
4x 16 decoder constructed with two
x
4. Draw a .The function table for the 74XX147 is shown in Table 1.16.1.
Boolean function using decoder.
5. State the procedure to implement
6. Mention the uses of decoders. AU Dec.-06, Marks 2 Decimal value Inputs Outputs
7. What is decoder ? Draw the block diagram and truth table for 2 to 4 decoder.

AU: May-09, 19, Marks 2

12 3 4 5 67 89 DCBA
0 11 1 11 1 1 1 1 1 1
8. Explain in detail about decoders. AU: Dec.-18, Marks 6

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