(1) Abstract:

This study presents the characterization of Junction Field Effect Transistors (JFETs) and
Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). The experimental
procedure involved analyzing the static and dynamic characteristics of these transistors to
understand their behavior and performance under varying conditions. Key parameters such as
drain current, gate-source voltage and drain-source voltage were measured and plotted to
determine the operational regions. For the JFET, pinch-off voltage and transconductance were
determined, while the MOSFET analysis focused on threshold voltage and subthreshold
characteristics. The findings illustrate the differences in performance and application between
the two devices, highlighting their relevance in modern electronic circuits.

(2) Objectives:
The objectives of this experiment are to
1. Understand the basic operation of JFETs and MOSFETs and determine the threshold
voltages.
2. Measure the current and voltage to obtain the I-V characteristics.
3. Find the different operating regions for both JFETs and MOSFETs.

(3) Theory:
Transistors play a critical role in modern electronics, with two of the most common types being
the Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Bipolar Junction
Transistors (BJTs). In the 1960s and 1970s, BJTs dominated the market, but today, MOSFETs
are primarily used in integrated circuits (ICs). BJTs still find use in specific areas such as analog
circuits (e.g., amplifiers), high-speed circuits, and power electronics.

Key differences between BJTs and FETs:

1. Control Mechanism: BJTs are current-controlled, while FETs (including MOSFETs) are
voltage-controlled.
2. Input Impedance: BJTs have relatively low input impedance, whereas FETs have very
high input impedance.
Within FETs, there are two main types:
 Junction Field Effect Transistor (JFET): Known for high power dissipation, making
them less suitable for densely packed ICs.
 Metal Oxide Semiconductor Field Effect Transistor (MOSFET): Preferred for ICs
due to their lower power dissipation.

 JFET Structure and Operation:

A transistor is a current-controlled device involving electron and hole flow, known as a bipolar
junction transistor (BJT). In contrast, a Field Effect Transistor (FET) is a unipolar, voltage-
controlled device where current in n-channel FETs is via electron flow and in p-channel FETs
via
 hole flow. While FETs can perform similar functions as BJTs, their biasing and characteristics
differ, so applications are chosen based on their strengths and weaknesses.
FET Characteristics:
1. High input impedance (~100 MΩ).
2. No offset voltage when used as a switch.
3. Less sensitive to radiation compared to BJTs.
4. Lower noise, ideal for low-level amplifiers.
5. Better thermal stability than BJTs.
JFET Structure:
 n-channel JFET: p-type regions diffused into n-type material.
 p-channel JFET: n-type regions diffused into p-type material.

Figure 1: Internal structure of n-channel and p-channel JFETs.

In p-channel and n-channel JFETs, the reversal of p- and n-type materials causes the current directions to
reverse due to the polarity differences in gate-to-source voltage (VGS) and drain-to- source voltage (VDS). In a
p-channel JFET, increasing positive voltages from gate to source constrict the channel, and the resulting VDS is
negative. The characteristic curve shows a drain saturation current (IDSS) of 6 mA and a pinch-off voltage (VP)
of +6 V.

Figure 2: JFET symbols: (a) n-channel (b) p-channel

 Figure 3: p-channel JFET drain-source characteristics with IDSS = 6 mA and VP = +6 V.

Figure 4 shows the transfer characteristics of a JFET. The curve shows a drain saturation
current (IDSS) of 4 mA and a pinch-off voltage (VP) of +3 V.

Figure 4: Transfer characteristics of p-channel JFET with IDSS = 4 mA and VP = +3 V.

 MOSFET Structure and Operation:

MOSFETs are the most widely used FETs and belong to the Insulated Gate Field Effect
Transistor (IGFET) group, with the gate insulated from the channel by a silicon dioxide (SiO₂)
layer. MOSFETs have three main terminals—Gate (G), Source (S), and Drain (D)—with an
optional fourth, the bulk/body terminal (B).
There are four types of MOSFETs:
1. Enhancement mode n-type (NMOS)
2. Enhancement mode p-type (PMOS)
3. Depletion mode n-type
4. Depletion mode p-type
The transistor type depends on whether the channel between drain and source is induced
(enhancement) or implanted (depletion), and whether the current flow is by electrons (n-type) or
holes (p-type). This manual focuses on enhancement-type MOSFETs, particularly NMOS.

Figure 5: Schematic cross-section of an enhancement-type NMOS transistor.

In an enhancement-type MOSFET, applying a positive voltage to the gate repels holes from the
channel region, forming a depletion region. Simultaneously, electrons are attracted, creating an
n-channel between the drain and source, allowing current flow when a voltage is applied
between them. This process is called enhancement and inversion. The threshold voltage (Vth)
is the minimum gate-to-source voltage (VGS) required to form the channel, with NMOS having
a positive Vth and PMOS a negative Vth.
In contrast, depletion-type MOSFETs have a pre-existing conductive channel, allowing current
flow even at VGS = 0, due to the physical implantation of an n-type region between drain and
source.

Figure 6: Symbols for enhancement-type NMOS and PMOS transistors.

 Figure 7: Drain current, ID vs. gate-to-source voltage, VGS graph of an enhancement
type NMOS transistor for adrain-to-source voltage above the gate overdrive voltage (VGS
– Vth) showing threshold voltage Vtn.

– VDS ch𝑛aracteristics curve of adevice with 𝑘′ (𝑊/𝐿) = 1 mA/V2

Figure 8: (a) an n-channel enhancement type MOSFET with VGS and VDS applied (b) the IDS

showing the three operating regions.

Circuit Diagram:

Figure 9: Circuit for plotting the IDS vs VGS that is, transfer characteristics of p-
channel JFET (J176)

Figure 10: Circuit for plotting the IDS vs VGS that is, transfer characteristics of n-channel
MOSFET (IRF540)

(3) Apparatus:
 J176 (p-channel JFET); 2N7000/IRF540N (n-channel enhancement type MOSFET);
 Resistance (R =0.977k ohm)
 Project Board
 DC Power Supply
 Multimeter
 Connecting Leads
(4) Experimental & Simulation Results:

 Experimental Data:

Table 1 Measured data of the voltage and current for the transfer characteristic curve of a
JFET. Dain- to-Source voltage.
VG (V) Gate Voltage Load Voltage Drain Current,
VGS (V) VRS (V) IDS (mA)

Table 2 Measured data of the voltage and current for the output characteristic curve of a
JFET. Gate- to-Source voltage.
Drain Voltage, Load Voltage Drain Current,
VDS (V) VRS (V) IDS (uA)
Table 3 Measured data of the voltage and current for the transfer characteristic curve of a
MOSFET. Dain-to-Source voltage.
Gate Voltage Load Voltage Drain Current,
VGS (V) VRS (V) IDS (mA)
  Simulation Data:
Table 1 Simulation data of the voltage and current for the transfer characteristic curve of
a JFET. Dain- to-Source voltage.
VG (V) Gate Voltage Load Voltage Drain Current,
VGS (V) VRS (V) IDS (mA)

Table 2 Simulation data of the voltage and current for the Output characteristic curve of a
JFET. Gate- to-Source voltage.
Drain Voltage, Load Voltage Drain Current,
VDS (V) VRS (V) IDS (mA)
Table 3 Simulation data of the voltage and current for the transfer characteristic curve of
a MOSFET. Dain-to-Source voltage.
Gate Voltage Load Voltage Drain Current,
VGS (V) VRS (mV) IDS (mA)
(7) References:
[1] Robert L. Boylestad, Louis Nashelsky, Electronic Devices and Circuit Theory, 9th
Edition, 2007-2008
[2] Adel S. Sedra, Kenneth C. Smith, Microelectronic Circuits, Saunders College
Publishing, 3rd ed., ISBN: 0-03-051648-X, 1991.
[3] American International University–Bangladesh (AIUB) Electronic Devices Lab Manual.
[4] David J. Comer, Donald T. Comer, Fundamentals of Electronic Circuit Design, John
Wiley & Sons Canada, Ltd.,ISBN: 0471410160, 2002.
[5] J. Keown, ORCAD PSpice and Circuit Analysis, Prentice Hall Press (2001)
[6] Resistor values: https://www.eleccircuit.com/how-to-basic-use-resistor/, accessed on 20
September 2023.