CONTENTS

Module-3

 Latches
 Flip flops
 Flip flop conversions
 Finite State Machine – design using mealy and Moore state machines
 Sequence detectors and generators design
 Shift Registers
 Counters-synchronous and asynchronous counters
 Ring and Johnson counters

Sequential Logic Circuit Design 2

 CONTENTS

Lecture-8

 Shift Registers

Sequential Logic Circuit Design 3

 BOOKS

Textbooks

1. M.Morris Mano, Michael D Ciletti, Digital Design, 5th edition, Pearson Publishers, 2013.
2. R.P. Jain, “Modern Digital Electronics”, 4th edition, TMH.

References

1. M.Morris Mano, Charles R. Kime, Tom Martin, Logic and Computer Design Fundamentals, 4th edition,
Pearson Publishers.
2. C. H. Roth and L. L. Kinney, Fundamentals of Logic Design, 5th edition, Cengage Publishers.

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Sequential Logic Circuit Design 5
 INTRODUCTION

 A circuit with flip‐flops is considered a sequential circuit even in the absence of combinational
gates. Two such circuits are Registers and Counters.

 A register is a group of flip‐flops, each one of which shares a common clock and is capable of
storing one bit of information.

 An n‐bit register consists of a group of n flip‐flops capable of storing n bits of binary information.

 Besides, a register may have combinational gates that perform certain data‐processing tasks.

 A counter is essentially a register that goes through a predetermined sequence of binary states.
The gates in the counter are connected in such a way as to produce the prescribed sequence of
states.

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 INTRODUCTION

 Registers consist of a finite number of flip-flops. Since each

flip-flop is capable of storing either a "0" or a "1", there is a
finite number of 0-1 combinations that can be stored into a
register. Each of those combinations is known as state or
content of the register.
 An example of 4- bit register is shown in the figure where a
common clock is used for all the 4 flip-flops. Clear_b is used
to reset the register.

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 INTRODUCTION

Register with Load Control

 Load Control = 1
 New data loaded on next positive
clock edge
 Load Control = 0
 Old data reloaded on next positive
clock edge

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Sequential Logic Circuit Design 9
 SHIFT REGISTERS

 A register which is capable of shifting the binary information held in each cell to its neighboring cell,
in a selected direction, is called a shift register.
 Shift registers consist of arrangements of flip-flops and are important in applications involving the
storage and transfer of data in a digital system.

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 SHIFT REGISTERS

 Basic data movement in shift registers are list below

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 SHIFT REGISTERS

 There are four types of shift registers based on data input and output.

1. Serial-in to Serial-out (SISO)

2. Serial-in to Parallel-out (SIPO)
3. Parallel-in to Serial-out (PISO)
4. Parallel-in to Parallel-out (PIPO)

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 SERIAL IN SERIEL OUT (SISO)

 The data is shifted serially “IN” and “OUT” of the register, one bit at a time in either a left or right
direction under clock control.

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 SERIAL IN SERIEL OUT (SISO)

 An example of shift operation is shown below

QA QB QC QD
Clock Pulse No
(FF0) (FF1) (FF2) (FF3)

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

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 SERIAL IN SERIEL OUT (SISO)

 A simple way of looking at the serial shifting

operation, with a focus on the data bits, is
illustrated at right.

 The 4-bit data word “1011” is to be shifted into

a 4-bit shift register.

 One shift per clock pulse.

 Data is shown entering at left and shifting right.

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 SERIAL IN SERIEL OUT (SISO)

 The diagram at right shows the 4-bit sequence

“1010” being loaded into the 4-bit serial-in
serial-out shift register.
 Each bit moves one position to the right each
time the clock’s leading edge occurs.
 Four clock pulses loads the register.

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 SERIAL IN SERIEL OUT (SISO)

 This diagram shows the 4-bit sequence “1010”

as it is unloaded from the 4- bit serial-in serial-
out shift register.
 Each bit moves one position to the right each
time the clock’s leading edge occurs.
 Four clock pulses unloads the register.

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 SERIAL IN PARALLEL OUT (SIPO)

 The register is loaded with serial data, one bit at a time, with the stored data being available at the
output in parallel form.

Parallel data output

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 PARALLEL IN SERIAL OUT (PISO)

 The parallel data is loaded into the register simultaneously and is shifted out of the register serially
one bit at a time under clock control.

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 PARALLEL IN PARALLEL OUT (PIPO)

 The parallel data is loaded simultaneously into the register and transferred together to their
respective outputs by the same clock pulse.

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 BI-DIRECTIONAL SHIFT REGISTER

 A bidirectional shift register is one in which the data can be shifted either left or right.

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 BI-DIRECTIONAL SHIFT REGISTER

Example : Determine the state of the shift register after each clock
pulse for the given RIGHT/LEFT control input waveform. Assume that Q0 = 1, Q0 Q1 Q2 Q3
Q1 = 1, Q2 = 0, and Q3 = 1 and that the serial data-input line is LOW. Initial 1 1 0 1

CP1 0 1 1 0 Right
CP2 0 0 1 1 Right
CP3 0 1 1 0 Left
CP4 1 1 0 0 Left
CP5 1 0 0 0 Left
CP6 0 1 0 0 Right
CP7 0 0 1 0 Right
CP8 0 1 0 0 Left
CP9 1 0 0 0 Left

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Sequential Logic Circuit Design 23