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Handout to Microprocessing and Interface

The document is a course handout for the Microprocessors Programming and Interfacing course (CS/EEE/ECE/INSTR F241) at Birla Institute of Technology and Science, Pilani, for the second semester of 2024-25. It outlines the course description, objectives, textbooks, course plan, evaluation scheme, and policies regarding consultation and make-up exams. The course focuses on processor architecture, assembly programming, memory interfacing, and system design, with a laboratory component included.

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GAURISH TRIVEDI
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8 views2 pages

Handout to Microprocessing and Interface

The document is a course handout for the Microprocessors Programming and Interfacing course (CS/EEE/ECE/INSTR F241) at Birla Institute of Technology and Science, Pilani, for the second semester of 2024-25. It outlines the course description, objectives, textbooks, course plan, evaluation scheme, and policies regarding consultation and make-up exams. The course focuses on processor architecture, assembly programming, memory interfacing, and system design, with a laboratory component included.

Uploaded by

GAURISH TRIVEDI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

Pilani Campus
AUGS/ AGSR Division

SECOND SEMESTER 2024-25


COURSE HANDOUT
Date: 5.01.2025

In addition to part I (General Handout for all courses appended to the Time table) this portion gives further
specific details regarding the course.
Course No : CS/EEE/ECE/INSTR F241
Course Title : Microprocessors Programming and Interfacing
Instructor-in-Charge : Prof. Meetha V Shenoy
Instructor(s) : Prof. Vinay Chamola
Tutorial Instructors : Prof. GSS Chalapathi, Prof. Satyendra Kumar Mourya, Prof. Neeraj
Mishra, Prof. Tejasvi Alladi, Naga Siva Sai Reddy, Balamurugan,
Anubhav Elhence, Jyoti Pandey

1. Course Description: Programmers model of processor, processor architecture; Instruction set, modular
assembly programming using subroutines, macros etc.; Timing diagrams; Concept of interrupts: hardware &
software interrupts, Interrupt handling techniques, Interrupt controllers; Types of Memory & memory
interfacing; Programmable Peripheral devices and I/O Interfacing; DMA controller and its interfacing: Design
of processor based system. This course will have laboratory component.

2. Scope and Objective of the Course:This course is a basic introduction to processor ISA, Assembly
programming, Computer & Embedded Architecture. Intel 80x86 is used as a platform through the course.
8086 - 80486 Programmers model of processor, processor architecture; Instruction set, modular assembly
programming using subroutines, macros etc.; Timing diagrams; Concept of interrupts: hardware & software
interrupts, Interrupt handling techniques, Interrupt controllers. Types of Memory & memory interfacing.
Programmable Peripheral devices and I/O Interfacing, DMA controller and its interfacing. Design of
processor based system.

3. Text Books: Barry B Brey, The Intel Microprocessors.Pearson, Eight Ed. 2009.
4. Reference Books:Douglas V Hall, Microprocessor and Interfacing, TMH, Second Edition.
5. Course Plan:
Module Lecture Lecture Session Reference Learning outcomes
No. Session (Text book)
1 1 Compute Architecture, Memory & I/O Chapter 1 Learn: Introduction to
organization, CISC/RISC processors Microprocessor and
Microcomputers
1 2-3 Programmer's Model Chapter 2 Learn: 8086
Microprocessor & its
architecture
1 4-6 Addressing Modes Chapter 3 Learn:Assembly
Programming
1 7-14 Instruction Set & ALP Chapter 4-6, 8 Learn:Assembly
Programming

1
BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
AUGS/ AGSR Division

2 15-17 Pin Out, Modes of operation, Clocking, Buses Chapter 9 Learn:8086/8088 Hardware
Specifications
2 18-20 Memory Devices, Address Decoding- Memory Chapter -10 Learn:Memory Interface
Interface 8086- 80386, Protected Memory and Protected memory
2 21 Basic I/O interfacing (I/O mapped I/O and Chapter 11.1, Learn:I/O Interfacing
Memory mapped I/O) I/O port address 11.2
decoding, Protected Mode
2 21-24 8255 Chapter 11.3 Learn:Programmable
Peripheral Devices
3 25-26 Types of interrupts, Vector tables, Priority Chapter 12.1, Learn:Interrupts
Schemes 12.2,
3 27-28 8259 Chapter 12.4 Learn:Interrupt Controller
3 29-30 8253/8254 Chapter 11.4 Learn:Programmable Timer
3 31-32 ADC, DAC Chapter 11.6 Learn:Converters
3 33-34 DMA controller 8237 Chapter -13 Learn:DMA controller
3 35-36 Processor-based system design Chapter 15 Learn:System Design
3 37-38 Advanced Processors Chapter 16 Learn-80186-80486

3 39-40 Bus interfaces Chapter 15 Learn- ISA, PCI, Com,


USB,AGP

6. Evaluation Scheme:

Component Duration Weightage (%) Date & Time (Close Book/


300 M Open Book)
Mid-Semester Test 90 Min. 25% (75M) Decided by AUSGD CB
Lab (Regular) 2 hr 4.67% (14M) Best 7 out of 9 OB
Tutorial exams periodic 10.33% (31M) Best 8 out of 10 CB
Lab test 1.5hr 12% (36M) To be announced OB
Design Test 1.5-2 hr 8% (24M) To be announced OB
Comprehensive 3 hr 40% (120M) Decided by AUSGD CB + OB
Examination

7. Chamber Consultation Hour: To be announced in the class


8. Notices: Will be shared by email periodically to students.
9. Make-up Policy: Make up will be allowed for genuine cases. No make up for Lab/ Tut test.
10. Note (if any): A student who scores less than 10% marks maybe awarded NC.

Instructor-in-charge
Course No. CS/EEE/ECE/INSTR F241
2

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