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Chip Test1

The document outlines a series of commands for setting up and executing a test environment for a chip design using ICL and IJTAG patterns. It includes commands for configuring clocks, reading input files, creating pattern sets, and generating various output files in different formats. The process concludes with writing configuration data and exiting the environment.

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shan timo
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11 views1 page

Chip Test1

The document outlines a series of commands for setting up and executing a test environment for a chip design using ICL and IJTAG patterns. It includes commands for configuring clocks, reading input files, creating pattern sets, and generating various output files in different formats. The process concludes with writing configuration data and exiting the environment.

Uploaded by

shan timo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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set_context patterns -ijtag -no_rtl

set_debug_control +ijtag/internalToplevelInterfaces

read_icl {../data/icl/*.icl}

set_current_design chip
report_icl_module -all > elaborated_model.txt

add_clocks ClkA -free_running -period 10ns


add_clocks 1 tck

set_system_mode analysis

source ../data/pdl/raw1.iprocs

open_pattern_set test1 -tester_period 100ns


iCall block2_I1.raw1_I1.run_testa blue
iCall block1_I1.raw1_I1.run_testa
close_pattern_set
report_pattern_set

write_patterns pat1.stil -stil -repl


write_patterns pat1.stil2005 -stil2005 -repl
write_patterns pat1.v -verilog -repl
write_patterns pat1.iproc -pattern_sets test1 -pdl -rep
write_patterns pat1.tasks -pattern_sets test1 -tasks -rep
write_patterns pat1.svf -pattern_sets test1 -svf -rep

open_pattern_set ijtag -tester_period 100ns


create_icl_verification_pattern
close_pattern_set

write_patterns my_ijtag_network.stil -stil -repl


write_patterns my_ijtag_network.svf -svf -repl

create_patterns_specification manufacturing

write_config_data demo.pat_spec -wrappers


/PatternsSpecification(chip,gate,manufacturing) -replace

exit

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