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Second_Exam_logic_Design_2018_1

The document is an exam paper for the Logic Circuits course at Philadelphia University, detailing instructions, allowed materials, and the structure of the exam. It consists of four questions totaling 20 marks, covering topics such as Boolean functions, combinational circuits, and multiplexers. The exam is scheduled for 50 minutes and requires students to submit their solutions with explanatory statements.

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14 views5 pages

Second_Exam_logic_Design_2018_1

The document is an exam paper for the Logic Circuits course at Philadelphia University, detailing instructions, allowed materials, and the structure of the exam. It consists of four questions totaling 20 marks, covering topics such as Boolean functions, combinational circuits, and multiplexers. The exam is scheduled for 50 minutes and requires students to submit their solutions with explanatory statements.

Uploaded by

fakhar_fast
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Philadelphia University Student Name:

Student Number:
Faculty of Engineering Serial Number:

Second Exam, First Semester: 2018/2019


Dept. of Computer Engineering
Course Title: Logic Circuits Date: 23/12/2017
Course No: 630211 Time Allowed: 50 minutes
Lecturer: Dr. Qadri Hamarsheh No. Of Pages: 5

Instructions:
 ALLOWED: pens and drawing tools (no red color).
 NOT ALLOWED: Papers, literatures and any handouts. Otherwise, it will lead to the non-approval of your examination.
 Shut down Telephones, and other communication devices.
Please note:
 This exam paper contains 4 questions totaling 20 marks
 Write your name and your matriculation number on every page of the solution sheets.
 All solutions together with solution methods (explanatory statement) must be inserted in the labelled position on the solution
sheets.
 You can submit your exam after the first hour.

Question 1 Multiple Choice (6 marks)

Identify the choice that best completes the statement or answers the question.
1) The Boolean function F with don't-care conditions are represented in the K-map for four-variables as
shown below, the simplification of the function F in sum-of-products form is:
CD
AB 00 01 11 10
00 0 1 1 0

01 X 1 1 X

11
X X 1 0

10 0 1 0 0

a) ̅𝑫 + 𝑨
𝑨 ̅𝑩 + 𝑩𝑫 + 𝑪 ̅𝑫
b) ̅𝑫 + 𝑨
𝑨 ̅𝑩 + 𝑪 ̅𝑫 + 𝑨𝑩 ̅𝑪̅𝑫
c) ̅𝑫 + 𝑩𝑫 + 𝑪
𝑨 ̅𝑫
d) ̅ ̅ ̅
𝑨𝑩𝑫 + 𝑨𝑩 + 𝑩𝑫 + 𝑨𝑩 ̅𝑪̅𝑫
2) The simplified expression of half adder carry is
a) 𝐜 = 𝐱𝐲 + 𝐱 b) 𝐜 = 𝐱𝐲
c) 𝐜 = 𝐱𝐲 + 𝐲 d) 𝐜=𝐲+𝐱
3) How many select lines will a 16 to 1 multiplexer will have:
a) 4 b) 3
c) 5 d) 6
4) Decoder with enable input can be used as:
a) Encoder b) Multiplexer
c) XOR d) Demultiplexer

1
5) The following circuit is a _________.

a) 2-4 decoder with active low enable and active low outputs
b) 2-4 decoder with active low enable and active high outputs
c) 2-4 decoder with active high enable and active low outputs
d) 2-4 decoder with active high enable and active high outputs
6) The logic realized by the circuit shown in figure is

a) 𝐅 = 𝐁 ⊕ 𝐂 b) 𝐅 = ̅̅̅̅̅̅̅̅̅̅
𝐁 ⊕ 𝐂
c) 𝐅 = 𝐀 ⊕ 𝐂 d) ̅̅̅̅̅̅̅̅̅̅
𝐅 = 𝐀 ⊕ 𝐂

2
Question 2 (5 marks)
a) Draw a diagram of an 8-bit adder/subtractor. (2.5 marks)
Solution

b) Explain the function of an encoder. Implement an encoder using gates. (2.5 marks)
Solution

3
Question 3 (6 marks)
a) A combinational circuit has 3 outputs 𝐅𝟏, 𝐅𝟐 and 𝐅𝟑 (3 marks)
𝐅𝟏 = 𝐱̅ 𝐲̅ 𝐳̅ + 𝐱𝐳
𝐅𝟐 = 𝐱 𝐲̅ 𝐳̅ + 𝐱̅ 𝐲
𝐅𝟑 = 𝐱̅ 𝐲̅ 𝐳 + 𝐱𝐲
Design the circuit with a decoder and external gates.
Solution

b) Design a 4-to-16 line decoder with Enable input using five 2-to-4 line decoders with Enable
inputs. (3 marks)
Solution

4
Question 4 (3 marks)
Implement the following Boolean function with an 8-to-1 multiplexer and a single inverter with variable
B as an input.
𝐟(𝐀, 𝐁, 𝐂, 𝐃) = 𝚺𝐦(𝟐, 𝟒, 𝟔, 𝟗, 𝟏𝟎, 𝟏𝟏, 𝟏𝟓)

Solution

GOOD LUCK
5

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