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Questions: B. Write Notes On: Fpga

A switching circuit performs logic operations on two data inputs depending on the values of two control inputs. The document presents the truth table and asks to (i) derive the truth table for the output and (ii) use a Karnaugh map to find a minimum logic circuit. It also asks how to make a 4-to-1 multiplexer using an 8-to-1 multiplexer and to design a circuit to subtract or add two numbers depending on a control input using components like subtracters and multiplexers. The document contains several other questions related to topics like finite state machines, programmable logic arrays, field programmable gate arrays and clocking schemes in digital circuits.

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126 views2 pages

Questions: B. Write Notes On: Fpga

A switching circuit performs logic operations on two data inputs depending on the values of two control inputs. The document presents the truth table and asks to (i) derive the truth table for the output and (ii) use a Karnaugh map to find a minimum logic circuit. It also asks how to make a 4-to-1 multiplexer using an 8-to-1 multiplexer and to design a circuit to subtract or add two numbers depending on a control input using components like subtracters and multiplexers. The document contains several other questions related to topics like finite state machines, programmable logic arrays, field programmable gate arrays and clocking schemes in digital circuits.

Uploaded by

unnidigi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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QUESTIONS

a.

b.

II.

a.

A switching circuit has two control inputs (C1 and C2), two data inputs
(X1 and X2), and one output (Z). The circuit performs one of the logic
operations AND, OR, EQU(equivalence), or XOR (exclusive OR) on
the two data inputs. The function performed depends on the control
inputs:
C1 C2
Function
Performed by
Circuit
0
0
OR
0
1
XOR
1
0
AND
1
1
EQU
(i) Derive a truth table for Z.
(ii) Use a Karnaugh map to find a minimum AND-OR gate circuit to
realize Z.
Show how to make a 4-to-1 MUX, using an 8-to-1 MUX.
OR
Design a circuit which will either subtract X from Y or Y from X,
depending on the value of A. If A = 1, the output should be X Y, and if
A = 0, the output should be Y X. Use a 4-bit subtracter and two 4-bit
2-to-1 multiplexers .

b.

Write notes on:


FPGA
Three state buffer

a.

Implement the given state graph using D flip-flops and gates. Use a
one-hot assignment and write down the logic equations by inspecting
the state graph.

b.

Discuss a procedure for finding all of the equivalent states in a state


table.

a.

An iterative circuit has an output of 1 from the last cell if and only if the
input pattern 1011 or 1101 has occurred as inputs to any four adjacent

cells in the circuit.


(i) Find a Moore state graph or table with a minimum number of states.
(ii) Make a suitable state assignment, and derive one of the equations
for a typical cell.
(iii) Derive the output equation.
III.

a.

b.
B

IV.

a.

b.

Construct an SM block that has three input variables (D, E, F), four
output variables (P, Q, R, S), and two exit paths. For this block, output
P is always 1, and Q is 1 iff D = 1. If D and F are 1 or if D and E are 0,
R =1 and exit path 2 is taken. If (D = 0 and E = 1) or (D = 1 and F = 0),
S = 1 and exit path 1 is taken.
Explain the derivation of SM chart using a suitable example.

a.
b.

Show how to implement a full subtracter using a PAL.


Realize a Hexadecimal-to-ASCII Code Converter using ROM.

a.

Discuss the following in detail:


PLA folding
FPGAs
Implement a 4-to-1 MUX using a CLB. Specify the function realized by
each function generator.

b.
V.

Consider the following logic function.


F(A, B, C, D) = m(0, 4, 5, 10, 11, 13, 14, 15)
(i) Find two different minimum circuits which implement F using AND
and OR gates. Identify two hazards in each circuit.
(ii) Find an AND-OR circuit for F which has no hazards.
(iii) Find an OR-AND circuit for F which has no hazards.
Discuss the hazards in combinational logic

a.
b.

Discuss the classification of digital systems based on clocking schemes.


Discuss on the impact of positive and negative skew on the stability of
digital circuits.

a.

Discuss the impact of skew and jitter on performance of integrated


circuits.
What are the sources of skew and jitter?

b.

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