USN 1 R V E C

Date: 22/02/2024 Test – 2 Max. Marks:50

Semester: V UG 𝟏
Duration: 1 Hrs
𝟐
Course: Embedded System Design (Common to ECE and E&I) Code:21EC54
No Questions M BT CO

1. The AT24C16A provides 16K bits(2048 bytes) of electrically erasable and programmable read- 10 4 4
only memory (EEPROM) with serial (I2C) interface. The 2048 bytes are organized into 8 pages
with 256 bytes each.
Addressing scheme is as follows.
• Each page requires 8-bits to access the 256 locations
• Additional 3 bits are required to address 8 pages.
The device address for I2C interface is 1010. The remaining bits of the first byte indicate 3-page
address bits as shown below:

Where, P2, P1, P0 indicate page address.

The write & read operations are shown diagram below.
Write Operation:

Read Operation:

Pin Diagram:AT24C16

NC SCL: I2C Clock line

NC NC SDA: I2C data line
NC NC: No Connection

Write interfacing diagram to connect AT24C16 to STM32F407VG MCU. Assume HAL is

generated using STM32CubeMX with following functions:
//Checks if target device is ready for communication
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t
DevAddress, uint32_t Trials, uint32_t Timeout)
 // Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t
DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
// Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t
DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Parameters:
DevAddress Target device address: The device 7 bits address value
in datasheet must be shifted to the left before calling the interface
Trials Number of trials
Timeout Timeout duration
pData is pointer to data to write interface in Transmit function where as it is a pointer to buffer to
store data after read in Receive function.
Write application code to run on STM32F407VG to perform memory read and write operations.
Add statements to store a string “Embedded System Design Electronics & Communication
Engineering” in page 4 at memory address starting at 0x20. In addition, add statements to perform
read operation. Assume tool chain as Keil uVision.
2. Modify the application code developed in question 1 to recover from transient errors which might 10 4 3
occur during execution. The read and write operations are bounded by 6 ms/byte. Invoke IDWT
available in STM32F407VG. HAL generated after configuring in STM32CubeMX are as follows:
// IWDT Handler
IWDG_HandleTypeDef hiwdg;
//Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start
watchdog.
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
//IWDG Initialization Function
void MX_IWDG_Init(void)
//Refresh the IWDG
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
3. a. A computer system uses 16-bit memory addresses. It has a 2K-byte cache organized in a direct- 05 2 2
mapped manner with 64 bytes per cache block. Assume that the size of each memory word is 1
byte. Calculate the number of bits in each of the Tag, Block, and Word fields of the memory
address.
b. What are the various messages in CAN protocol? Write the format of data frame. 05
4. a. Differentiate between I2C, I3C and SPI w.r.t electrical characteristics, signalling, addressing, 06 1 1
arbitration, number lines, speed, and advantages.
b. Write the functionality of different layers of SATA. 04
5. The table below shows miss rates of unified cache and split cache for different sizes: 10 3 2
Size Split Cache Unified Assume a total of 75% memory
Data cache Instruction cache Cache accesses are instructions and
4 KB 15.94 % 1.78% 7.24% remaining 25% are data accesses.
8 KB 10.19% 1.10% 4.57% The hit time of split cache is 1 cycle
16 KB 6.47% 0.64% 2.87% and for unified cache because of its
32 KB 4.82% 0.39% 1.99% common port the hit time is 2 cycles.
The miss penalty in both the caches is 50 cycles. Draw a conclusion based on average memory
access time and miss rates.

Particulars CO1 CO2 CO3 CO4 L1 L2 L3 L4 L5 L6

Marks
Distribution Test Max 10 20 10 10 10 10 15 20 - -
Marks
Date: 22/02/2024 Test - 3 Max. Marks:
Semester: V UG 𝟏
Duration: 1 𝟐 Hrs
Course: Embedded System Design Code:21EC54
SCHEME & SOLUTIONS
S No Solutions with Scheme Marks
1. 10
Application code to read and write operation
2. 10
Application code with using HAL of IDWT
3. a. 05

05
b. The message transfer is controlled by four different types of frames.
Data Frame: Carries data from transmitter to receiver.
Remote Frame: Transmitted by a node to request for a transfer frame with same identifier.
Error Frame: Transmitted by a node, on detecting a bus error.
Overload Frame: Used to provide a delay between two successive data frames or remote
frames. (02 Marks)
Data frame format: (03 Marks)
4. a. I2C: Typically operates at 3.3V or 5V, but some devices support lower voltages. Uses 05
open-drain or open-collector outputs for bidirectional communication.
I3C: Supports a wide range of voltage levels, including low-power modes. Uses push-
pull or open-drain signaling, depending on the mode of operation. 05
SPI: Operates at various voltage levels, commonly 3.3V or 5V. Uses push-pull outputs
for communication
(Similarly other differences)
b. Physical Layer:
 Physical transmission uses differential signaling. The SATA PHY contains a
transmit pair and receive pair.
 When the SATA-link is not in use, the transmitter allows the transmit pins to float to
their common-mode voltage level.
 When the SATA-link is either active or in the link-initialization phase, the transmitter
drives the transmit pins at the specified differential voltage.
 The link layer is responsible for managing the communication between the
SATA host controller and SATA storage devices.
Link Layer:
The operations are:
• Framing: SATA uses a frame-based protocol where data is transmitted in fixed-size
frames. Each frame consists of a header, payload (data), and a CRC for error
detection.
• Flow Control: Flow control mechanisms ensure that data is transmitted at an
appropriate rate to prevent buffer overflow or underflow.
• Addressing: SATA devices are identified using unique addresses. The link layer
handles addressing to ensure that data is correctly routed to the intended device.
• Hot-Plugging Support: The link layer manages the process of detecting and
initializing newly connected devices.
Transport Layer
 The transport layer sits above the link layer and provides additional features and
functionalities to ensure efficient and reliable data transmission.
The functions are:
 Command Queuing: SATA supports command queuing, allowing multiple
commands(READ,WRITE,IDENTIFY DEVICE,SET FEATURES, SECURITY
commands, etc..) to be sent to the storage device and executed in the order specified
by the host.
 Power Management: SATA supports power management features at the transport
layer, allowing devices to enter low-power states when not in use to conserve energy.
5. Size Split Cache Unified Cache 10
Data cache Instruction cache
4 KB 15.94 % 1.78% 7.24%
8 KB 10.19% 1.10% 4.57%
16 KB 6.47% 0.64% 2.87%
32 KB 4.82% 0.39% 1.99%

4 KB:
Split cache:
AMAT= 0.75{(1-0.0178)+ 0.0178 x 50}+0.25{(1-0.1594)+0.1594x50)
 =3.60 cycles
Unified cache:
AMAT= 0.75{(1-0.0724)+ 0.0724x 50}+0.25{2(1-0.0724)+0.0724x50)}
=4.7 cycles
Similar calculations for other cache sizes.
Conclusion: The unified cache has a longer AMAT, even though its miss rate is lower,
due to conflicts for instruction and data hazards.
Date: 22/02/2024 Test - 2 Max. Marks:50
Semester: V UG 𝟏
Duration: 1 𝟐 Hrs
Course: Embedded System Design Code:21EC54

SCRUTINY & EVALUATION OF CIE QUESTION PAPER

Declaration by the Course handling faculties:

As a teaching faculty of the course Embedded System Design with code: 21EC54,
We hereby confirm that the question paper with Scheme and Solutions is thoroughly reviewed and we
ensure that it adheres to the following criteria:
Sl. No Criteria Yes/No
1 The question paper adequately covers the prescribed syllabus contents.
2 The question paper is in line with the recommended pattern, taking into consideration the
structure and format suitable for the Continuous Internal Evaluation.
3 The question paper is designed to align with the Revised Bloom's Taxonomy,
encompassing various levels of cognitive skills such as remembering, understanding,
applying, analysing, evaluating, and creating.
4 The question paper is aligned with the defined course outcomes, ensuring that it effectively
assesses the knowledge and skills acquired during the course.
5 Course handling faculty (as applicable) who are responsible for preparing the question
paper, Scheme and Solutions have unanimously agreed to utilize this Question paper for
conducting the Continuous Internal Evaluation.
6 The Question paper, Scheme and complete Solutions have been submitted to the Test
coordinators within the designated time-frame to ensure the smooth conduction of
Continuous Internal Evaluations

Course handling Faculties:

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No Max Awarded
1 Timely submission of the question paper along with the scheme & solution 10
2 Heterogeneous nature of QP with respect to BTs and Cos 10
3 Format with proper entry of all particulars including test, course name, code, 10
date, max marks, BT CO table, efficient use of paper (proper spacing, figures)
4 No handwritten data or diagrams, and uniform fonts throughout 10
5 Scheme & complete Solutions in the format 10
Total points 50
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