Lecture No.

Course Name Electronic (3)

CMOS VLSI Design

Lecture 2: CMOS Fabrication and
Layout
Instructor Dr. Samia Heshmat
Credits: David Harris
Harvey Mudd College

(Material taken/adapted from Harris’ lecture notes)

email samia.heshmat@aswu.edu.eg CMOS VLSI Design 07 October 2024

 CMOS Fabrication
❑ CMOS transistors are fabricated on silicon wafer
❑ Lithography process similar to printing press
❑ On each step, different materials are deposited or
etched
❑ Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

CMOS VLSI Design Slide 2

 Inverter Cross-section
❑ Typically use p-type substrate for nMOS transistors
❑ Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

CMOS VLSI Design Slide 3

Well and Substrate Taps
❑ Substrate is tied to GND and n-well to VDD
❑ Metal to lightly-doped semiconductor forms poor
connection
❑ Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

CMOS VLSI Design Slide 4

 Inverter Mask Set
❑ Transistors and wires are defined by masks
❑ Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

CMOS VLSI Design Slide 5

 Detailed Mask Views
❑ Six masks n well

– n-well
– Polysilicon
Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

CMOS VLSI Design Slide 6

 Fabrication Steps
❑ Start with blank wafer
❑ Build inverter from the bottom up
❑ First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

CMOS VLSI Design Slide 7

 Oxidation
❑ Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

CMOS VLSI Design Slide 8

 Photoresist
❑ Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

CMOS VLSI Design Slide 9

 Lithography
❑ Expose photoresist through n-well mask
❑ Strip off exposed photoresist

Photoresist
SiO2

p substrate

CMOS VLSI Design Slide 10

 Etch
❑ Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
❑ Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

CMOS VLSI Design Slide 11

 Strip Photoresist
❑ Strip off remaining photoresist
– Use mixture of acids called piranha etch
❑ Necessary so resist doesn’t melt in next step

SiO2

p substrate

CMOS VLSI Design Slide 12

 n-well
❑ n-well is formed with diffusion or ion implantation
❑ Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
❑ Ion Implantation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well

CMOS VLSI Design Slide 13

 Strip Oxide
❑ Strip off the remaining oxide using HF
❑ Back to bare wafer with n-well
❑ Subsequent steps involve similar series of steps

n well
p substrate

CMOS VLSI Design Slide 14

 Polysilicon
❑ Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
❑ Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

CMOS VLSI Design Slide 15

 Polysilicon Patterning
❑ Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

CMOS VLSI Design Slide 16

 N-diffusion
❑ Use oxide and masking to expose where n+ dopants
should be diffused or implanted
❑ N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

CMOS VLSI Design Slide 17

 N-diffusion (cont.)
❑ Pattern oxide and form n+ regions

n+ Diffusion

n well
p substrate

CMOS VLSI Design Slide 18

 N-diffusion (cont.)
❑ Historically dopants were diffused
❑ Usually ion implantation today
❑ But regions are still called diffusion

n+ n+ n+

n well
p substrate

CMOS VLSI Design Slide 19

 N-diffusion (cont.)
❑ Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

CMOS VLSI Design Slide 20

 P-Diffusion
❑ Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

CMOS VLSI Design Slide 21

 Contacts
❑ Now we need to wire together the devices
❑ Cover chip with thick field oxide
❑ Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

CMOS VLSI Design Slide 22

 Metalization
❑ Sputter on aluminum over whole wafer
❑ Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

CMOS VLSI Design Slide 23

 Gate Layout
❑ Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
❑ Standard cell design methodology
– VDD and GND should be at standard height
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

CMOS VLSI Design Slide 24

 Layout
❑ Chips are specified with set of masks
❑ Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
❑ Feature size f = distance between source and drain
– Set by minimum width of polysilicon
❑ Feature size improves 30% every 3 years or so
❑ Normalize for feature size when describing design
rules
❑ Express rules in terms of  = f/2
– E.g.  = 0.3 m in 0.6 m process

CMOS VLSI Design Slide 25

 Stick Diagrams
❑ Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers

CMOS VLSI Design Slide 26

 Wiring Tracks
❑ A wiring track is the space required for a wire
– 4  width, 4  spacing from neighbor = 8  pitch
❑ Transistors also consume one wiring track

CMOS VLSI Design Slide 27

 Well spacing
❑ Wells must surround transistors by 6 
– Implies 12  between opposite transistor flavors

CMOS VLSI Design Slide 28

 Simplified Design Rules
❑ Conservative rules to get you started

CMOS VLSI Design Slide 29

 Inverter Layout
❑ Transistor dimensions specified as Width / Length
– Minimum size is 4 / 2 sometimes called 1 unit
– In f = 0.6 m process, this is 1.2 m wide, 0.6 m
long

CMOS VLSI Design Slide 30

 Example: Inverter

VDD

A Y

GND

CMOS VLSI Design Slide 31

 Stick Diagrams

– What is stick diagram?

– Why stick diagram?
– Conventions and rules related to stick diagram.
– Drawing stick diagrams.

CMOS VLSI Design Slide 32

Stick Diagrams

N+ N+

CMOS VLSI Design Slide 33

 Stick Diagrams
VDD
VDD
X

X x
x x
x Stick X
Diagram
X

Gnd Gnd

CMOS VLSI Design Slide 34

 Stick Diagrams

VDD
VDD
X

X x
x x
x X

Gnd Gnd
CMOS VLSI Design Slide 35
 Stick Diagrams
❑ VLSI design aims to translate circuit concepts onto
silicon.
❑ stick diagrams are a means of capturing topography
and layer information using simple diagrams.
❑ Stick diagrams convey layer information through
colour codes (or monochrome encoding).
❑ Acts as an interface between symbolic circuit and
the actual layout.

CMOS VLSI Design Slide 36

 Stick Diagrams

▪ Does show all components/vias.

▪ It shows relative placement of components.
▪ Goes one step closer to the layout
▪ Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

CMOS VLSI Design Slide 37

 Stick Diagrams

▪ Does not show

• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..

CMOS VLSI Design Slide 38

 Stick Diagrams – Notations

Metal 1

poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.

Similarly for contacts, via, tub etc..

CMOS VLSI Design Slide 39

Stick Diagrams – Some rules

Rule 1.
When two or more ‘sticks’ of the same type cross or
touch each other that represents electrical contact.

CMOS VLSI Design Slide 40

 Stick Diagrams – Some rules
Rule 2.
When two or more ‘sticks’ of different type cross or touch
each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).

CMOS VLSI Design Slide 41

Stick Diagrams – Some rules
Rule 3.
When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

CMOS VLSI Design Slide 42

Stick Diagrams – Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid touching
of p-diff with n-diff. All pMOS must lie on one side of the
line and all nMOS will have to be on the other side.

CMOS VLSI Design Slide 43

How to draw Stick Diagrams

CMOS VLSI Design Slide 44

Stick Diagrams

CMOS VLSI Design Slide 45

 Stick Diagrams
Power

poly.
P- diff
n- diff
metal Out
A

Ground

CMOS VLSI Design Slide 46

Stick Diagrams

CMOS VLSI Design Slide 47