Lecture No.

Course Name Electronic (3)

CMOS VLSI Design

Lecture 3-1: CMOS Fabrication
and Layout
Instructor Dr. Samia Heshmat
Credits: David Harris
Harvey Mudd College

(Material taken/adapted from Harris’ lecture notes)

email samia.heshmat@aswu.edu.eg CMOS VLSI Design 13 October 2024

 Stick Diagrams

– What is stick diagram?

– Why stick diagram?
– Conventions and rules related to stick diagram.
– Drawing stick diagrams.

CMOS VLSI Design Slide 2

Stick Diagrams

N+ N+

CMOS VLSI Design Slide 3

 Stick Diagrams
VDD
VDD
X

X x
x x
x Stick X
Diagram
X

Gnd Gnd

CMOS VLSI Design Slide 4

 Stick Diagrams

VDD
VDD
X

X x
x x
x X

Gnd Gnd
CMOS VLSI Design Slide 5
 Stick Diagrams
❑ VLSI design aims to translate circuit concepts onto
silicon.
❑ stick diagrams are a means of capturing topography
and layer information using simple diagrams.
❑ Stick diagrams convey layer information through
colour codes (or monochrome encoding).
❑ Acts as an interface between symbolic circuit and
the actual layout.

CMOS VLSI Design Slide 6

 Stick Diagrams

▪ Does show all components/vias.

▪ It shows relative placement of components.
▪ Goes one step closer to the layout
▪ Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

CMOS VLSI Design Slide 7

 Stick Diagrams

▪ Does not show

• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..

CMOS VLSI Design Slide 8

 Stick Diagrams – Notations

Metal 1

poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.

Similarly for contacts, via, tub etc..

CMOS VLSI Design Slide 9

Stick Diagrams – Some rules

Rule 1.
When two or more ‘sticks’ of the same type cross or
touch each other that represents electrical contact.

CMOS VLSI Design Slide 10

 Stick Diagrams – Some rules
Rule 2.
When two or more ‘sticks’ of different type cross or touch
each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).

CMOS VLSI Design Slide 11

Stick Diagrams – Some rules
Rule 3.
When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

CMOS VLSI Design Slide 12

Stick Diagrams – Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid touching
of p-diff with n-diff. All pMOS must lie on one side of the
line and all nMOS will have to be on the other side.

CMOS VLSI Design Slide 13

How to draw Stick Diagrams

CMOS VLSI Design Slide 14

Stick Diagrams

CMOS VLSI Design Slide 15

 Stick Diagrams
Power

poly.
P- diff
n- diff
metal Out
A

Ground

CMOS VLSI Design Slide 16

Stick Diagrams

CMOS VLSI Design Slide 17

 Area Estimation
❑ Estimate area by counting wiring tracks
– Multiply by 8 to express in 

CMOS VLSI Design Slide 18

 Example: NAND3
❑ Horizontal N-diffusion and p-diffusion strips
❑ Vertical polysilicon gates
❑ Metal1 VDD rail at top
❑ Metal1 GND rail at bottom
❑ 32  by 40 

Y
A
B
C

CMOS VLSI Design Slide 19

 Example: O3AI
❑ Sketch a stick diagram for O3AI and estimate area
– Y = ( A+ B + C) D

CMOS VLSI Design Slide 20

 Example: O3AI
❑ Sketch a stick diagram for O3AI and estimate area
– Y = ( A+ B + C) D
A
OR-AND-INVERT-3-1 (OAI31) gate.
B
C D
Y
D
A B C

CMOS VLSI Design Slide 21

 Example: O3AI
❑ Sketch a stick diagram for O3AI and estimate area
– Y = ( A+ B + C) D

CMOS VLSI Design Slide 22

 Example: O3AI
❑ Sketch a stick diagram for O3AI and estimate area
– Y = ( A+ B + C) D

CMOS VLSI Design Slide 23

Assessment:
a) Draw the transistor circuit diagram for the following
combinational logic function
A B C Z
A A`B B`C C` 0 0 0 S0
0 0 1 S1
ABC S0
S1 0 1 0 S2
S. 2 8 to 1 Z 0 1 1 S3
.
. selector 1 0 0 S4
.
S7 1 0 1 S5
1 1 0 S6
1 1 1 S7

b) Construct a color-code stick diagram, representing the

design of integrated cmos
CMOS structure
VLSI Design
 Design Partitioning
❑ Know that MOS transistors behave as voltage-
controlled switches.
❑ Know how to build logic gates out of transistors.
❑ Know how transistors are fabricated and how to
draw a layout that specifies how transistors should
be placed and connected together.
❑ Now, you know enough to start building your own
simple chips.

CMOS VLSI Design Slide 25

 Design Partitioning
❑ The greatest challenge in modern VLSI design is not
in designing the individual transistors but rather in
managing system complexity. Modern System-On-
Chip (SOC)

❑ To design combine memories, processors, high-

speed I/O interfaces, and dedicated application-
specific logic on a single chip; use hundreds of
millions or billions of transistors and cost tens of
millions of dollars (or more) to design.

CMOS VLSI Design Slide 26

 Design Partitioning
Digital VLSI design is often partitioned into five levels of
abstractions: architecture design, microarchitecture design,
logic design, circuit design, and physical design
❑ Architecture: describes the functions of the system.
User’s perspective, what does it do?
– Instruction set, registers set, memory model.
– MIPS, x86, Alpha, PIC, ARM, …

❑ Microarchitecture: how the architecture is

partitioned into registers and functional units.
– Single cycle, multicycle, pipelined, superscalar?

CMOS VLSI Design 27

 Design Partitioning
Digital VLSI design is often partitioned into five levels of
abstractions: architecture design, microarchitecture design,
logic design, circuit design, and physical design
❑ Logic: how are functional blocks constructed
– Ripple carry, carry lookahead, carry select adders

❑ Circuit: describes how transistors are used to

implement the logic
– Complementary CMOS, pass transistors, domino

❑ Physical: describes the layout of the chip.

– Datapaths, memories, random logic
CMOS VLSI Design 28
 Structured Design
The practice of structured design used in large software
projects to manage the complexity.
❑ Hierarchy: tool for managing complex designs.
− Large system → partitioned into multiple cores.
− Each core → built from various units.
− Each unit → composed many functional blocks.
− These blocks → built from cells
− Cells are constructed from transistors.
The system design hierarchy can be viewed as a tree
structure with the overall chip as the root and the
primitive cells as leaf.
CMOS VLSI Design 29
 Structured Design
The practice of structured design used in large software
projects to manage the complexity.
❑ Regularity aids the management of design complexity
by designing the minimum number of different blocks
– Reuse modules wherever possible
– Ex: Standard cell library
❑ Modularity: requires that the blocks have well-defined
interfaces to avoid unanticipated interactions
– Allows modules to be treated as black boxes
❑ Locality involves keeping information where it is used
– Physical and temporal
CMOS VLSI Design 30
 Behavioral, Structural, and
Physical Domains
 An alternative way of viewing design partitioning is
shown with the Y-chart
 The radial lines on
the Y-chart represent
three distinct design
domains: behavioral,
structural, and
physical.

CMOS VLSI Design 31

 Behavioral, Structural, and
Physical Domains
 The way of viewing
design partitioning is
the Y-chart
 These domains are
described the design of
any artifact and thus
form a general
taxonomy for
describing the design
process
CMOS VLSI Design 32
 MIPS Architecture
❑ The remainder of the chapter is a case study in the
design of a simple microprocessor to illustrate the
various aspects of VLSI design applied to a
nontrivial system.
❑ It is begun by describing the architecture and
microarchitecture of the processor, then logic design
and discuss hardware description languages.
❑ The processor is built with static CMOS circuits,
transistor-level.

CMOS VLSI Design Slide 33

 MIPS Architecture
❑ Continues exploring the physical design of the
processor, design verification is critically important
and happens at each level of the hierarchy for each
element of the design.
❑ Finally, the layout is converted into masks so the
chip can be manufactured, packaged, and tested.

CMOS VLSI Design Slide 34

 Design Verification
❑ Fabrication is slow & expensive
– MOSIS 0.6m: $1000, 3 months Specification

– 65 nm: $3M, 1 month = Function

❑ Debugging chips is very hard Architecture

Design

– Limited visibility into operation = Function

❑ Prove design is right before building!

Logic
Design

– Logic simulation = Function

Circuit

– Ckt. simulation / formal verification Design

Function
= Timing
– Layout vs. schematic comparison Physical
Power

– Design & electrical rule checks

Design

❑ Verification is > 50% of effort on most chips!

CMOS VLSI Design 35

Fabrication & Packaging
❑ Tapeout final layout
❑ Fabrication
– 6, 8, 12” wafers
– Optimized for throughput,
not latency (10 weeks!)
– Cut into individual dice
❑ Packaging
– Bond gold wires from die I/O pads to package

CMOS VLSI Design 36

 Testing
❑ Test that chip operates
– Design errors
– Manufacturing errors
❑ A single dust particle or wafer defect kills a die
– Yields from 90% to < 10%
– Depends on die size, maturity of process
– Test each part before shipping to customer

CMOS VLSI Design 37

 MIPS R3000 Processor
❑ 32-bit 2nd generation commercial processor (1988)
❑ Led by John Hennessy (Stanford, MIPS Founder)
❑ 32-64 KB Caches
❑ 1.2 m process
❑ 111K Transistors
❑ Up to 12-40 MHz
❑ 66 mm2 die
❑ 145 I/O Pins
❑ VDD = 5 V
❑ 4 Watts
❑ SGI Workstations http://gecko54000.free.fr/?documentations=1988_MIPS_R3000

CMOS VLSI Design 38