Lecture 1:

Introduction
1. Introduction
2. MOS Transistors
3. CMOS Logic Gates
4. IC Design Flow

1: Introduction
 1. Introduction
 Integrated circuits (IC): many transistors on one chip.
 Very Large Scale Integration (VLSI): bucket loads!
 Complementary Metal Oxide Semiconductor (CMOS)
– Fast, cheap, low power transistors
 Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
 Rest of the course: How to build a good CMOS chip

1: Introduction CMOS VLSI Design 4th Ed.

 Growth Rate
 53% compound annual growth rate over 50 years
– No other technology has grown so fast so long
 Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society

[Moore65]
Electronics Magazine

1: Introduction CMOS VLSI Design 4th Ed.

 Transistor Types
 Bipolar junction transistors (BJT)
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
(MOSFET)
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration
1: Introduction CMOS VLSI Design 4th Ed.
 Interesting Facts from 2013
 1.4 Billion mobile phones & tablets
– About 100 million transistors per phone processor
– About 2 GB per phone/tablet of memory
 180 million PCs, laptops, desktops, and servers
– About 1 Billion transistors per processor
– Average memory of 8 GB each
 Total logic transistors ~ 3.2E17
 Total memory transistors ~ 4.2E18
– And this doesn’t count flash in cameras, SSDs, …
 About 600 million transistors for each earthling/yr
 140 Billion transistors/second
 90% of all transistors ever made were made in the last 4
years!
 50% of all transistors ever made were made in the last 15
months! have been manufactured by Homo Sapiens!
http://www.quora.com/How-many-transistors-are-made-per-year
Introduction CMOS VLSI Design Slide 3
The iPhone: A VLSI Enabled System

Introduction CMOS VLSI Design Slide 4

 iPhone 3G Parts Breakdown

Electronic Components
About one dozen major ICs
Introduction CMOS VLSI Design Slide 5
 iPhone 4 Parts Breakdown

Electronic Components

Introduction CMOS VLSI Design Slide 6

 iPhone 6 Parts Breakdown

Electronic
Components

https://9to5mac.files.wordpress.com/2014/09/msuctmh4vhqmloo2.jpeg

Introduction CMOS VLSI Design Slide 7

 iPhone 6 Chip Set

http://www.nfcworld.com/wp-content/uploads/2014/09/iphone-6-circuit-board.jpg
http://4.bp.blogspot.com/-
QyO7GPfsy6w/VSMHQQHu_uI/AAAAAAAAAjI/XRZBmn2TnvI/s1600/Back.p ng

A8 processor chip
• Dual core 64b ARM
• 2B transistors
• Graphics processor
• 1 GB DRAM chip stacked on top

http://www.ifixit.com/Misc/iphone_processor_crossection.jpg
https://www.chipworks.com/about-
chipworks/overview/blog/inside-iphone-6-and-
iphone-6-plus-part-2

Introduction CMOS VLSI Design Slide 8

 iPhone Functions
iPhone VLSI Design Class
 Digital Functions Yes
– Processor
– Memory
– LCD Driver
– Analog and Radio Interfaces (glue logic)
 Radio Functions NO
– 2G Cell Phone (GSM) Transceiver
– 3G Data Interconnect Transceiver
– GPS Receiver
– Bluetooth Transceiver
– WiFi Transceiver
– Near Field Wireless
 Analog Functions Very Little
– Audio input and output No Some No
– A-to-D and D-to-A converters No No No
– Video Sensor (2 in iPhone 4) Some No No
– Screen Touch Sensor
– Proximity Sensor
– 3D Accelerometer (6D in iPhone 4
– Digital I/O
– USB Interface
– Firewire Interface
Introduction CMOS VLSI Design Slide 9
 iPhone Technology Timeline
iPhone First Use
Digital Functions
– Processor 1971
– Memory 1971
– LCD Driver 1988
– Analog and Radio Interfaces (glue logic) 1972
 Radio Functions
– 2G Cell Phone (GSM-TDMA) Transceiver 1992
– 3G Data Interconnect Transceiver 2003
– GPS Receiver 1993
– Bluetooth Transceiver 1994
– WiFi (IEEE 802.11) Transceiver 2000
 Analog Functions
– Audio input and output 1952
– A-to-D and D-to-A converters ~1970
– Video Sensor (2 in iPhone 4) 1974
– Screen Touch Sensor 2007
– Proximity Sensor
– 3D Accelerometer (6D in iPhone 4 1990
– Digital I/O
– USB Interface 1995
– Firewire Interface
1995
Introduction CMOS VLSI Design Slide 10
 Transistor and IC History

Introduction CMOS VLSI Design Slide 11

 A Short History of Semiconductors
 What would someone in 2000 think of the iPhone?
 1990?
 1980?
 1970?
 1960?
 1950?

1950 Record Album 2011 iPod Nano

16 songs 5500 songs
30 cm X 30 cm X 3 cm 3.75 cm X 4.09 cm X 0.875 cm
170 cm3 / song 2.4E-3 cm3 / song

70,000 X Improvement

Introduction CMOS VLSI Design Slide 12

 The Beginnings:
The Bipolar Transistor Era 1947-1963

 Point Contact Transistor (Brattain,

Bardeen, Shockley, Bell Labs, 1947)
 Western Electric Allentown, PA
plant begins transistor
manufacturing (1952)
 Germanium Bipolar Transistor
(Saby, GE, 1952)
 Silicon Bipolar Transistor (Moll, Bell
Labs, 1955

Introduction CMOS VLSI Design Slide 13

 Discrete Transistors
Circa 1950s
1959

• 6 transistors
• ~ $200 (in 2010 dollars)
• AM stations only

Introduction CMOS VLSI Design Slide 14

 The Small-Medium Scale Integrated
Circuit Era 1963-1974
 The First Integrated Circuit
– Kilby (TI, 1958) mesa transistors and wirebonds Kilby: 1958
– Noyce (Fairchild, 1959) diffused transistors and
deposited metal
 Silicon Field Effect Transistor comes of age
– MOS Transistor
– Self-Aligned Poly-Gate MOS Transistor
 Key Circuits
– Single-chip Operational Amplifiers
– The first microprocessors
 CAD Fairchild: 1961
– Primitive circuit & logic design
– SPICE developed at UC Berkeley
 The IC business characteristics
– Mfg equipment made by Semiconductor Companies
– Each transistor is unique. Every chip has a device
engineer

Introduction CMOS VLSI Design Slide 15

 Early Chips: The
Thousand Transistor
Limit

Rubylith, the Step-and-Repeat Mask

Machine and Contact Printing

CMOS VLSI Design

 MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle

Intel 1101 Intel 4004 Intel 1103

256-bit SRAM 4-bit µProc 1K bit DRAM

Introduction CMOS VLSI Design Slide 17

 Intel 4004

• Transistors 2300
• Process 10 µ
• Area 83 mm2
• Clock 100 kHz
Introduction CMOS VLSI Design Slide 18
 4004 Schematic

http://www.4004.com/assets/4004-lajos-schematics.gif
Introduction CMOS VLSI Design Slide 19
 The 8-bit RCA 1802 circa 1975:
The First CMOS Microprocessor
(which went to Jupiter!)

Introduction CMOS VLSI Design Slide 20

 CMOS Chips In Cross Section

http://www.engr.sjsu.edu/WofMatE/images/intercon.gif

http://www.hitequest.com/Kiss/photolithography.gif

Introduction CMOS VLSI Design Slide 21

 Rubylith, the Step-and-Repeat Mask
Machine and Contact Printing

http://s7.computerhistory.org/is/image/CHM/500003094-03-01?$re-inline-artifact$

Introduction CMOS VLSI Design Slide 22

The Large Scale Integrated Circuit
Era 1975-1985

 The Scanning Projection Photolithography - the PEP Tool

 EBES - The Electron Beam Exposure System for Mask
Making
 CAD
– SPICE used for circuit design
– Logic Analysis tools developed

 Technology driven by the DRAM

 The big Microprocessor and the PC

Introduction CMOS VLSI Design Slide 23

 The Beginnings of the PC Era

Intel 8088 Motorola 68000

IBM PC Apple Macintosh

Introduction CMOS VLSI Design Slide 24

 The VLSI Era
1986-?
 The Stepper
 32-64 Bit Microprocessors
 Signal Processing
– Switched Capacitor
• e.g. ISDN U-Interface
– Sigma-Delta A/D Converter
– Digital Signal Processing
 CAD
– Logic Analyzers
• Verilog
• VHDL
– Logic Synthesis
– Static Timing Analyzers
– Mixed Signal Analyzers
– Standard Cell & Routers

Introduction CMOS VLSI Design Slide 25

 Intel 80386
32 bit Microprocessor

Transistors 275 K
Process 1µ
Clock 16-33 MHz

Introduction CMOS VLSI Design Slide 26

Transition to Automation and Regular Structures

Intel 4004 (‘71)

Intel 8080 Intel 8085

Intel 8286 Intel 8486

Courtesy Intel
Introduction CMOS VLSI Design Slide 27
2008: Intel Nehalem Quad
731 M Transistors Core i7 32 nm CMOS

Introduction CMOS VLSI Design Slide 28

 2008: Intel Nehalem Quad: 731 M Transistors

32 nm Technology Node

Transistor CANNOT be seen

under highest power
optical microscope

Why?
Wavelengths of Visible Light
370-750 nm
Dimensions are < 370 nm
Introduction CMOS VLSI Slide 29
Design
 Intel 7500 Xeon

http://download.intel.com/pressroom/kits/xeon/7500series/images/NHM-EX-Die-
Shot-2.jpg
Introduction CMOS VLSI Design Slide 30
 Memory Chips

1k bit DRAM

256M bit DRAM 4Gb bit DRAM

http://sammyhub.com/wp-content/uploads/2012/02/ddr3.jpg

http://www.eeherald.com/images/nand_cell_array.jpg

32Gb bit Flash

http://news.cnet.com/i/bto/20080529/intel-32gb-nand-flash-small.jpg

Introduction CMOS VLSI Design Slide 31

 Active Memory

Terasys 1993 EXECUBE 1993 Micron Yukon 2003

SRAM + 64 1b ALUs 8-cores on 4 Mb DRAM
http://www.nitrd.gov/pubs/bluebooks/1994/nsa.1.3.gif

Introduction CMOS VLSI Design Slide 32

 The Era of Tiled Microprocessors

IBM Cell Tilera

NVIDIA Fermi Intel Phi

Introduction CMOS VLSI Design Slide 33
 The Era of Accelerators
First Generation Google Tensor Processing Unit Chip:
• H/W Dense Matrix-Vector Product (low precision)
• Peak 92,000 G flops/s (8 bit floats)
• Peak H/W Intensity (8-bit) = 2,700 8b flops per byte

https://images.anandtech.com/doci/11749/hc29.22.730-tensorpu-young-google-page-015.jpg

http://3s81si1s5ygj3mzby34dq6qf-wpengine.netdna-ssl.com/wp-content/uploads/2017/05/image004.jpg

4 TPU2’s per card

http://3s81si1s5ygj3mzby34dq6qf-wpengine.netdna-ssl.com/wp-
content/uploads/2017/05/image003.jpg

Introduction CMOS VLSI Design Slide 34

 And Now to 3D Chip Stacks

https://upload.wikimedia.org/wikipedia/commons/thumb/c/c1/Through-
Silicon_Via_Flavours.svg/300px-Through-Silicon_Via_Flavours.svg.png

Introduction CMOS VLSI Design Slide 35

 Scaling and Moore’s Law

Introduction CMOS VLSI Design Slide 36

http://https://upload.wikimedia.org/wikipedia/en/thumb/9/9d/Moore%27s_Law_Transistor_Count_1971-2016.png/1200px-Moore%27s_Law_Transistor_Count_1971-2016.png

Introduction CMOS VLSI Design Slide 37

 Clock Speeds

https://upload.wikimedia.org/wikipedia/en/c/ce/Clock_CPU_Scaling.jpg

Introduction CMOS VLSI Design Slide 38

 Feature Size
 Minimum feature size shrinking 30% every 2-3 years

Today 103

1: Introduction CMOS VLSI Design 4th Ed.

 Corollaries
 Many other factors grow exponentially
– Ex: clock frequency, processor performance

1: Introduction CMOS VLSI Design 4th Ed.

 MOS Transistor Scaling: 1970s- mid 2000s
1974 R. H. Dennard, et. al.

Dimensions 1/K
Channel Width 1/K
Channel Length 1/K
Gate Oxide Thickness 1/K
Green: Diffusion Gate Capacitance 1/K
Red: Oxide Blue:
Metal Power Voltage 1/K
Substrate Doping K
K = “Scale Factor” from one
Circuit Area } 1/K2
generation to next
Speed
Big Win
K
Moore’s Law Current 1/K
Power
K = √ 2 / 2.5 years Power per Unit Area
1/K2
1

Introduction CMOS VLSI Design Slide 40

 MOS Generations
About every 2.5 Years
Dimensions 0.7 X
Channel Length Channel 0.7 X
Width 0.7 X
Gate Oxide Thickness 0.7 X
Gate Capacitance 0.7 X
Stopped
Voltage 0.7 X In ~2005
Substrate Doping 1.4 X
Circuit Area
Peak Speed
0.5 X
1.4 X
} Big Win
Current 0.7 X
Power
Power per Unit Area
X
1/2 X
1
No Longer True
Now Dominates Design Process

Introduction CMOS VLSI Design Slide 41

 Moore’s Law
 Circuit Density - 32% per year
 Circuit Speed
– Scaling - 15% / year
– Architecture and Circuit Design - 10%/year
– Overall - 26%/year
 Chip Size - 15%/year
 Architecture/Parallelism - 35%/year

66% performance improvement per year

Before hitting the Power Wall of 2005

Now Just Architecture/Parallelism

Introduction CMOS VLSI Design Slide 42

 Moore’s Law
 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months

10,000

1,000 Integration Levels

Transistor Count (Millions)

100
SSI: 10 gates
10

1
MSI: 1000 gates
0 LSI: 10,000 gates
VLSI: > 10k gates
0
1975 1980 1985 1990 1995 2000 2005 2010 2015 2020

Historical Single Core Historical Multi-Core ITRS Projections

Introduction CMOS VLSI Design Slide 43

 Moore’s Design Rule
Scaling Law

10,000
10
Design Rule Generation (nm)

1,000
1
Same circuit is 250 X smaller
20 years later

100
0.1

10
0.01
1970 1980 1990 2000 2010 2020

Year

Introduction CMOS VLSI Design Slide 44

 20 Years of Progress

Introduction CMOS VLSI Design Slide 45

 Today’s Transistor Structure

https://image.slidesharecdn.com/ehudtzuri3dchallanges-new-120529041437-phpapp01/95/the-shift-to-3dic-structures-manufacturing-and-process-control-challenges-12-728.jpg?cb=1338264919

Introduction CMOS VLSI Design Slide 46

 Next Gen Transistors

https://www.researchgate.net/profile/Arvind_Singh64/publication/286439699/figure/fig2/AS:389174046806054@14 69797732007/Fig-2-
CNTFET-Structure-Carbon-nanotube-field-effect-transistors-CNTFETs-utilize.jpg
https://www.blogcdn.com/www.engadget.com/media/2007/06/toshiba-3d-nand.jpg
Carbon Nanotube FET
3D Transistor Array

Introduction CMOS VLSI Design Slide 47

 2. MOS Transistors
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

1: Introduction CMOS VLSI Design 4th Ed.

 Dopants
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

1: Introduction CMOS VLSI Design 4th Ed.

 p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode

1: Introduction CMOS VLSI Design 4th Ed.

1: Introduction CMOS VLSI Design 4th Ed.
 nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor Source Gate Drain
Polysilicon
– Even though gate is SiO2
no longer made of metal
n+ n+
Body
p bulk Si

1: Introduction CMOS VLSI Design 4th Ed.

 nMOS Operation
 Body is usually tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

1: Introduction CMOS VLSI Design 4th Ed.

 nMOS Operation Cont.
 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

1: Introduction CMOS VLSI Design 4th Ed.

 pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

1: Introduction CMOS VLSI Design 4th Ed.

 Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
– Lower V -> increase f
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

1: Introduction CMOS VLSI Design 4th Ed.

 Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

1: Introduction CMOS VLSI Design 4th Ed.

 How Does a Transistor Work?
Wall Switch

Power Supply

– In order for the lamp to glow, electrons must flow

– In order for electrons to flow, there must be a closed circuit from
the power supply to the lamp and back to the power supply
– The lamp can be turned on and off by simply manipulating the wall
switch to make or break the closed circuit

CMOS VLSI Design 4th Ed. 61

How Does a Transistor Work?
 Instead of the wall switch, we could use an n-type or a p-type
MOS transistor to make or break the closed circuit
If the gate of an n-type transistor is
Drain supplied with a high voltage, the
connection from source to drain acts
Gate
like a piece of wire (i.e., the circuit is
closed)
Depending on the technology,
Source
high voltage can range from 0.3V to
Schematic of an n-type 3V
MOS transistor
If the gate of the n-type transistor is
supplied with zero voltage, the
connection between the source and
drain is broken (i.e., the circuit is open)
CMOS VLSI Design 4th Ed. 62
How Does a Transistor Work?
 The n-type transistor in a circuit with a battery and a bulb

3
0 Volt
Gate

Power Supply
Shorthand notation

 The p-type transistor works in exactly the opposite fashion

from the n-type transistor
Drain Drain
The circuit is closed The circuit is closed
when the gate is when the gate is
supplied with 3V Gate Gate
supplied with 0V
n-type p-type
Source Source
63
Logic Gates

64
One Level Higher in the Abstraction
 Now, we know how a MOS transistor works
 How do we build logic structures out of MOS transistors?
Problem
 We construct basic logical units out of Algorithm
individual MOS transistors Program/Language
Runtime System
(VM, OS, MM)
 These logical units are called logic gates ISA (Architecture)
 They implement simple Boolean functions Microarchitecture
Logic
Devices
Electrons

George Boole, “The Mathematical Analysis of Logic,” 1847. 65

Making Logic Blocks Using CMOS Technology
 Modern computers use both n-type and p-type transistors,
i.e. Complementary MOS (CMOS) technology
nMOS + pMOS = CMOS

 The simplest logic structure that exists in a modern

computer 3V

p-type

In (A) Out (Y) What does this circuit do?

n-type

0V
66
Functionality of Our CMOS Circuit
What happens when the input is connected to 0V?

3V 3V
p-type transistor
pulls the output up

0V Out (Y) Y = 3V

0V 0V

p-type transistors are good at pulling up the voltage

67
Functionality of Our CMOS Circuit
What happens when the input is connected to 3V?

3V 3V

A= 3V Out (Y) Y = 0V

n-type transistor pulls

the output down

0V 0V

n-type transistors are good at pulling down the voltage

68
CMOS NOT Gate (Inverter)
3V
 This is actually the CMOS NOT Gate
 Why do we call it NOT? P
 If A = 0V then Y = 3V In (A) Out (Y)
If A = 3V then Y = 0V
N


 Digital circuit: one possible interpretation

 Interpret 0V as logical (binary) 0 value
0V
 Interpret 3V as logical (binary) 1 value

A P N Y
0 ON OFF 1
1 OFF ON 0

69
 3. CMOS logic gates
CMOS Inverter
VDD
A Y
0 1 OFF
ON
0
1
1 0 A Y
ON
OFF

A Y
GND
3: CMOS Technology CMOS VLSI Design 4th Ed.
 CMOS NAND Gate
A B Y
0 0 1 ON
OFF
OFF
ON OFF
ON
0 1 1
1
Y
0
1 0 1
A ON
OFF
1 1 0 0
1
1
0
B OFF
ON
ON
OFF

3: CMOS Technology CMOS VLSI Design 4th Ed.

CMOS AND Gate
 How can we make an AND gate?
A B Y
0 0 0
0 1 0 A
1 0 0 Y
1 1 1 B
3V 3V
We make an AND gate using
one NAND gate and P1 P2 P3
one NOT gate Out (Y)
In (A) N1 N3

In (B) N2
0V

0V

72
CMOS NOT, NAND, AND Gates
A A
A Y Y Y
B B

A Y A B Y A B Y
0 1 0 0 1 0 0 0
1 0 0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
3V
3V 3V 3V

P1 P2 P1 P2 P3
P Out (Y)
Out (Y)
In (A) Out (Y) In (A) N1 In (A) N1 N3
N
In (B) N2 In (B) N2
0V

0V 0V 0V

73
 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

3: CMOS Technology CMOS VLSI Design 4th Ed.

 3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0

Y
A
B
C

3: CMOS Technology CMOS VLSI Design 4th Ed.

 4. IC Design Flow

1: Introduction CMOS VLSI Design 4th Ed.

 Logic Design
 Define the top-level chip interface and block diagram
 Specify the logic with a Hardware Description Language (HDL),
which provides a higher level of abstraction than schematics or
layout.
 This code is called the Register Transfer Level (RTL) description.

module adder(
input logic [7:0] a, b,
input logic c,
output logic [7:0] s,
output logic cout);

1: Introduction CMOS VLSI Design 4th Ed.

 Circuit Design
 Circuit design is to arrange transistors to perform a
particular logic function.
 A particular logic function can be implemented in
many ways
 Circuit designers often draw schematics at the
transistor and/or gate level.

1: Introduction CMOS VLSI Design 4th Ed.

 Physical Design
 Physical design is to map the RTL into actual geometric representations
of all electronics devices, such as capacitors, resistors, logic gates, and
transistors
 Physical design step:
– Floorplanning: The RTL of the chip is assigned to gross regions of
the chip, input/output (I/O) pins are assigned and large objects
(arrays, cores, etc.) are placed.
– Placement: The gates in the netlist are assigned to non-overlapping
locations on the die area.
– Clock insertion: Clock signal wiring is (commonly, clock trees)
introduced into the design.
– Routing: The wires that connect the gates in the netlist are added.
– Final checking
– Tapeout: and mask generation: the design data is turned into
photomasks

1: Introduction CMOS VLSI Design 4th Ed.

 Design Verification
 Design verification is essential to catching the
errors before manufacturing
 A testbench is used to verify that the logic is
correct
 Formal verification tools are to check that a
circuit performs the same Boolean function as
the associated logic.
 Layout vs. Schematic tools (LVS) check that
transistors in a layout are connected in the
same way as in the circuit schematic.
 Design rule checkers (DRC) verify that the
layout satisfies design rules.
 Electrical rule checkers (ERC) scan for other
potential problems such as noise or premature
wearout;

1: Introduction CMOS VLSI Design 4th Ed.

Fabrication, Packaging, and Testing

 The mask descriptions are sent to the

manufacturer electronically for fabrication.
 Two common formats for mask descriptions:
– Caltech Interchange Format (CIF) (mainly
used in academia)
– Calma GDS II Stream Format (GDS:
Graphic Database System) (used in
industry).
 A set of masks for a nanometer process can be very expensive.
– In a 65 nm process, the mask set costs about $3 million
– With a university discount, the cost for a run of 40 small chips
on a multi-project wafer can run about $10,000 in a 130 nm
process down to $2000 in a 0.6 µm process.
1: Introduction CMOS VLSI Design 4th Ed.
 Review
1. What do they mean?
1. IC, VLSI, HDL, RTL, LVS, DRC, ERC, CIF, GDSII, BJT,
MOSFET, CMOS
2. Describe brief history of transistors
3. How to make a MOS transistor?
4. What are differences between nMOS and pMOS?
5. What is IC design flow?
6. Describe logic design
7. Describe circuit design
8. Describe physical design
9. What are CMOS logic gates?
10. Sketch a transistor-level schematic for a CMOS 4-input NOR
11. Sketch a transistor-level schematic for a CMOS 4-input NAND
1: Introduction CMOS VLSI Design 4th Ed.
 Chapter 2:
MOS
Transistor
Theory
1. MOS transistor operation
2. I-V characteristics
3. C-V characteristics
4. DC transfer characteristics

2: MOS Transistor Theory 1

1. MOS Transistor Operation
❑ So far, we have treated transistors as ideal switches
❑ An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
❑ Transistor gate, source, drain all have capacitance
– I = C (V/t) -> t = (C/I) V
– Capacitance and current determine speed

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 2

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 3
 Electrical Property of MOS Devices

▪▪ Necessary to understand the basic electrical properties of

the MOS transistor (geometry => electrical), e.g., delay/power
– Ensure that the circuits are robust
– Create working layouts
– Predict delays and power consumption

▪▪ As technology advances and circuit dimensions scale down,

Electrical effects become more important
– Secondary/non-‐ideal effects (next lecture)

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 4

 MOS Capacitor
❑ Gate and body form MOS
capacitor polysilicon gate

❑ Operating modes
V <0 g
silicon dioxide insulator
+
- p-type body
– Accumulation
– Depletion (a)

– Inversion 0<V <V g t

depletion region
+
-

(b)

Vg > Vt
inversion region
+
- depletion region

(c)

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 5

 MOS Capacitor

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 6

 The nMOS transistor

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 7

 Terminal Voltages
❑ Mode of operation depends on Vg, Vd, Vs Vg

– Vgs = Vg – Vs Vgs
+ +
Vgd
– Vgd = Vg – Vd - -

– Vds = Vd – Vs = Vgs - Vgd Vs

-
Vds +
Vd

❑ Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds  0
❑ nMOS body is grounded. First assume source is 0 too.
❑ Three regions of operation
– Cutoff
– Linear
– Saturation

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 8

 nMOS

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 9

 nMOS Cutoff
❑ No channel
❑ Ids ≈ 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 10

 nMOS Linear
❑ Channel forms
❑ Current flows from d to s
V > Vt
– e from s to d Vgd = Vgs
gs
- + g +
- -
❑ Ids increases with Vds s d
Vds = 0
n+ n+
❑ Similar to linear resistor p-type body
b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 11

 nMOS Saturation
❑ Channel pinches off
❑ Ids independent of Vds
❑ We say current saturates
❑ Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 12

 The pMOS transistor

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 13

 2. I-V Characteristics
❑ In Linear region, Ids
depends on
– How much charge
is in the channel?
– How fast is the
charge moving?

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 14

 Channel Charge
❑ MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
❑ Qchannel = CV
❑ C = Cg = oxWL/tox = CoxWL Cox = ox / tox
❑ V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 15

 Channel Charge
▪ MOS structure looks like parallel
plate capacitor while operating in
inversion:
▪ Gate – oxide – channel
▪ Qchannel = CV
▪ C = Cg = oxWL/tox = coxWL
▪ V = Vgc – Vt = (Vgs – Vds/2) – Vt

cox = ox / tox

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 16

 Carrier velocity

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 17

 nMOS Linear I-V
Now we know:
How much charge Qchannel is in
the channel
How much time t each carrier
takes to cross
Qchannel
I ds =
t
= Cox
W V − V − Vds V
 gs t  ds
L  2 
=  Vgs − Vt − ds Vds
V W
 = Cox
 2 L
2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 18
 nMOS Saturation I-V
❑ If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
❑ Now drain voltage no longer increases current


I ds =  Vgs − Vt −
Vdsat V
 dsat
 2 

( − Vt )
2
= V gs
2

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 19

 nMOS I-V Summary
❑ Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds =   Vgs − Vt −  ds linear
 2 
ds dsat

 
(Vgs − Vt )
2
 Vds  Vdsat saturation
2

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 20

Tóm tắt cách tìm quan hệ dòng và áp trong N-EMOS
dq dq dx
i= = (1)
dt dx dt
Q = CV  ox
Cox = (4.2)
(2)
tox
 ox = 3.9 0 = 3.9  8.854  10−12 = 3.45  10−11 F/m
dq = −Cox (Wdx ) GS −  ( x ) − Vt  (4.3)
(3)
d ( x )
E( x) = − ( E = −V )
dx
dx d ( x )
= − n E ( x ) = n (4)
(4.4)
dt dx
d ( x )
i = − nCoxW GS −  ( x ) − Vt 
dx
d ( x )
iD = − i = nCoxW GS −  ( x ) − Vt 
dx
 ox
Cox = (4.2)
iDdx = nCoxW GS − Vt −  ( x )d ( x ) kn = nCox (7)
(4.7) tox
(2)

 DS W  1 2 
 iD dx = 
L
nCoxW GS − Vt −  ( x )d ( x ) iD = kn   (GS − Vt ) DS − 2  DS  (Triode region) (5a)
(4.5a)
0 0  L  
W  1 2 
iD = ( nCox )   (GS − Vt ) DS −  DS  (4.5)
(5) 1 W 
 L   iD = k  (GS − Vt )
2
(6a)
2 n  L
2 (saturation region) (4.6a)

Khi vào miền bão hòa, υDS= υGS - Vt
W 
1 W   L  : Aspect ratio of the MOSFET
iD = ( nCox )   (GS − Vt ) (4.6)
2
(6)   (Tỉ số hình dạng của MOSFET)
2  L 
21
 Example
❑ We will be using a 0.6 m process for your project
– From AMI Semiconductor
– tox = 100 Å 2.5
V =5
–  = 350 cm /V*s
2
gs

2
– Vt = 0.7 V 1.5 V =4

Ids (mA)
gs

❑ Plot Ids vs. Vds 1

– Vgs = 0, 1, 2, 3, 4, 5 0.5
V =3 gs

– Use W/L = 4/2 l

V =2 gs
V =1 gs
0
0 1 2 3 4 5
W  3.9  8.85 10−14   W  W Vds
 = Cox = ( 350 )  −8   = 120 μA/V 2
L  100 10  L  L

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 22

 pMOS I-V
❑ All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
❑ Mobility p is determined by holes
– Typically 2-3x lower than that of electrons n
– 120 cm2/V•s in AMI 0.6 m process
0

❑ Thus pMOS must be wider to

Vgs = -1
Vgs = -2

provide same current

-0.2
Vgs = -3

– In this class, assume

Ids (mA)
-0.4
Vgs = -4

n / p = 2 -0.6

Vgs = -5
-0.8
-5 -4 -3 -2 -1 0
Vds

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 23

 Assignment
❑ Consider an nMOS transistor in a 0.6 m process
with W/L = 4/2 l (i.e., 1.2/0.6 m). In this process,
the gate oxide thickness is 100 Ao and the mobility of
electrons is 350 cm2/V· s. The threshold voltage is
0.7 V. Plot Ids vs. Vds for Vgs = 0, 1, 2, 3, 4, and 5 V.

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 24

 3. C-V Characteristics
❑ Any two conductors separated by an insulator have
capacitance
❑ Gate to channel capacitor is very important
– Creates channel charge necessary for operation
❑ Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 25

 Gate Capacitance
❑ Approximate channel as connected to source
❑ Cg = CoxWL = CpermicronW
❑ Cpermicron = CoxL = oxL/tox
❑ Cpermicron is typically about 2 fF/m

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 26

 Gate Capacitance
▪ When the transistor is off, the channel is not inverted
Cg = Cgb = oxWL/tox = CoxWL
▪ Let’s call CoxWL = C0
▪ When the transistor is on, the channel extends from the source
to the drain (if the transistor is unsaturated, or to the pinchoff
point otherwise)
Cg = Cgb + Cgs + Cgd

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 27

 Gate Capacitance

In reality the gate overlaps source and drain.

Thus, the gate capacitance should include not
only the intrinsic capacitance but also parasitic
overlap capacitances:
Cgs(overlap) = Cox W LD
Cgs(overlap) = Cox W LD

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 28

 Device Capacitances, Cont’d

Linear Region
Depletion region exists, forming dielectric of depletion
capacitance, Cdep in series with Cox
As the device turns on, Cgb reduces to 0
The gate capacitance is now a function of the gate voltage

ECE Department, University of Texas at Austin Lecture 4. MOS Transistor Theory

 Device Capacitances, Cont’d
Saturated Region
Region under the gate is heavily inverted, and drain region of
channel pinched off, with Cgd reducing to zero
Gate capacitance is now less than Cox

Approximation of Gate Capacitance

For simplicity, we can assume the gate capacitance to be
constant, Cg = A/tox
ECE Department, University of Texas at Austin Lecture 4. MOS Transistor Theory
 Diffusion (Source/Drain) Capacitance
Capacitance at the drain (Cdb) or
source (Csb) of a device, or
when diffusion is used as a wire

Two components:
1 An Area component
2 A Peripheral
(sidewall) component
The peripheral component
comes from the depth of the
diffusion

Assume diffusion capacitance is

approximately Cg for
contacted diffusion
It is 1/2Cg for
uncontacted diffusion
ECE Department, University of Texas at Austin Lecture 4. MOS Transistor Theory
Detailed Gate Capacitance
Capacitance Cutoff Linear Saturation
Cgb (total) C0 0 0
Cgd (total) CoxWLD C0/2 + CoxWLD CoxWLD
Cgs (total) CoxWLD C0/2 + CoxWLD 2/3 C0+ CoxWLD

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 32

 Diffusion Capacitance
❑ Csb, Cdb
❑ Undesirable, called parasitic capacitance
❑ Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 33

Lumped representation of the MOSFET capacitances

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 34

 Review
1. Which factors affect to switching speed of MOS
transistors?
2. What are three operation modes of MOS
transistors?
3. When is a MOS transistor OFF?
4. When does a MOS transistor operate in saturation
region?
5. What does the drain-source current Ids depend on?
6. What does the gate capacitance Cg depend on?

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 35

4. DC Transfer Characteristics
❑ Assuming the input changes slowly enough that
capacitances have plenty of time to charge or
discharge.
❑ Specific ranges of input and output voltages are
defined as valid 0 and 1 logic levels

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 36

 DC Response
❑ DC Response: Vout vs. Vin for a gate
❑ Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
VDD
– In between, Vout depends on
transistor size and current Idsp
Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 37

 Transistor Operation
❑ Current depends on region of transistor behavior
❑ For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 38

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 39

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 40

 I-V Characteristics
❑ Make pMOS is wider than nMOS such that n = p
Vgsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 41

 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 42

 Load Line Analysis
❑ For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 43

 Load Line Analysis
❑ Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD

Vin0 Vin5
in5

Vin1 Vin4
dsn, |Idsp
Idsn dsp
|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
in0
VDD
Vout
out
DD

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 44

 DC Transfer Curve
❑ Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 45

 Operating Regions
❑ Revisit transistor operating regions VDD

Vin Vout

Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B

C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 46

 Beta Ratio
❑ If p / n  1, switching point will move from VDD/2
❑ Called skewed gate
❑ Other gates: collapse into equivalent inverter
VDD
p
= 10
n
Vout 2
1
0.5
p
= 0.1
n

0
VDD
Vin

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 47

 Noise Margins
❑ How much noise can a gate input see before it does
not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 48

 Logic Levels
❑ To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic

Vout

Unity Gain Points

VDD
Slope = -1
VOH

 p/ n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 49

 Transient Response
❑ DC analysis tells us Vout if Vin is constant
❑ Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
❑ Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 50

 Inverter Step Response
❑ Ex: find step response of inverter driving load cap
Vin (t ) = u (t − t0 )VDD
Vin(t)
Vout (t  t0 ) = VDD Vout(t)
Cload
dVout (t ) I dsn (t )
=− Idsn(t)
dt Cload
Vin(t)

 0 t  t0

I dsn (t ) =  
( − ) Vout  VDD − Vt
2
2 V DD V Vout(t)
 t
  VDD − Vt − out 2  V (t ) V  V − V
V (t )
 out t0
  
out DD t

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 51

 Pass Transistors
❑ We have assumed source is grounded
❑ What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
❑ Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
❑ nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
❑ pMOS pass transistors pull no lower than Vtp
❑ Transmission gates are needed to pass both 0 and 1

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 52

 Pass Transistor Ckts

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 53

 Pass Transistor Ckts

VDD VDD VDD

VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn

VDD
VDD-Vtn
Vs = |Vtp|
VDD VDD-2Vtn
VSS

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 54

 Pass Transistor Ckts

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 55

 Example 1
Assumption: initial voltage on each node is 2.5 volts
Relevant transistor parameters are, Vdd = 5V , Vtn = 1V and
|Vtp| = 0.7V

ECE Department, University of Texas at Austin Lecture 4. MOS Transistor Theory

 Example 1, Cont’d

Vdd = 5V , Vtn = 1V and |Vtp| = 0.7V

ECE Department, University of Texas at Austin Lecture 4. MOS Transistor Theory

 Example 2
Assume: initial voltage of 0.5V on all the internal nodes
Vdd = 1.0V , Vtn = 0.2V and |Vtp|= 0.2V

ECE Department, University of Texas at Austin Lecture 4. MOS Transistor Theory

 Example 2, Cont’d
Assume: initial voltage of 0.5V on all the internal nodes
Vdd = 1.0V , Vtn = 0.2V and |Vtp|= 0.2V

ECE Department, University of Texas at Austin Lecture 4. MOS Transistor Theory

 Transmission Gates
▪ Pass transistors produce degraded outputs
▪ Transmission gates pass both 0 and 1 well

CMOS VLSI Design 4th Ed.

Transmission gate ON resistance

CMOS VLSI Design 4th Ed.

 Review
1. What are conditions for Vgs when the nMOS is in cutoff, linear,
and saturated modes?
2. What is noise margin?
3. What is transmission gate and its applications?
4. What are Vtp and Vtn ?
5. Give expressions for the output voltage.

2: MOS Transistor Theory CMOS VLSI Design 4th Ed. 62

 CMOS
Technology

1. Basic Processing Steps

2. CMOS Fabrication
3. Layout Design Rules

3: CMOS Technology
Basic Integrated Circuit
Processing
 Lecture Outline
• Details of the physical structure of devices will be very
important in developing models for electrical behavior
• Device structure is better understood by following through
fabrication sequence
• The basic processing steps used in fabricating integrated
devices will be examined in this lecture, then the use of
these process steps in fabricating a diode, bipolar junction
transistor or FET will be dealt with in later lectures

ELEC 3908, Physical Electronics:

David J. Walkey Page 3
Basic IC Processing (4)
 Ingot Growth
• First step in production of an
integrated circuit is growth of a
large piece of almost perfectly
crystalline semiconducting
material called an ingot (boule)
• Small seed crystal is suspended
in molten material then pulled
(1m/hr) and rotated (1/2 rps) to
form the ingot
• Result is an ingot approx. 1m
long and anywhere from 75 to
300 mm in diameter
• Dopant is almost always added
to the molten material

ELEC 3908, Physical Electronics:

David J. Walkey Page 4
Basic IC Processing (4)
 Ingot Growth

ELEC 3908, Physical Electronics:

David J. Walkey Page 5
Basic IC Processing (4)
 Wafer Sawing
• Ingots are then sawed into wafers approximately 500-1000
µm (0.5 to 1 mm) thick using a diamond tipped saw
• Wafers are the starting material for integrated circuit
manufacture, and are normally referred to as the substrate
• Surface of the wafer is smoothed with combination of
chemical and mechanical polishing steps

ELEC 3908, Physical Electronics:

David J. Walkey Page 6
Basic IC Processing (4)
 Photolithography
• Lithography refers to the transfer of an image onto paper
using a plate and ink-soluble grease
• Photolithography is the transfer of an image using
photographic techniques
• Photolithography transfers designer generated information
(device placement and interconnections) to an actual IC
structure using masks which contain the geometrical
information
• The process of photolithography is repeated many times in
manufacture of an IC to build up device structures and
interconnections

ELEC 3908, Physical Electronics:

David J. Walkey Page 7
Basic IC Processing (4)
 Photolithography - Application of Photoresist
• First step in photolithography is
to coat the surface with approx
1 µm of photoresist (PR)
• PR will be the medium whereby
the required image is transferred
to the surface
• PR is often applied to the center
of the wafer, which is then spun
to force the PR over the entire
surface
• Note that the scale of these
diagrams is not correct - the PR
is approx. 1 µm thick while the
wafer is 1000 µm thick.

ELEC 3908, Physical Electronics:

David J. Walkey Page 8
Basic IC Processing (4)
 Photolithography - Exposure
• The PR is then exposed to UV
(ultraviolet) radiation through a
mask UV radiation
• The masks generated from
information about device mask mask
placement and connection
• The UV radiation causes a
chemical change in the PR
• The transfer of information wafer
from the mask to the surface
occurs through the UV-induced
chemical change - only occurs
where the mask is transparent

ELEC 3908, Physical Electronics:

David J. Walkey Page 9
Basic IC Processing (4)
 Photolithography - Development
• The PR is then developed using
a chemical developer
• Two possibilities:
– A negative PR is hardened
against the developer by the
UV radiation, and hence
remains on the surface where
UV shone through the mask
– A positive PR is the opposite,
it is removed where the UV
shone through the mask
• Assume a negative PR for this
example, so the PR on the sides
will be weakened and removed
by the developer

ELEC 3908, Physical Electronics:

David J. Walkey Page 10
Basic IC Processing (4)
 Photolithography

Feature on mask Feature on mask

results in feature on silicon results in negative feature on silicon

CMOS Processing CMOS VLSI Design

 Photolithography - Final Structure
• Once the developer has been
washed off, the result is PR in (mask shown to indicate final region)
the region corresponding to the mask mask
transparent part of the mask
(the mask is shown again to
indicate where the final region selected area
is formed – it is not part of the
final structure)
• Subsequent processing steps
will use this structure to form wafer
device areas, interconnects, etc.
• Note that an optically reversed
mask and a positive resist
would give the same structure

ELEC 3908, Physical Electronics:

David J. Walkey Page 12
Basic IC Processing (4)
 Mask Generation - Reticle
• The geometry information over
the entire IC required for a
particular photolithography step
is used to create a reticle, a 10X
sized optical plate
• There can be anywhere from 6
to 24+ individual
photolithography steps in a
manufacturing process, each
with its own set of geometrical
information captured in a reticle

ELEC 3908, Physical Electronics:

David J. Walkey Page 13
Basic IC Processing (4)
 Mask Generation - Step and Repeat
• In order to fabricate many devices simultaneously, the reticle
information is reduced and projected many times onto a 1X mask using
a step and repeat process

ELEC 3908, Physical Electronics:

David J. Walkey Page 14
Basic IC Processing (4)
 Mask Generation - Final 1X Mask
• The 1X mask which results
from the step and repeat process
contains all the information for
a particular photolith step for all
chips which will be fabricated
on the wafer
• This image is projected during
the exposure step to cause PR
chemical changes in the
appropriate locations

ELEC 3908, Physical Electronics:

David J. Walkey Page 15
Basic IC Processing (4)
 Reticle and Mask Example

1:1 Mask 4:1 Reticle

ELEC 3908, Physical Electronics:

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Basic IC Processing (4)
 Example Simple Mask Set
• Shown below is a highly simplified layout for a two
transistor digital gate, and the masks which would be
required based on its layout (see MOSFET)
• Not in notes, just shown as an example of how masks are
derived from a user-generated layout
layout (4 layers) layer 1 mask layer 2 mask layer 3 mask layer 4 mask

ELEC 3908, Physical Electronics:

David J. Walkey Page 17
Basic IC Processing (4)
 Etching - Dry and Wet Processes
• Etching is the selective removal
of material from the chip
surface
• In dry etching, ions of a neutral
material are accelerated toward
the surface and cause ejection
of atoms of all materials
• In wet etching, a chemical
etchant is used to remove
material via a chemical reaction

ELEC 3908, Physical Electronics:

David J. Walkey Page 18
Basic IC Processing (4)
 Etching - Selectivity and Anisotropy
• Two most important issues in etching are selectivity and anisotropy
– Selectivity refers to the ability of an etchant to remove one material on the
surface while leaving another intact.
– Isotropic refers to the tendency of the etching to proceed laterally as well
as downward

ELEC 3908, Physical Electronics:

David J. Walkey Page 19
Basic IC Processing (4)
 Thermal Oxidation - Oxidation Furnace
• One of the simplest steps in IC processing is thermal oxidation, the
growth of a layer of silicon dioxide (SiO2) on the substrate surface
• Requires only substrate heating to 900-1200 °C in a dry (O2) or wet
(H20 steam) ambient using an oxidation furnace
• Silicon oxidizes quite readily - one reason why Si is so widely used

ELEC 3908, Physical Electronics:

David J. Walkey Page 20
Basic IC Processing (4)
 Oxidation – Boat/Tube Examples

ELEC 3908, Physical Electronics:

David J. Walkey Page 21
Basic IC Processing (4)
 Oxidation - System

ELEC 3908, Physical Electronics:

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Basic IC Processing (4)
 Thermal Oxidation - Oxide Formation
• Oxide forms due to the
chemical reaction between
oxygen in the ambient and
silicon in the substrate
• Substrate silicon is consumed
during the reaction, so oxide
layer grows in both directions
from the original substrate
surface (approx. 50/50)

ELEC 3908, Physical Electronics:

David J. Walkey Page 23
Basic IC Processing (4)
 Thermal Oxidation - Wet vs. Dry Rates
• Due to the different reaction
mechanisms, oxidation in a wet
ambient is many times faster
than oxidation in a dry ambient
• However, the oxide quality is
much better when a dry ambient
is used
• Thick isolation layers are
therefore formed using wet
oxidation, while MOSFET gate
oxides are formed with dry
oxidation

ELEC 3908, Physical Electronics:

David J. Walkey Page 24
Basic IC Processing (4)
 Local Oxidation
• The presence of another
material such as silicon nitride
(Si3N4) on the surface inhibits
the growth of oxide in that
region
• This allows selective or local
oxidation of the substrate
surface - will be used to isolate
devices or conductive layers
• Some oxidation does occur
laterally under the nitride layer,
giving rise to the bird’s beak
effect

ELEC 3908, Physical Electronics:

David J. Walkey Page 25
Basic IC Processing (4)
 Dopant Diffusion
• Dopant can be introduced into
the substrate through diffusion
• Diffusion is a general physical
process which drives particles
down a concentration gradient
• The substrate is heated in the
presence of dopant atoms,
which then diffuse into the
substrate
• Diffusion may also occur into
other layers which are present
such as silicon dioxide
• Large amount of lateral
diffusion also occurs

ELEC 3908, Physical Electronics:

David J. Walkey Page 26
Basic IC Processing (4)
 Ion Implantation
• In ion implantation, dopant
atoms are accelerated toward
the substrate surface and enter
due to their kinetic energy
• This is the preferred technique
for introduction of dopant
atoms since the amount of
lateral diffusion is much lower

ELEC 3908, Physical Electronics:

David J. Walkey Page 27
Basic IC Processing (4)
 Ion Implantation System

Ion source

Plasma
Extraction assembly

Analyzing magnet
Acceleratio
Ion beam Process
n column chamber
Scanning
disk

ELEC 3908, Physical Electronics:

David J. Walkey Page 28
Basic IC Processing (4)
 Ion Implantation - Predep and Drive-in
• Ion implantation can be
used to form a deep region
of doping using a two step
procedure
– A high concentration of
dopant is deposited near
the surface in the
predeposition or predep
stage
– The dopant source is then
removed and the wafer
heated to cause
redistribution of the
dopant via diffusion in the
drive-in stage

ELEC 3908, Physical Electronics:

David J. Walkey Page 29
Basic IC Processing (4)
 Deposition
• Layers of materials such as metal (and in some cases
silicon dioxide) may need to be formed on the surface
• General procedure of forming a layer of material on the
surface is termed deposition
• Two types can be identified, physical and chemical
– In physical deposition, a piece (target) of the material to be
deposited is bombarded with ions, ejecting atoms of material which
then adhere to the substrate surface
– Chemical deposition uses an ongoing chemical reaction to form the
desired material as a precipitate on the substrate surface
• A specialized form of deposition is epitaxy, the formation
of a layer of crystalline semiconductor material

ELEC 3908, Physical Electronics:

David J. Walkey Page 30
Basic IC Processing (4)
 Sputtering System

ELEC 3908, Physical Electronics:

David J. Walkey Page 31
Basic IC Processing (4)
 Patterning
• The use of a series of PR deposition, exposure,
development and etching to create regions of particular
shape is called patterning
• For example, if a newly deposited metal layer was coated
with PR, exposed using a mask, developed and etched
using a method which selectively removed the metal not
covered by the PR, this would be referred to as
“patterning” the metal
• There will be many individual patterning steps in the
creation of a useful integrated structure

ELEC 3908, Physical Electronics:

David J. Walkey Page 32
Basic IC Processing (4)
 Final Fabricated Wafer

ELEC 3908, Physical Electronics:

David J. Walkey Page 33
Basic IC Processing (4)
 Scribing and Cleaving
• After processing is finished, the wafers are separated into individual
dice by scribing and cleaving
– Scribing refers to creating a groove along scribe channels which have
been left between the rows and columns of individual chips (during mask
generation)
– Cleaving is the process of breaking the wafer apart into individual dice

ELEC 3908, Physical Electronics:

David J. Walkey Page 34
Basic IC Processing (4)
 Dicing Machine

ELEC 3908, Physical Electronics:

David J. Walkey Page 35
Basic IC Processing (4)
 Lecture Summary
• A number of important processing steps were discussed
– Wafer preparation
– Photolithography
– Etching
– Thermal and Local Oxidation
– Dopant Diffusion and Ion Implantation
– Deposition
– Patterning
– Scribing and cleaving
• Next lecture will examine how these processing steps are
used in sequence to generate integrated diode structures

ELEC 3908, Physical Electronics:

David J. Walkey Page 36
Basic IC Processing (4)
 1. CMOS Fabrication
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press
 On each step, different materials are deposited or
etched
 Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Inverter Cross-section
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

3: CMOS Technology CMOS VLSI Design 4th Ed.

Well and Substrate Taps
 Substrate must be tied to GND and n-well to VDD
 Metal to lightly-doped semiconductor forms poor
connection called Schottky Diode
 Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Well and Substrate Taps
What is Latchup: Latchup refers to short circuit formed between power and ground rails in an
IC leading to high current and damage to the IC. Speaking about CMOS transistors, latch up is
the phenomenon of low impedance path between power rail and ground rail due to interaction
between parasitic pnp and npn transistors. The structure formed by these resembles a Silicon
Controlled rectifier (SCR, usually known as a thyristor, a PNPN device used in power
electronics). These form a +ve feedback loop, short circuit the power rail and ground rail,
which eventually causes excessive current, and can even permanently damage the device.

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Inverter Mask Set
 Transistors and wires are defined by masks
 Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Detailed Mask Views
 Six masks n well

– n-well
– Polysilicon
Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Fabrication
 Chips are built in huge factories called fabs
 Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Fabrication Steps
 Start with blank wafer
 Build inverter from the bottom up
 First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Oxidation
 Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Photoresist
 Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Lithography
 Expose photoresist through n-well mask
 Strip off exposed photoresist

Photoresist
SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Etch
 Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Strip Photoresist
 Strip off remaining photoresist
– Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step

SiO2

p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 n-well
 n-well is formed with diffusion or ion implantation
 Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
 Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Polysilicon
 Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Polysilicon Patterning
 Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Self-Aligned Process
 Use oxide and masking to expose where n+ dopants
should be diffused or implanted
 N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 N-diffusion
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion
 Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 N-diffusion cont.
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called diffusion

n+ n+ n+

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 N-diffusion cont.
 Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 P-Diffusion
 Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate

3: CMOS Technology CMOS VLSI Design 4th Ed.

 2. Layout Design Rules
 Describes actual layers and geometry on the silicon
substrate to implement a function
 Need to define transistors, interconnection
– Transistor widths (for performance)
– Spacing, interconnect widths, to reduce defects, satisfy power
requirements
– Contacts (between poly or active and metal), and vias (between
metal layers)
– Wells and their contacts (to power or ground)
 Layout of lower-‐level cells constrained by higher‐level
requirements:
– “floorplanning”
3: CMOS Technology CMOS VLSI Design 4th Ed.
 2. Layout Design Rules
 Chips are specified with set of masks
 Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
 Feature size f = distance between source and drain
– Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design
rules
 Express rules in terms of λ = f/2
– E.g. λ = 0.3 µm in 0.6 µm process

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Simplified Design Rules
 Conservative rules to get you started

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Inverter Layout
 Transistor dimensions specified as Width / Length
– Minimum size is 4λ / 2λ, sometimes called 1 unit
– In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm
long

3: CMOS Technology CMOS VLSI Design 4th Ed.

 Advanced Processes

CMOS Processing CMOS VLSI Design Slide 48

 Twin Tub CMOS w/STI & Al-W metal
Circa 1997
CMP Oxide

metal (Al)

TiSi TiSi
n-poly p-poly

STI Source NMOS Drain Drain PMOS Source

P- Epitaxial Layer
P+ Substrate
contact (W)

CMOS Processing CMOS VLSI Design Slide 49

 Why Changes?

 CMP Oxide
 Chemical Mechanical Polishing (CMP)
 Flatten surface to enable multiple levels of metal
 Tungsten (W) contacts and Vias
 Enable use of CMP
 P+ Substrate
 Reduce substrate resistance and thus reduce latch-up.
 P- Epi
 Needed to enable p and n transistor tub doping with P+
Substrate
 Shallow Trench Isolation (STI)
 Reduce source and drain capacitance
 Reduce source and drain spacing
 Tungsten-Silicide
 Reduce gate resistance

CMOS Processing CMOS VLSI Design Slide 50

 Twin Tub CMOS w/ STI & Al-W metal

CMP Oxide

metal (Al)

WSi WSi
n-poly p-poly

STI
P- Epitaxial Layer
P+ Substrate

Deep Tub Implant VT Adjust

(Shallow Implant)

CMOS Processing CMOS VLSI Design Slide 51

 Dual Damascene Cu Process

CMOS Processing CMOS VLSI Design Slide 52

 TSMC 0.18 CMOS Cross Section

Al Metal 3
W Via 2
Al Metal 2
W Via 1
Al Metal 1
W Contact

Shallow Source SiO2

Trench Poly Drain
Isolation
(STI) Gate
CMOS Processing CMOS VLSI Design Slide 53
 130 nm transistor

WSi
Spacer

Poly Si
Gate Source/Drain

CMOS Processing CMOS VLSI Design Slide 54

 Deep Sub Micron Progress

http://www.zdnet.com/blog/computers/why-intels-22nm-technology-really-matters/5703

CMOS Processing CMOS VLSI Design Slide 55

 Intel 45 nm Transistor

http://www.eetimes.com/design/automotive-design/4004782/Under-the-Hood-Intel-s-45-nm-high-k-metal-gate-process

CMOS Processing CMOS VLSI Design Slide 56

 TriGate or FinFET Transistor

http://www.electronicproducts.com/uploadedImages/Digital_ICs/Microprocessors_Microcontrollers_DSPs/MOUCM_Processing0102_AUG2013.jpg

CMOS Processing CMOS VLSI Design Slide 57

 32 and 28 nm Transistors

http://www.sciencedirect.com/science/article/pii/S0040609011018335

CMOS Processing CMOS VLSI Design Slide 58

 Intel 22 nm Tri-gate Transistor

http://www.electroiq.com/blogs/chipworks_real_chips_blog/2012/04/intel-s-22-nm-trigate-transistors-exposed.html

CMOS Processing CMOS VLSI Design Slide 59

 10nm FINFET

http://www.electronicproducts.com/uploadedImages/Digital_ICs/Microprocessors_Microcontrollers_DSPs/MOUCM_Processing0103_AUG2013.jpg

CMOS Processing CMOS VLSI Design Slide 60

 A 10nm Protein Transistor

http://www.nature.com/nnano/journal/v7/n3/fig_tab/nnano.2012.7_F2.html
CMOS Processing CMOS VLSI Design Slide 61
 Carbon Nanotube Transistor

http://www.infineon.com/export/sites/default/media/press/Image/migration/nanotube_english.jpg

CMOS Processing CMOS VLSI Design Slide 62

 Review
1. Which material is for a blank wafer?
2. How many masks is for a basic CMOS inverter?
3. How to create SiO2 layer on the wafer?
4. How to etch the SiO2 layer?
5. How to form the n-well on the p substrate?
6. What is self-aligned process?
7. What is feature size? What is λ?
8. What are distances between two metals, two polysilicons, two
metal vias?
9. Explain the following picture:

3: CMOS Technology CMOS VLSI Design 4th Ed.

Lecture:
Circuits &
Layout
 Outline
 CMOS Gate Design
 Pass Transistors
 CMOS Latches & Flip-Flops
 Standard Cell Layouts
 Stick Diagrams

1: Circuits & Layout CMOS VLSI Design 4th Ed. 2

 CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NOR gate

A
B
C
D
Y

1: Circuits & Layout CMOS VLSI Design 4th Ed. 3

 CMOS Circuit Styles
 Static complementary CMOS - except during switching,
output connected to either VDD or GND via a low-
resistance path
 high noise margins
- full rail to rail swing
- VOH and VOL are at VDD and GND, respectively
 low output impedance, high input impedance
 no steady state path between VDD and GND (no static power
consumption)
 delay a function of load capacitance and transistor resistance
 comparable rise and fall times (under the appropriate transistor
sizing conditions)

 Dynamic CMOS - relies on temporary storage of signal

values on the capacitance of high-impedance circuit
nodes
 simpler, faster gates
 increased sensitivity to noise
CSE477 L06 Static CMOS Logic.4 Irwin&Vijay, PSU, 2003
 Complementary CMOS
 Complementary CMOS logic gates
– nMOS pull-down network pMOS

– pMOS pull-up network pull-up

network
inputs
– a.k.a. static CMOS output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

1: Circuits & Layout CMOS VLSI Design 4th Ed. 5

 Static Complementary CMOS
 Pull-up network (PUN) and pull-down network (PDN)

VDD
PMOS transistors only
In1
pull-up: make a connection from VDD to F
In2 PUN
when F(In1,In2,…InN) = 1
InN
F(In1,In2,…InN)
In1
pull-down: make a connection from F to
In2 PDN
GND when F(In1,In2,…InN) = 0
InN
NMOS transistors only

PUN and PDN are dual logic networks

CSE477 L06 Static CMOS Logic.6 Irwin&Vijay, PSU, 2003

 Threshold Drops

VDD VDD
PUN

VDD

0→ 0→

CL CL

PDN VDD → VDD →

CL CL
VDD

CSE477 L06 Static CMOS Logic.7 Irwin&Vijay, PSU, 2003

 Threshold Drops

VDD VDD
PUN
S D
VDD

D 0 → VDD S 0 → VDD - VTn

VGS
CL CL

PDN VDD → 0 VDD → |VTp|

VGS
D CL S CL
VDD

S D

CSE477 L06 Static CMOS Logic.8 Irwin&Vijay, PSU, 2003

 Construction of PDN
 NMOS devices in series implement a NAND function

A•B
A

 NMOS devices in parallel implement a NOR function

A+B
A B

CSE477 L06 Static CMOS Logic.9 Irwin&Vijay, PSU, 2003

 Dual PUN and PDN
 PUN and PDN are dual networks
 DeMorgan’s theorems

A+B=A•B [!(A + B) = !A • !B or !(A | B) = !A & !B]

A•B=A+B [!(A • B) = !A + !B or !(A & B) = !A | !B]

 a parallel connection of transistors in the PUN corresponds to a

series connection of the PDN

 Complementary gate is naturally inverting (NAND,

NOR, AOI, OAI)
 Number of transistors for an N-input logic gate is 2N

CSE477 L06 Static CMOS Logic.10 Irwin&Vijay, PSU, 2003

 Series and Parallel
nMOS: 1 = ON
a a a a
 g1
a
0 0 1 1

pMOS: 0 = ON
g2
 b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON

 Series: both must be ON a a a a a

 Parallel: either can be ON g1

g2
0

0
0

1
1

0
1

1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

1: Circuits & Layout CMOS VLSI Design 4th Ed. 11

Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
 Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel

1: Circuits & Layout CMOS VLSI Design 4th Ed. 12

 Static CMOS Circuits
N and P channel networks implement logic functions
– Each network Connected between Output and VDD or VSS

1: Circuits & Layout CMOS VLSI Design 4th Ed. 13

 CMOS NAND

A B F
0 0 1
A B
0 1 1
1 0 1
A•B
1 1 0
A

A
B

CSE477 L06 Static CMOS Logic.14 Irwin&Vijay, PSU, 2003

 CMOS NOR

A B F
B
0 0 1
A 0 1 0
1 0 0
A+B
1 1 0
A B

A
B

CSE477 L06 Static CMOS Logic.15 Irwin&Vijay, PSU, 2003

 Compound Gates
 Compound gates can do any inverting function
 Ex:
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)

1: Circuits & Layout CMOS VLSI Design 4th Ed. 16

 Layout of Complex Gate

1: Circuits & Layout CMOS VLSI Design 4th Ed. 17

 Example: O3AI


A
B
C D
Y
D
A B C

1: Circuits & Layout CMOS VLSI Design 4th Ed. 18

 Practice 1
 OUT = D + A • (B + C)
B
A
C

A
D
B C

1: Circuits & Layout CMOS VLSI Design 4th Ed. 19

 Complex CMOS Gate

B
A
C

D
OUT = !(D + A • (B + C))
A
D
B C

CSE477 L06 Static CMOS Logic.20 Irwin&Vijay, PSU, 2003

 Practice 1
OUT = D + A • (B + C) VDD VDD

C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

1: Circuits & Layout CMOS VLSI Design 4th Ed. 21

 Standard Cell Layout Methodology

Routing
channel
VDD

signals

GND

What logic function is this?

CSE477 L06 Static CMOS Logic.22 Irwin&Vijay, PSU, 2003

 Practice 2


1: Circuits & Layout CMOS VLSI Design 4th Ed. 23

Duality is not Necessary

1: Circuits & Layout CMOS VLSI Design 4th Ed. 24

 Signal Strength
 Strength of signal
– How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
– But degraded or weak 1
 pMOS pass strong 1
– But degraded or weak 0
 Thus nMOS are best for pull-down network

1: Circuits & Layout CMOS VLSI Design 4th Ed. 25

 Gate Layout
 Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
 Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

1: Circuits & Layout CMOS VLSI Design 4th Ed. 26

 Example: Inverter

1: Circuits & Layout CMOS VLSI Design 4th Ed. 27

 Example: NAND3
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32 λ by 40 λ

1: Circuits & Layout CMOS VLSI Design 4th Ed. 28

 Stick Diagrams
 Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3

1: Circuits & Layout CMOS VLSI Design 4th Ed. 29

 Wiring Tracks
 A wiring track is the space required for a wire
– 4 λ width, 4 λ spacing from neighbor = 8 λ pitch
 Transistors also consume one wiring track

1: Circuits & Layout CMOS VLSI Design 4th Ed. 30

 Well spacing
 Wells must surround transistors by 6 λ
– Implies 12 λ between opposite transistor flavors
– Leaves room for one wire track

1: Circuits & Layout CMOS VLSI Design 4th Ed. 31

 Area Estimation
 Estimate area by counting wiring tracks
– Multiply by 8 to express in λ

40 λ

32 λ

1: Circuits & Layout CMOS VLSI Design 4th Ed. 32

 Example: O3AI
 Sketch a stick diagram for O3AI and estimate area
–

VDD
A B C D

6 tracks =
48 λ
Y

GND
5 tracks =
40 λ

1: Circuits & Layout CMOS VLSI Design 4th Ed. 33

 Stick Diagrams

Stick Diagrams

 Objectives:
• To know what is meant by stick diagram.
• To understand the capabilities and limitations of stick
diagram.
• To learn how to draw stick diagrams for a given MOS
circuit.

 Outcome:
• At the end of this module the students will be able
draw the stick diagram for simple MOS circuits.

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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Stick Diagrams

N+ N+

35
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Stick Diagrams

VDD
VDD
X

X
x x x
x Stick
Diagram X

Gnd Gnd

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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Stick Diagrams

VDD
VDD
X

X
x x x
x X

Gnd Gnd

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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Stick Diagrams

 VLSI design aims to translate circuit concepts

onto silicon.
 stick diagrams are a means of capturing
topography and layer information using
simple diagrams.
 Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
 Acts as an interface between symbolic circuit
and the actual layout.
38
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Stick Diagrams

 Does show all components/vias.

 It shows relative placement of components.
 Goes one step closer to the layout
 Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

39
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Stick Diagrams

 Does not show

• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..

40
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Stick Diagrams – Notations

Metal 1

poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.

Similarly for contacts, via, tub etc..

41
 Stick Diagrams

Stick Diagrams – Some rules

Rule 1.
When two or more ‘sticks’ of the same type cross
or touch each other that represents electrical
contact.

42
 Stick Diagrams

Stick Diagrams – Some rules

Rule 2.
When two or more ‘sticks’ of different type cross
or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).

43
 Stick Diagrams

Stick Diagrams – Some rules

Rule 3.
When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor.

44
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Stick Diagrams – Some rules

Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have
to be on the other side.

45
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

How to draw Stick Diagrams

46
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

47
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Power

A Out

Ground

48
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams
Contains no dimensions
Represents relative positions of transistors

VDD VDD

Inverter
NAND2

Out Out

In A B
GND GND

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 Stick Diagram Drawing : CMOS

Steps
1) Implement the expression in CMOS Logic
2) Find all Euler paths that cover the graph
3) Find n and p Euler paths that have same
labeling
4) Draw Stick diagram for optimization of
diffusion areas

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 Stick Diagrams

Logic Graph X PUN

A
j C
B C

X i VDD
X = C • (A + B)
C
i B j A

A B A
B PDN
C GND

PUN: Pull-up Network, PDN: Pull-down Network

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 Two Versions of C • (A + B)
A C B A B C

VDD VDD

X X

GND GND

Two Strips Line of Diffusions One Strip Line of Diffusions

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 Two Stick Layouts of !(C • (A + B))

crossover requiring vias

A C B A B C

VDD VDD

X X

GND GND

uninterrupted diffusion strip

CSE477 L06 Static CMOS Logic.53 Irwin&Vijay, PSU, 2003

 Consistent Euler Path
 An uninterrupted diffusion strip is possible only if there
exists a Euler path in the logic graph
 Euler path: a path through all nodes in the graph such that
each edge is visited once and only once.
X

X i VDD

B j A

GND A B C

 For a single poly strip for every input signal, the Euler
paths in the PUN and PDN must be consistent (the same)
CSE477 L06 Static CMOS Logic.54 Irwin&Vijay, PSU, 2003
 OAI22 Logic Graph

X PUN
A C

B D D C

X VDD
X = ((A+B)•(C+D))

C D
B A

A B PDN
A GND
B
C
D

CSE477 L06 Static CMOS Logic.55 Irwin&Vijay, PSU, 2003

 OAI22 Layout

A B D C

VDD

GND

 Some functions have no consistent Euler path like

x = !(a + bc + de) (but x = !(bc + a + de) does!)

CSE477 L06 Static CMOS Logic.56 Irwin&Vijay, PSU, 2003

Example: x = AB + CD
VDD
Euler paths {A B C D }
D C

A B

X = AB + CD
C B
VDD
D A
X
GND GND
A B C D
Stick diagram for ordering { A B C D } 57
EE141 Manufacturing
Example: x = ab+cd
x x

b c b c

x VDD x VD D

a d a d

GND GND

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

VD D

Euler Paths x
For both PUD
and PDN GND
a b c d
(c) stick diagram for ordering {a b c d}
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5
9

Layout of Complex Gate

1: Circuits & Layout

EE141 Manufacturing
CMOS Gate1

OUT = (D+E).A+B C

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 Minimize area-Eulers path

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 Euler graph APPROACH

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 63
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 Stick Diagram using Euler Graph Method

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Stick Diagram Optimum Gate Ordering ALL IN ONE
 Find a Euler path in both the pull-down tree
graph and the pull-up tree graph with
identical ordering of the inputs.
 Euler path: traverses each branch of the
graph exactly once!
 By reordering the input gates as E-D-A-B-C,
we can obtain an optimum layout of the
given CMOS gate with single actives for both
NMOS and PMOS devices (below).

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Stick diagram

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 Example: 1. Draw Logic Graph

 Identify each transistor

by a unique name of its
gate signal (A, B, C, D,
E in the example of
Figure 1).
 Identify each
connection to the
transistor by a unique
name (1,2,3,4 in the
example of Figure 1).

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EE141 Manufacturing
 Example: 2. Define Euler Path
 Euler paths are defined
by a path the traverses
each node in the path,
such that each edge is
visited only once.
 The path is defined by
the order of each
transistor name. If the
path traverses
transistor A then B then
C. Then the path name
is {A, B, C}
 The Euler path of the
Pull up network must be
the same as the path of
the Pull down network.
 Euler paths are not
necessarily unique.
 It may be necessary to
redefine the function to
find a Euler path.
F = E + (CD) + (AB) =
(AB) +E + (CD)
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 Example: 3. Connection label layout

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Example: 4. VDD, VSS and Output Labels

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 Example: 5. Interconnected

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 1) Z=ABCD
2) Z=A+B+C+D DRAW THE
3) Z=ABC+D STICK
DIAGRAMS
4) Z=(AB+C) D
5) Z=(A+B+C)D
6) Z=A(B+C)+DE

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EE141 Manufacturing
Lecture 4:
Delay

1. Delay definition
2. RC delay models
3. Linear delay models
5: DC and Transient Response CMOS VLSI Design 4th Ed. 2
 1. Delay Definitions
 tpdr: rising propagation delay
– From input to rising output
crossing VDD/2
 tpdf: falling propagation delay
– From input to falling output
crossing VDD/2
 tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
 tr: rise time
– From output crossing 0.2
VDD to 0.8 VDD
 tf: fall time
– From output crossing 0.8
VDD to 0.2 VDD

5: DC and Transient Response CMOS VLSI Design 4th Ed. 3

 1. Delay Definitions
 tcdr: rising contamination delay
– From input to rising output crossing VDD/2
 tcdf: falling contamination delay
– From input to falling output crossing VDD/2
 tcd: average contamination delay
– tcd = (tcdr + tcdf)/2

5: DC and Transient Response CMOS VLSI Design 4th Ed. 4

 1. Delay Definitions
The contamination delay, tcd, is the fastest that the logic gate
will change output based on a changed input.
The propagation delay, tpd, is the slowest that the logic gate
will change output based on a changed input.

5: DC and Transient Response CMOS VLSI Design 4th Ed. 5

 Arrival time
 Arrival time is the latest time at which each node in a block of logic
will switch
 The slack is the difference between the required and arrival times.
 Positive slack means that the circuit meets timing.
 Negative slack means that the circuit is not fast enough.

5: DC and Transient Response CMOS VLSI Design 4th Ed. 6

Simulated Inverter Delay
 Solving differential equations by hand is too hard
 SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
 But simulations take time to write, may hide insight
2.0

1.5

1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5

0.0

0.0 200p 400p 600p 800p 1n

t(s)

5: DC and Transient Response CMOS VLSI Design 4th Ed. 7

 Delay Estimation
 We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
 The step response usually looks like a 1st order RC
response with a decaying exponential.
 Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
 Characterize transistors by finding their effective R
– Depends on average current as gate switches

5: DC and Transient Response CMOS VLSI Design 4th Ed. 8

 Effective Resistance
 Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
 Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
 Too inaccurate to predict current at any given time
– But good enough to predict RC delay

5: DC and Transient Response CMOS VLSI Design 4th Ed. 9

 3. RC Delay Model
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d

5: DC and Transient Response CMOS VLSI Design 4th Ed. 10

 RC Values
 Capacitance
– C = Cg = Cs = Cd = 2 fF/µm of gate width in 0.6 µm
– Gradually decline to 1 fF/µm in nanometer techs.
 Resistance
– R ≈ 6 KΩ*µm in 0.6 µm process
– Improves with shorter channel lengths
 Unit transistors
– May refer to minimum contacted device (4/2 λ)
– Or maybe 1 µm wide device
– Doesn’t matter as long as you are consistent

5: DC and Transient Response CMOS VLSI Design 4th Ed. 11

 Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC

5: DC and Transient Response CMOS VLSI Design 4th Ed. 12

 Inverter Delay Estimate
 Estimate the delay of an inverter driving 4 identical
inverters – Fanout-of-4 (FO4) delay
 An important abstraction at higher levels of the design

d = 15RC
5: DC and Transient Response CMOS VLSI Design 4th Ed. 13
 Delay Model Comparison

5: DC and Transient Response CMOS VLSI Design 4th Ed. 14

 Example: 3-input NAND
 Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).

2 2 2

3
3

5: DC and Transient Response CMOS VLSI Design 4th Ed. 15

 3-input NAND Caps
 Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
9C
3 3C
5C 3C
3C
3
5C 3C
3C
3
5C 3C
3C

5: DC and Transient Response CMOS VLSI Design 4th Ed. 16

 Example: Sizing Complex Gate
Size the transistors in the cir-
cuit below so that it has the
same drive strength, in the
worst case, as an inverter that
has PW = 5 and NW = 3.
Use the smallest widths possi-
ble to achieve this ratio.

Note: if there are multiple

paths through a transistor, use
the size for the “worst-case” in-
put combination.

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics

 Example: Sizing Complex Gate
Size the transistors in the
circuit below so that it has
the same drive strength, in the
worst case, as an inverter that
has PW = 5 and NW = 3.
Use the smallest widths possi-
ble to achieve this ratio.

This solution does NOT use the

smallest widths
Note: if there are multiple
paths through a transistor, use
the size for the “worst-case” in-
put combination.

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics

 Example: Sizing of Complex Gate – Better Solution
Size the transistors in the
circuit below so that it has
the same drive strength, in the
worst case, as an inverter that
has PW = 5 and NW = 3.
Use the smallest widths possi-
ble to achieve this ratio.

Note: if there are multiple

paths through a transistor, use
the size for the “worst-case” in-
put combination.

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics

 Elmore Delay
 ON transistors look like resistors
 Pullup or pulldown network modeled as RC ladder
 Elmore delay of RC ladder
t pd ≈ ∑
nodes i
Ri −to − sourceCi

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N

R1 R2 R3 RN

C1 C2 C3 CN

5: DC and Transient Response CMOS VLSI Design 4th Ed. 20

 Elmore Delay

5: DC and Transient Response CMOS VLSI Design 4th Ed. 21

 Elmore Delay – Ex.1

5: DC and Transient Response CMOS VLSI Design 4th Ed. 22

 Elmore Delay – Ex.1

5: DC and Transient Response CMOS VLSI Design 4th Ed. 23

5: DC and Transient Response CMOS VLSI Design 4th Ed. 24
 Example: Elmore Delay Calculation

Delay from A to X:

Delay from A to Y:

Delay from A to Z:

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics

 Example: Elmore Delay Calculation, Cont’d

Delay from A to X: 40RC

Delay from A to Y: 38RC

Delay from A to Z: 35RC

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics

 Example: Delay of 2-Input NAND Using Elmore
Formulation

Estimate rising and falling propagation delays of a 2-input NAND

driving h identical gates

tpdr = (6 + 4h)RC
ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics
 Example: Delay of 2-Input NAND Using Elmore
Formulation

Estimate rising and falling propagation delays of a 2-input NAND

driving h identical gates

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics

 Example of Elmore Delay Calculation

Calculate the Elmore delay from C to F in the circuit. The widths

of the pass transistors are shown, and the inverters have
minimum-sized transistors

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics

 Example of Elmore Delay Calculation
Calculate the Elmore delay from C to F in the circuit. The widths
of the pass transistors are shown, and the inverters have
minimum-sized transistors

ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics

 Example: 3-input NAND
 Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2 2 2 Y
3 9C 5hC
n2
3 n1 3C
h copies
3 3C

t pdr = [(9 + 5h )C ](R ) + (3C )(R ) + (3C )(R ) t pdf = (3C )( R3 ) + (3C )( R3 + R3 ) + [(9 + 5h )C ]( R3 + R3 + R3 )
= (15 + 5h )RC = (12 + 5h )RC

5: DC and Transient Response CMOS VLSI Design 4th Ed. 31

 Delay Components
 Delay has two parts
– Parasitic delay
• 15 or 12 RC
• Independent of load
– Effort delay
• 5h RC
• Proportional to load capacitance

5: DC and Transient Response CMOS VLSI Design 4th Ed. 32

 Contamination Delay
 Best-case (contamination) delay can be substantially less than
propagation delay.
 Ex: If all three inputs fall simultaneously

2 2 2 Y
3 9C 5hC
n2
3 n1 3C

3 3C

R  5 
tcdr ( 9 + 5h ) C    =
=  3 + h  RC
3  3 

5: DC and Transient Response CMOS VLSI Design 4th Ed. 33

 Diffusion Capacitance
 We assumed contacted diffusion on every s / d.
 Good layout minimizes diffusion area
 Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C

3C 3C 3C 3 3C

5: DC and Transient Response CMOS VLSI Design 4th Ed. 34

 Isolated/Shared/Merged Diffusion
 Shared contacted diffusion can reduce the diffusion capacitance
 Un-contacted diffusion nodes can reduce more capacitance

Isolated Shared Merged

5: DC and Transient Response CMOS VLSI Design 4th Ed. 35

 Layout Comparison
 Which layout is better?

VDD VDD
A B A B

Y Y

GND GND

5: DC and Transient Response CMOS VLSI Design 4th Ed. 36

5: DC and Transient Response CMOS VLSI Design 4th Ed. 37
 Review
1. What are tpdr, tpdf, tf, tr, tcdr, tcdf?
2. Calculate arrive time of the following circuit:

20
10 40 30
30 40
3. Explain the delay estimation of a fanout-of-1 inverter (slide 10)
4. Explain the tpdr and tpdf delay estimation of 3-input NAND
driving h identical gates (slide 15).
5. Estimate delay for the gates: AOI21, OAI31
6. What is logical effort?
7. What is parasitic delay?
8. Estimate the delay of the following gate:
5: DC and Transient Response CMOS VLSI Design 4th Ed. 38
Lecture 5:
Logical
Effort
 Outline
 Logical Effort
 Delay in a Logic Gate
 Multistage Logic Networks
 Choosing the Best Number of Stages
 Example
 Summary

6: Logical Effort CMOS VLSI Design 4th Ed. 2

 Introduction
 Chip designers face a bewildering array of choices
– What is the best circuit topology for a function?
– How many stages of logic give least delay?
???
– How wide should the transistors be?

 Logical effort is a method to make these decisions

– Uses a simple model of delay
– Allows back-of-the-envelope calculations
– Helps make rapid comparisons between alternatives
– Emphasizes remarkable symmetries

6: Logical Effort CMOS VLSI Design 4th Ed. 3

 Example
 Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a register file.
A[3:0] A[3:0]
32 bits

 Decoder specifications:

4:16 Decoder

16 words
16
Register File
– 16 word register file
– Each word is 32 bits wide
– Each bit presents load of 3 unit-sized transistors
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
 Ben needs to decide:
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?
6: Logical Effort CMOS VLSI Design 4th Ed. 4
 Delay in a Logic Gate
 Express delays in process-independent unit d = d abs
 Delay has two components: d = f + p τ
τ = 3RC
 f: effort delay = gh (a.k.a. stage effort)
≈ 3 ps in 65 nm process
– Again has two components 60 ps in 0.6 µm process
 g: logical effort
– Measures relative ability of gate to deliver current
– g ≡ 1 for inverter
 h: electrical effort = Cout / Cin
– Ratio of output to input capacitance
– Sometimes called fanout
 p: parasitic delay
– Represents delay of gate driving no load
– Set by internal parasitic capacitance

6: Logical Effort CMOS VLSI Design 4th Ed. 5

 Delay Plots
d =f+p 2-input
= gh + p 6
NAND Inverter
g = 4/3

Normalized Delay: d
5 p=2
 What about d = (4/3)h + 2
4 g=1
NOR2? p=1
3 d=h+1

2 Effort Delay: f

1
Parasitic Delay: p
0
0 1 2 3 4 5

Electrical Effort:
h = Cout / Cin

6: Logical Effort CMOS VLSI Design 4th Ed. 6

Computing Logical Effort
 DEF: Logical effort is the ratio of the input
capacitance of a gate to the input capacitance of an
inverter delivering the same output current.
 Measure from delay vs. fanout plots
 Or estimate by counting transistor widths
2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1

Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3

6: Logical Effort CMOS VLSI Design 4th Ed. 7

 Catalog of Gates
 Logical effort of common gates

Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8

6: Logical Effort CMOS VLSI Design 4th Ed. 8

 Catalog of Gates
 Parasitic delay of common gates
– In multiples of pinv (≈1)
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8

6: Logical Effort CMOS VLSI Design 4th Ed. 9

Example: Ring Oscillator
 Estimate the frequency of an N-stage ring oscillator

Logical Effort: g=1 31 stage ring oscillator in

0.6 µm process has
Electrical Effort: h=1 frequency of ~ 200 MHz
Parasitic Delay: p=1
Stage Delay: d=2
Frequency: fosc = 1/(2*N*d) = 1/4N

6: Logical Effort CMOS VLSI Design 4th Ed. 10

 Example: FO4 Inverter
 Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort: g=1

Electrical Effort: h=4 The FO4 delay is about

Parasitic Delay: p=1 300 ps in 0.6 µm process

Stage Delay: d=5 15 ps in a 65 nm process

6: Logical Effort CMOS VLSI Design 4th Ed. 11

Multistage Logic Networks
 Logical effort generalizes to multistage networks
 Path Logical Effort G= gi ∏
 Path Electrical Effort
Cout-path
H=
Cin-path
 Path Effort =F ∏
= f ∏g h i i i

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

6: Logical Effort CMOS VLSI Design 4th Ed. 12

Multistage Logic Networks
 Logical effort generalizes to multistage networks
 Path Logical Effort G= ∏
gi

 Path Electrical Effort

Cout − path
H=
Cin − path
 Path Effort =F ∏
= f ∏g h i i i

 Can we write F = GH?

6: Logical Effort CMOS VLSI Design 4th Ed. 13

 Paths that Branch
 No! Consider paths that branch:
15
G =1 90
5
H = 90 / 5 = 18
GH = 18 15
90
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH

6: Logical Effort CMOS VLSI Design 4th Ed. 14

 Branching Effort
 Introduce branching effort
– Accounts for branching between stages in path
Con path + Coff path
b=
Con path
Note:
B = ∏ bi
∏h i = BH
 Now we compute the path effort
– F = GBH

6: Logical Effort CMOS VLSI Design 4th Ed. 15

 Multistage Delays
 Path Effort Delay DF = ∑ f i

 Path Parasitic Delay P = ∑ pi

 Path Delay D
= ∑=
d i DF + P

6: Logical Effort CMOS VLSI Design 4th Ed. 16

 Designing Fast Circuits
D
= ∑=
d i DF + P
 Delay is smallest when each stage bears same effort

fˆ g=
1
= i hi F N

 Thus minimum delay of N stage path is

1
D NF + P
= N

 This is a key result of logical effort

– Find fastest possible delay
– Doesn’t require calculating gate sizes

6: Logical Effort CMOS VLSI Design 4th Ed. 17

 Gate Sizes
 How wide should the gates be for least delay?

fˆ gh
= = g CCoutin
gi Couti
⇒ Cini =
fˆ
 Working backward, apply capacitance
transformation to find input capacitance of each gate
given load it drives.
 Check work by verifying input cap spec is met.

6: Logical Effort CMOS VLSI Design 4th Ed. 18

 Example: 3-stage path
 Select gate sizes x and y for least delay from A to B

y
x
45
A 8
x
y B
45

6: Logical Effort CMOS VLSI Design 4th Ed. 19

 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ
= 3
F 5
=
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4

6: Logical Effort CMOS VLSI Design 4th Ed. 20

 Example: 3-stage path
 Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

y
x
45
45
A P:
84 P:
x 4
N: 4 P:
y 12 B
N: 6 45
N: 3 45

6: Logical Effort CMOS VLSI Design 4th Ed. 21

 Best Number of Stages
 How many stages should a path use?
– Minimizing number of stages is not always fastest
 Example: drive 64-bit datapath with unit inverter
Initial Driver 1 1 1 1

8 4 2.8

D = NF1/N + P 16 8

= N(64)1/N + N
23

Datapath Load 64 64 64 64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest

6: Logical Effort CMOS VLSI Design 4th Ed. 22

 Derivation
 Consider adding inverters to end of path
– How many give least delay? N - n1 ExtraInverters
Logic Block:
n1 n1Stages

D= NF + ∑ pi + ( N − n1 ) pinv
1
N Path Effort F

i =1
∂D 1 1 1
− F N ln F N + F N + pinv =
= 0
∂N
1
 Define best stage effort ρ=F N

pinv + ρ (1 − ln ρ ) =
0

6: Logical Effort CMOS VLSI Design 4th Ed. 23

 Best Stage Effort
 pinv + ρ (1 − ln ρ ) =
0 has no closed-form solution

 Neglecting parasitics (pinv = 0), we find ρ = 2.718 (e)

 For pinv = 1, solve numerically for ρ = 3.59

6: Logical Effort CMOS VLSI Design 4th Ed. 24

 Sensitivity Analysis
 How sensitive is delay to using exactly the best
number of stages? 1.6
1.51

D(N) /D(N)
1.4
1.26
1.2 1.15

1.0

(ρ=6) (ρ =2.4)

0.0
0.5 0.7 1.0 1.4 2.0

N/ N

 2.4 < ρ < 6 gives delay within 15% of optimal

– We can be sloppy!
– I like ρ = 4

6: Logical Effort CMOS VLSI Design 4th Ed. 25

 Example, Revisited
 Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a register file.
A[3:0] A[3:0]
32 bits

 Decoder specifications:

4:16 Decoder

16 words
16
Register File
– 16 word register file
– Each word is 32 bits wide
– Each bit presents load of 3 unit-sized transistors
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
 Ben needs to decide:
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?
6: Logical Effort CMOS VLSI Design 4th Ed. 26
 Number of Stages
 Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B=8

 If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8

Number of Stages: N = log4F = 3.1

 Try a 3-stage design

6: Logical Effort CMOS VLSI Design 4th Ed. 27

 Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort: F = GBH = 154
Stage Effort: =fˆ F=
1/ 3
5.36
Path Delay: D= 3 fˆ + 1 + 4 + 1= 22.1
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

10 10 10 10 10 10 10 10

y z word[0]

96 units of wordline capacitance

y z word[15]

6: Logical Effort CMOS VLSI Design 4th Ed. 28

 Comparison
 Compare many alternatives with a spreadsheet
 D = N(76.8 G)1/N + P
Design N G P D
NOR4 1 3 4 234
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6

6: Logical Effort CMOS VLSI Design 4th Ed. 29

 Review of Definitions
Term Stage Path
number of stages 1 N
logical effort g G = ∏ gi
electrical effort h= Cout
Cin
H=
Cout-path
Cin-path
Con-path +Coff-path
branching effort b= Con-path B = ∏ bi
effort f = gh F = GBH

effort delay f DF = ∑ f i

parasitic delay p P = ∑ pi
delay d= f + p D
= ∑=
d i DF + P

6: Logical Effort CMOS VLSI Design 4th Ed. 30

 Method of Logical Effort
1) Compute path effort F = GBH
2) Estimate best number of stages N = log 4 F
3) Sketch path with N stages
1
4) Estimate least delay D NF + P
= N

5) Determine best stage effort ˆf = F N1

gi Couti
6) Find gate sizes Cini =
fˆ

6: Logical Effort CMOS VLSI Design 4th Ed. 31

 Limits of Logical Effort
 Chicken and egg problem
– Need path to compute G
– But don’t know number of stages without G
 Simplistic delay model
– Neglects input rise time effects
 Interconnect
– Iteration required in designs with wire
 Maximum speed only
– Not minimum area/power for constrained delay

6: Logical Effort CMOS VLSI Design 4th Ed. 32

 Summary
 Logical effort is useful for thinking of delay in circuits
– Numeric logical effort characterizes gates
– NANDs are faster than NORs in CMOS
– Paths are fastest when effort delays are ~4
– Path delay is weakly sensitive to stages, sizes
– But using fewer stages doesn’t mean faster paths
– Delay of path is about log4F FO4 inverter delays
– Inverters and NAND2 best for driving large caps
 Provides language for discussing fast circuits
– But requires practice to master

6: Logical Effort CMOS VLSI Design 4th Ed. 33

 Practice 1

6: Logical Effort CMOS VLSI Design 4th Ed. 34

 Practice 2

6: Logical Effort CMOS VLSI Design 4th Ed. 35

 Practice 2

6: Logical Effort CMOS VLSI Design 4th Ed. 36

 Practice 3

6: Logical Effort CMOS VLSI Design 4th Ed. 37

 Review
1. What are tpdr, tpdf, tf, tr, tcdr, tcdf?
2. Calculate arrive time of the following circuit:

20
10 40 30
30 40
3. Explain the delay estimation of a fanout-of-1 inverter (slide 10)
4. Explain the tpdr and tpdf delay estimation of 3-input NAND
driving h identical gates (slide 15).
5. Estimate delay for the gates: AOI21, OAI31
6. What is logical effort?
7. What is parasitic delay?
8. Estimate the delay of the following gate:
5: DC and Transient Response CMOS VLSI Design 4th Ed. 38
Lecture 5:
Power

1. Power and Energy

2. Dynamic Power
3. Static Power
4. Low Power Techniques
 1. Power and Energy
 Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.

 Instantaneous Power: P(t ) = I (t )V (t )

T
 Energy: E = ∫ P(t )dt
0
T
 Average Power: E 1
Pavg= = ∫
T T 0
P(t )dt

7: Power CMOS VLSI Design 4th Ed. 2

 Power in Circuit Elements
PVDD ( t ) = I DD ( t ) VDD

VR2 ( t )
P
=R ( t ) = I R (t ) R
2

∞ ∞
dV
EC I ( t )V ( t ) dt ∫ C V ( t ) dt
∫0= 0
dt
VC

∫ V ( t )dV
C=
0
1
2 CVC2

7: Power CMOS VLSI Design 4th Ed. 3

 2. Dynamic Power
Charging a Capacitor
 When the gate output rises
– Energy stored in capacitor is
2
EC = 12 CLVDD
– But energy drawn from the supply is
∞ ∞
dV
=EVDD I ( t )VDD dt
∫= ∫ CL VDD dt
0 0
dt
VDD

LVDD ∫ dV
2
= C= CLVDD
0
– Half the energy from VDD is dissipated in the
pMOS transistor as heat, other half stored in
capacitor
 When the gate output falls
– Energy in capacitor is dumped to GND
– Dissipated as heat in the nMOS transistor

7: Power CMOS VLSI Design 4th Ed. 4

 Sources of Power Dissipation

Dynamic Power Dissipation

Charging and discharging of load capacitances
“Short-circuit” current while both p- and n-MOS networks are
partially on

Static Dissipation
Subthreshold leakage (through OFF transistors)
Gate leakage through gate dielectric
Junction leakage from source/drain diffusion
Contention current in ratioed circuits

ECE Department, University of Texas at Austin Lecture 18. Design for Low Power
 Switching Waveforms
 Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz

7: Power CMOS VLSI Design 4th Ed. 6

 Switching Power
T
1
Pswitching = ∫ iDD (t )VDD dt
T 0
T
VDD
=
T 0∫ iDD (t )dt

VDD
= [Tfsw CVDD ] VDD
T iDD(t)
fsw

= CVDD 2 fsw
C

7: Power CMOS VLSI Design 4th Ed. 7

 Activity Factor
 Suppose the system clock frequency = f
 Let fsw = αf, where α = activity factor
– If the signal is a clock, α = 1
– If the signal switches once per cycle, α = ½

 Dynamic power:
Pswitching = α CVDD 2 f

7: Power CMOS VLSI Design 4th Ed. 8

Lowering Dynamic Power
Capacitance: Supply voltage:
Function of fan-out, Has been dropping with
wire length, transistor successive generations
sizes

Pdyn = CL VDD2 P0→1 f

Activity factor: Clock frequency:

How often, on average, do Increasing…
wires switch?

CMOS VLSI Design 4th Ed.

 Short Circuit Current
 When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
 Leads to a blip of “short circuit” current.
 < 10% of dynamic power if rise/fall times are
comparable for input and output
 We will generally ignore this component

7: Power CMOS VLSI Design 4th Ed. 10

Power Dissipation Sources
 Ptotal = Pdynamic + Pstatic
 Dynamic power: Pdynamic = Pswitching + Pshortcircuit
– Switching load capacitances
– Short-circuit current
 Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
– Subthreshold leakage
– Gate leakage
– Junction leakage
– Contention current

7: Power CMOS VLSI Design 4th Ed. 11

CMOS Energy & Power Equations

E = CL VDD2 P0→1 + tsc VDD Ipeak P0/1→1/0 + VDD Ileak

f = P * fclock

P = CL VDD2 f + tscVDD Ipeak f + VDD Ileak

Dynamic power Short-circuit Leakage power

(~90% today and power (~2% today and
decreasing (~8% today and increasing)
relatively) decreasing
absolutely)

CSE477 L12&13 Low Power.12 Irwin&Vijay, PSU, 2003

 Power and Energy Design Space

Constant Variable
Throughput/Latency Throughput/Latency
Energy Design Time Non-active Modules Run Time
Logic design
DFS, DVS
Active Reduced Vdd
Clock Gating (Dynamic Freq,
(Dynamic) TSizing Voltage
Scaling)
Multi-Vdd
Sleep Transistors
Multi-VT
Leakage Multi-Vdd
Stack effect Variable VT
(Standby) Variable VT
Pin ordering
Input control

CSE477 L12&13 Low Power.13 Irwin&Vijay, PSU, 2003

Estimate dynamic power
 1 billion transistor chip
– 50M logic transistors
• Average width: 12 λ
• Activity factor = 0.1
– 950M memory transistors
• Average width: 4 λ
• Activity factor = 0.02
– 1.0 V 65 nm process
– C = 1 fF/µm (gate) + 0.8 fF/µm (diffusion)
 Estimate dynamic power consumption @ 1 GHz.
Neglect wire capacitance and short-circuit current.

7: Power CMOS VLSI Design 4th Ed. 14

 Solution
(
Clogic = 50 × 10 6
) (12λ )( 0.025µ m / λ )(1.8 fF / µ m ) =
27 nF

( 950 ×106 ) ( 4λ )( 0.025µ m / λ )(1.8 fF / µ m ) =

Cmem = 171 nF
0.1Clogic + 0.02Cmem  (1.0 ) (1.0 GHz ) =
2
Pdynamic = 6.1 W

7: Power CMOS VLSI Design 4th Ed. 15

 Dynamic Power Reduction

P
 switching = α CV 2
DD f

 Try to minimize:
– Activity factor
– Capacitance
– Supply voltage
– Frequency

7: Power CMOS VLSI Design 4th Ed. 16

 Activity Factor Estimation
 Let Pi = Prob(node i = 1)
– Pi = 1-Pi
 αi = Pi * Pi
 Completely random data has P = 0.5 and α = 0.25
 Data is often not completely random
– e.g. upper bits of 64-bit words representing bank
account balances are usually 0
 Data propagating through ANDs and ORs has lower
activity factor
– Depends on design, but typically α ≈ 0.1

7: Power CMOS VLSI Design 4th Ed. 17

 Dynamic Power Consumption is Data Dependent
 Switching activity, P0→1, has two components
 A static component – function of the logic topology
 A dynamic component – function of the timing behavior (glitching)

Static transition probability

P0→1 = Pout=0 x Pout=1
2-input NOR Gate
= P0 x (1-P0)
A B Out
0 0 1
With input signal probabilities
0 1 0
PA=1 = 1/2
1 0 0 PB=1 = 1/2
1 1 0
NOR static transition probability
= 3/4 x 1/4 = 3/16
CSE477 L12&13 Low Power.18 Irwin&Vijay, PSU, 2003
 NOR Gate Transition Probabilities
 Switching activity is a strong function of the input signal
statistics
 PA and PB are the probabilities that inputs A and B are one

0
A B
CL PA
1 0 1
PB

P0→1 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB)

CSE477 L12&13 Low Power.19 Irwin&Vijay, PSU, 2003

 Switching Probability

7: Power CMOS VLSI Design 4th Ed. 20

 Example
 A 4-input AND is built out of two levels of gates
 Estimate the activity factor at each node if the inputs
have P = 0.5

7: Power CMOS VLSI Design 4th Ed. 21

 Transition Probabilities for Some Basic Gates

P0→1 = Pout=0 x Pout=1

NOR (1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB)
OR (1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB))
NAND PAPB x (1 - PAPB)
AND (1 - PAPB) x PAPB
XOR (1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB)
X
0.5 A
Z
0.5 B

For X: P0→1 = P0 x P1 = (1-PA) PA

= 0.5 x 0.5 = 0.25
For Z: P0→1 = P0 x P1 = (1-PXPB) PXPB
= (1 – (0.5 x 0.5)) x (0.5 x 0.5) = 3/16
CSE477 L12&13 Low Power.23 Irwin&Vijay, PSU, 2003
 Example
 Determine the activity factors at each node in the
circuit assuming the input probabilities
PA = PB = PC = PD = 0.5.

7: Power CMOS VLSI Design 4th Ed. 24

 Example
 Determine the activity factors at each node in the
circuit assuming the input probabilities
PA = PB = PC = PD = 0.5.

7: Power CMOS VLSI Design 4th Ed. 25

 Inter-signal Correlations
 Determining switching activity is complicated by the fact
that signals exhibit correlation in space and time
 reconvergent fan-out

(1-0.5)(1-0.5)x(1-(1-0.5)(1-0.5)) = 3/16
0.5 A
X
0.5 B
Z

(1- 3/16 x 0.5) x (3/16 x 0.5) = 0.085

Reconvergent

P(Z=1) = P(B=1) & P(A=1 | B=1)

 Have to use conditional probabilities

CSE477 L12&13 Low Power.26 Irwin&Vijay, PSU, 2003
 Logic Restructuring
 Logic restructuring: changing the topology of a logic
network to reduce transitions
AND: P0→1 = P0 x P1 = (1 - PAPB) x PAPB
3/16
0.5 A Y
0.5 (1-0.25)*0.25 = 3/16
A W 7/64 0.5 B 15/256
B X F
15/256 0.5
0.5 C C
0.5 D F
0.5 0.5 D Z
3/16

Chain implementation has a lower overall switching activity

than the tree implementation for random inputs
Ignores glitching effects

CSE477 L12&13 Low Power.27 Irwin&Vijay, PSU, 2003

 Input Ordering

(1-0.5x0.2)x(0.5x0.2)=0.09 (1-0.2x0.1)x(0.2x0.1)=0.0196
0.5 0.2
A B X
X
B C
F 0.1 A F
0.2 C
0.1 0.5

Which is better wrt transition probabilities?

Beneficial to postpone the introduction of signals with a

high transition rate (signals with signal probability
close to 0.5)

CSE477 L12&13 Low Power.29 Irwin&Vijay, PSU, 2003

 Glitching in Static CMOS Networks
 Gates have a nonzero propagation delay resulting in
spurious transitions or glitches (dynamic hazards)
 glitch: node exhibits multiple transitions in a single cycle before
settling to the correct logic value

A X
B
C Z

ABC 101 000

Unit Delay
CSE477 L12&13 Low Power.31 Irwin&Vijay, PSU, 2003
 Glitching in an RCA

Cin

S15 S14 S2 S1 S0

CSE477 L12&13 Low Power.32 Irwin&Vijay, PSU, 2003

 Balanced Delay Paths to Reduce Glitching
 Glitching is due to a mismatch in the path lengths in
the logic network; if all input signals of a gate change
simultaneously, no glitching occurs

0 0
0 F1 1 0 F1 1
0 F2 2
F3
0 F3 0
0 F2 1

So equalize the lengths of timing paths through logic

CSE477 L12&13 Low Power.33 Irwin&Vijay, PSU, 2003

 3. Static Power
 Static power is consumed even when chip is
quiescent.
– Leakage draws power from nominally OFF
devices
– Ratioed circuits burn power in fight between ON
transistors

7: Power CMOS VLSI Design 4th Ed. 34

 Leakage (Static) Power Consumption

VDD Ileakage

Vout
Drain junction
leakage

Gate leakage Subthreshold current

Sub-threshold current is the dominant factor.

All increase exponentially with temperature!

CSE477 L12&13 Low Power.35 Irwin&Vijay, PSU, 2003

 Leakage Current Mechanisms

I1 p-n junction reverse

bias current (drain
I7 I8 junction)
Polysilicon I2 weak inversion
Gate oxide
Gate (subthreshold current)
I3 DIBL
Source Drain
I4 GIDL
n+ I I I n+
2 3 6
I1 I5 punchthrough
I5
I4
p substrate I6 narrow width effect
Bulk (Body)
I7 gate oxide tunneling
(gate leakage)
I8 hot carrier injection

CSE477 L12&13 Low Power.36 Irwin&Vijay, PSU, 2003

 Static Power Example
 Revisit power estimation for 1 billion transistor chip
 Estimate static power consumption
– Subthreshold leakage
• Normal Vt: 100 nA/µm
• High Vt: 10 nA/µm
• High Vt used in all memories and in 95% of
logic gates
– Gate leakage 5 nA/µm
– Junction leakage negligible

7: Power CMOS VLSI Design 4th Ed. 37

 Solution

( 50 ×106 ) (12λ )( 0.025µ m / λ )( 0.05) =

Wnormal-Vt = 0.75 ×106 µ m

Whigh-Vt = ( 50 ×106 ) (12λ )( 0.95 ) + ( 950 ×106 ) ( 4λ )  ( 0.025µ m / λ ) = 109.25 ×106 µ m

I sub = Wnormal-Vt ×100 nA/µ m+Whigh-Vt ×10 nA/µ m  / 2 =

584 mA

( )
I gate=  Wnormal-Vt + Whigh-Vt × 5 nA/µ m  / 2= 275 mA
 
Pstatic = ( 584 mA + 275 mA )(1.0 V ) = 859 mW

7: Power CMOS VLSI Design 4th Ed. 38

 Subthreshold Leakage
 For Vds > 50 mV Typical values in 65 nm
Vgs +η (Vds −VDD ) − kγ Vsb Ioff = 100 nA/µm @ Vt = 0.3 V
I sub ≈ I off 10 S Ioff = 10 nA/µm @ Vt = 0.4 V
Ioff = 1 nA/µm @ Vt = 0.5 V
η = 0.1
 Ioff = leakage at Vgs = 0, Vds = VDD
kγ = 0.1
S = 100 mV/decade

7: Power CMOS VLSI Design 4th Ed. 39

 Stack Effect
 Series OFF transistors have less leakage
– Vx > 0, so N2 has negative Vgs
η (Vx −VDD ) −Vx +η ( (VDD −Vx ) −VDD ) − kγ Vx

= off 10
I sub I= I off 10
S S
    
N2 N1

ηVDD
Vx =
1 + 2η + kγ
 1+η + kγ 
−ηVDD  
 1+ 2η + kγ  −ηVDD
 
=I sub I off 10 S
≈ I off 10 S

– Leakage through 2-stack reduces ~10x

– Leakage through 3-stack reduces further

7: Power CMOS VLSI Design 4th Ed. 40

 Leakage Control
 Leakage and delay trade off
– Aim for low leakage in sleep and low delay in
active mode
 To reduce leakage:
– Increase Vt: multiple Vt
• Use low Vt only in critical circuits
– Increase Vs: stack effect
• Input vector control in sleep
– Decrease Vb
• Reverse body bias in sleep
• Or forward body bias in active mode

7: Power CMOS VLSI Design 4th Ed. 41

 Gate Leakage
 Extremely strong function of tox and Vgs
– Negligible for older processes
– Approaches subthreshold leakage at 65 nm and
below in some processes
 An order of magnitude less for pMOS than nMOS
 Control leakage in the process using tox > 10.5 Å
– High-k gate dielectrics help
– Some processes provide multiple tox
• e.g. thicker oxide for 3.3 V I/O transistors
 Control leakage in circuits by limiting VDD

7: Power CMOS VLSI Design 4th Ed. 42

 NAND3 Leakage Example
 100 nm process
Ign = 6.3 nA Igp = 0
Ioffn = 5.63 nA Ioffp = 9.3 nA

Data from [Lee03]

7: Power CMOS VLSI Design 4th Ed. 43

 Junction Leakage
 From reverse-biased p-n junctions
– Between diffusion and substrate or well
 Ordinary diode leakage is negligible
 Band-to-band tunneling (BTBT) can be significant
– Especially in high-Vt transistors where other
leakage is small
– Worst at Vdb = VDD
 Gate-induced drain leakage (GIDL) exacerbates
– Worst for Vgd = -VDD (or more negative)

7: Power CMOS VLSI Design 4th Ed. 44

 Power and Energy Design Space

Constant Variable
Throughput/Latency Throughput/Latency
Energy Design Time Non-active Modules Run Time
Logic design
DFS, DVS
Active Reduced Vdd
Clock Gating (Dynamic Freq,
(Dynamic) TSizing Voltage
Scaling)
Multi-Vdd
Sleep Transistors
Multi-VT
Leakage Multi-Vdd
Stack effect Variable VT
(Standby) Variable VT
Pin ordering
Input control

CSE477 L12&13 Low Power.45 Irwin&Vijay, PSU, 2003

4. Low Power Methodology
 Resonant circuits: reduce switching power consumption
 Clock gating: turn off the clock to registers in unused
blocks to reduce the activity
 Reduce capacitance: wire/gate capacitance
 Dynamic Voltage Scaling: Adjust VDD and f according
to workload
 Power gating: Turn OFF power to blocks when they are
idle to save leakage

7: Power CMOS VLSI Design 4th Ed. 46

 Resonant Circuits
 Letting energy slosh back and forth between storage
elements such as capacitors and inductors rather
than dumping the energy to ground.
 The technique is best suited to applications such as
clocks that operate at a constant frequency.

7: Power CMOS VLSI Design 4th Ed. 47

 Clock Gating
 The best way to reduce the activity is to turn off the
clock to registers in unused blocks
– Saves clock activity (α = 1)
– Eliminates all switching activity in the block
– Requires determining if block will be used

7: Power CMOS VLSI Design 4th Ed. 48

 Capacitance
 Gate capacitance
– Fewer stages of logic
– Small gate sizes
 Wire capacitance
– Good floorplanning to keep communicating
blocks close to each other
– Drive long wires with inverters or buffers rather
than complex gates

7: Power CMOS VLSI Design 4th Ed. 49

 Voltage / Frequency
 Run each block at the lowest possible voltage and
frequency that meets performance requirements
 Voltage Domains
– Provide separate supplies to different blocks
– Level converters required when crossing
from low to high VDD domains

 Dynamic Voltage Scaling

– Adjust VDD and f according to
workload

7: Power CMOS VLSI Design 4th Ed. 50

 Power Gating
 Turn OFF power to blocks when they are idle to
save leakage
– Use virtual VDD (VDDV)
– Gate outputs to prevent
invalid logic levels to next block

 Voltage drop across sleep transistor degrades

performance during normal operation
– Size the transistor wide enough to minimize
impact
 Switching wide sleep transistor costs dynamic power
– Only justified when circuit sleeps long enough
7: Power CMOS VLSI Design 4th Ed. 51
 Low Power Design
 Reduce dynamic power
– α: clock gating, sleep mode
– C: small transistors (esp. on clock), short wires
– VDD: lowest suitable voltage
– f: lowest suitable frequency
 Reduce static power
– Selectively use ratioed circuits
– Selectively use low Vt devices
– Leakage reduction: stacked devices, body bias,
low temperature, …

D. Z. Pan CMOS VLSI Design 4th Ed.

Low Power Design Techniques

Algorithm

Architecture

Logic/circuit

Technology/circuit

 Need combination of techniques at all levels

D. Z. Pan CMOS VLSI Design 4th Ed.

 Review
1. What is dynamic power?
2. What is static power?
3. Why does switching probability affect to dynamic power?
4. Describe some low power techniques
5. Describe resonant circuits
6. What are difference between clock gating and power gating
7. Calculate activity factors of the following circuits:
(PA = PB = PC = PD = 0.5)

7: Power CMOS VLSI Design 4th Ed. 54